[PowerPC] Implement vector shift builtins - llvm portion

This patch corresponds to review https://reviews.llvm.org/D26095.
Committing on behalf of Tony Jiang.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285681 91177308-0d34-0410-b5e6-96231b3b80d8

Author: nemanjai

include/llvm/IR/IntrinsicsPowerPC.td

@@ -622,6 +622,8 @@ def int_ppc_altivec_vsl   : PowerPC_Vec_WWW_Intrinsic<"vsl">;
 def int_ppc_altivec_vslo  : PowerPC_Vec_WWW_Intrinsic<"vslo">;
 
 def int_ppc_altivec_vslb  : PowerPC_Vec_BBB_Intrinsic<"vslb">;
+def int_ppc_altivec_vslv  : PowerPC_Vec_BBB_Intrinsic<"vslv">;
+def int_ppc_altivec_vsrv  : PowerPC_Vec_BBB_Intrinsic<"vsrv">;
 def int_ppc_altivec_vslh  : PowerPC_Vec_HHH_Intrinsic<"vslh">;
 def int_ppc_altivec_vslw  : PowerPC_Vec_WWW_Intrinsic<"vslw">;
 

lib/Target/PowerPC/PPCInstrAltivec.td

@@ -1342,8 +1342,10 @@ def VRLDNM : VX1_VT5_VA5_VB5<453, "vrldnm", []>;
 def VRLDMI : VX1_VT5_VA5_VB5<197, "vrldmi", []>;
 
 // Vector Shift Left/Right
-def VSLV : VX1_VT5_VA5_VB5<1860, "vslv", []>;
-def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv", []>;
+def VSLV : VX1_VT5_VA5_VB5<1860, "vslv",
+                           [(set v16i8 : $vD, (int_ppc_altivec_vslv v16i8 : $vA, v16i8 : $vB))]>;
+def VSRV : VX1_VT5_VA5_VB5<1796, "vsrv",
+                           [(set v16i8 : $vD, (int_ppc_altivec_vsrv v16i8 : $vA, v16i8 : $vB))]>;
 
 // Vector Multiply-by-10 (& Write Carry) Unsigned Quadword
 def VMUL10UQ   : VXForm_BX<513, (outs vrrc:$vD), (ins vrrc:$vA),

test/CodeGen/PowerPC/vsx-p9.ll

@@ -167,4 +167,27 @@ entry:
 ; Function Attrs: nounwind readnone
 declare <2 x double> @llvm.ppc.vsx.xviexpdp(<2 x i64>, <2 x i64>)
 
+define <16 x i8> @testVSLV(<16 x i8> %a, <16 x i8> %b) {
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.altivec.vslv(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %0
+; CHECK-LABEL: testVSLV
+; CHECK: vslv 2, 2, 3
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <16 x i8> @llvm.ppc.altivec.vslv(<16 x i8>, <16 x i8>)
+
+; Function Attrs: nounwind readnone
+define <16 x i8> @testVSRV(<16 x i8> %a, <16 x i8> %b) {
+entry:
+  %0 = tail call <16 x i8> @llvm.ppc.altivec.vsrv(<16 x i8> %a, <16 x i8> %b)
+  ret <16 x i8> %0
+; CHECK-LABEL: testVSRV
+; CHECK: vsrv 2, 2, 3
+; CHECK: blr
+}
+; Function Attrs: nounwind readnone
+declare <16 x i8> @llvm.ppc.altivec.vsrv(<16 x i8>, <16 x i8>)
+
 declare void @sink(...)