[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.

This re-applies r268760, reverted in r268794.
Fixes http://llvm.org/PR27670

The original imp-defs assertion was way overzealous: forward all
implicit operands, except imp-defs of the new super-reg def (r268787
for GR64, but also possible for GR16->GR32), or imp-uses of the new
super-reg use.
While there, mark the source use as Undef, and add an imp-use of the
old source reg: that should cover any case of dead super-regs.

At the stage the pass runs, flags are unlikely to matter anyway;
still, let's be as correct as possible.

Also add MIR tests for the various interesting cases.

Original commit message:
Codesize is less (16) or equal (8), and we avoid partial
dependencies.

Differential Revision: http://reviews.llvm.org/D19999

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268831 91177308-0d34-0410-b5e6-96231b3b80d8

Author: ahmedbougacha

lib/Target/X86/X86FixupBWInsts.cpp

@@ -90,6 +90,11 @@ class FixupBWInstPass : public MachineFunctionPass {
   /// OK, otherwise return nullptr.
   MachineInstr *tryReplaceLoad(unsigned New32BitOpcode, MachineInstr *MI) const;
 
+  /// Change the MachineInstr \p MI into the equivalent 32-bit copy if it is
+  /// safe to do so.  Return the replacement instruction if OK, otherwise return
+  /// nullptr.
+  MachineInstr *tryReplaceCopy(MachineInstr *MI) const;
+
 public:
   static char ID;
 
@@ -226,6 +231,42 @@ MachineInstr *FixupBWInstPass::tryReplaceLoad(unsigned New32BitOpcode,
   return MIB;
 }
 
+MachineInstr *FixupBWInstPass::tryReplaceCopy(MachineInstr *MI) const {
+  assert(MI->getNumExplicitOperands() == 2);
+  auto &OldDest = MI->getOperand(0);
+  auto &OldSrc = MI->getOperand(1);
+
+  unsigned NewDestReg;
+  if (!getSuperRegDestIfDead(MI, NewDestReg))
+    return nullptr;
+
+  unsigned NewSrcReg = getX86SubSuperRegister(OldSrc.getReg(), 32);
+
+  // This is only correct if we access the same subregister index: otherwise,
+  // we could try to replace "movb %ah, %al" with "movl %eax, %eax".
+  auto *TRI = &TII->getRegisterInfo();
+  if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) !=
+      TRI->getSubRegIndex(NewDestReg, OldDest.getReg()))
+    return nullptr;
+
+  // Safe to change the instruction.
+  // Don't set src flags, as we don't know if we're also killing the superreg.
+  // However, the superregister might not be defined; make it explicit that
+  // we don't care about the higher bits by reading it as Undef, and adding
+  // an imp-use on the original subregister.
+  MachineInstrBuilder MIB =
+      BuildMI(*MF, MI->getDebugLoc(), TII->get(X86::MOV32rr), NewDestReg)
+          .addReg(NewSrcReg, RegState::Undef)
+          .addReg(OldSrc.getReg(), RegState::Implicit);
+
+  // Drop imp-defs/uses that would be redundant with the new def/use.
+  for (auto &Op : MI->implicit_operands())
+    if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg))
+      MIB.addOperand(Op);
+
+  return MIB;
+}
+
 void FixupBWInstPass::processBasicBlock(MachineFunction &MF,
                                         MachineBasicBlock &MBB) {
 
@@ -272,6 +313,15 @@ void FixupBWInstPass::processBasicBlock(MachineFunction &MF,
       NewMI = tryReplaceLoad(X86::MOVZX32rm16, MI);
       break;
 
+    case X86::MOV8rr:
+    case X86::MOV16rr:
+      // Always try to replace 8/16 bit copies with a 32 bit copy.
+      // Code size is either less (16) or equal (8), and there is sometimes a
+      // perf advantage from eliminating a false dependence on the upper portion
+      // of the register.
+      NewMI = tryReplaceCopy(MI);
+      break;
+
     default:
       // nothing to do here.
       break;

test/CodeGen/X86/2011-06-14-PreschedRegalias.ll

@@ -6,7 +6,7 @@
 define i8 @f(i8 %v1, i8 %v2) nounwind {
 entry:
 ; CHECK: callq
-; CHECK: movb %{{.*}}, %al
+; CHECK: movl %{{.*}}, %eax
 ; CHECK: mulb
 ; CHECK: mulb
         %rval = tail call i8 @bar() nounwind

test/CodeGen/X86/anyext.ll

@@ -39,7 +39,7 @@ define i32 @bar(i32 %p, i16 zeroext %x) nounwind {
 ; X64-LABEL: bar:
 ; X64:       # BB#0:
 ; X64-NEXT:    xorl %edx, %edx
-; X64-NEXT:    movw %di, %ax
+; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    divw %si
 ; X64-NEXT:    andl $1, %eax
 ; X64-NEXT:    retq

test/CodeGen/X86/avx512-calling-conv.ll

@@ -461,7 +461,7 @@ define i32 @test12(i32 %a1, i32 %a2, i32 %b1) {
 ; KNL_X32-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; KNL_X32-NEXT:    movl %edi, (%esp)
 ; KNL_X32-NEXT:    calll _test11
-; KNL_X32-NEXT:    movb %al, %bl
+; KNL_X32-NEXT:    movl %eax, %ebx
 ; KNL_X32-NEXT:    movzbl %bl, %eax
 ; KNL_X32-NEXT:    movl %eax, {{[0-9]+}}(%esp)
 ; KNL_X32-NEXT:    movl %esi, {{[0-9]+}}(%esp)

test/CodeGen/X86/avx512-mask-op.ll

@@ -81,7 +81,7 @@ define i16 @mand16(i16 %x, i16 %y) {
 ; CHECK-NEXT:    xorl %esi, %eax
 ; CHECK-NEXT:    andl %esi, %edi
 ; CHECK-NEXT:    orl %eax, %edi
-; CHECK-NEXT:    movw %di, %ax
+; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
   %ma = bitcast i16 %x to <16 x i1>
   %mb = bitcast i16 %y to <16 x i1>

test/CodeGen/X86/avx512-select.ll

@@ -72,7 +72,7 @@ define i8 @select05(i8 %a.0, i8 %m) {
 ; CHECK-LABEL: select05:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    orl %esi, %edi
-; CHECK-NEXT:    movb %dil, %al
+; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
   %mask = bitcast i8 %m to <8 x i1>
   %a = bitcast i8 %a.0 to <8 x i1>
@@ -102,7 +102,7 @@ define i8 @select06(i8 %a.0, i8 %m) {
 ; CHECK-LABEL: select06:
 ; CHECK:       ## BB#0:
 ; CHECK-NEXT:    andl %esi, %edi
-; CHECK-NEXT:    movb %dil, %al
+; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
   %mask = bitcast i8 %m to <8 x i1>
   %a = bitcast i8 %a.0 to <8 x i1>

test/CodeGen/X86/avx512dq-mask-op.ll

@@ -36,7 +36,7 @@ define i8 @mand8(i8 %x, i8 %y) {
 ; CHECK-NEXT:    xorl %esi, %eax
 ; CHECK-NEXT:    andl %esi, %edi
 ; CHECK-NEXT:    orl %eax, %edi
-; CHECK-NEXT:    movb %dil, %al
+; CHECK-NEXT:    movl %edi, %eax
 ; CHECK-NEXT:    retq
   %ma = bitcast i8 %x to <8 x i1>
   %mb = bitcast i8 %y to <8 x i1>

test/CodeGen/X86/cmovcmov.ll

@@ -250,14 +250,14 @@ attributes #0 = { nounwind }
 ; CMOV-DAG: movb $20, %al
 ; CMOV-DAG: movb $20, %dl
 ; CMOV:   jl [[BB0:.LBB[0-9_]+]]
-; CMOV:   movb %cl, %dl
+; CMOV:   movl %ecx, %edx
 ; CMOV: [[BB0]]:
 ; CMOV:   jg [[BB1:.LBB[0-9_]+]]
-; CMOV:   movb %dl, %al
+; CMOV:   movl %edx, %eax
 ; CMOV: [[BB1]]:
 ; CMOV:   testl %edi, %edi
 ; CMOV:   je [[BB2:.LBB[0-9_]+]]
-; CMOV:   movb %dl, %al
+; CMOV:   movl %edx, %eax
 ; CMOV: [[BB2]]:
 ; CMOV:   movb %al, g8(%rip)
 ; CMOV:   retq

test/CodeGen/X86/fixup-bw-copy.ll

@@ -0,0 +1,70 @@
+; NOTE: Assertions have been autogenerated by update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -fixup-byte-word-insts=1 -mtriple=x86_64-- < %s | FileCheck --check-prefix=X64 --check-prefix=BWON64 %s
+; RUN: llc -verify-machineinstrs -fixup-byte-word-insts=0 -mtriple=x86_64-- < %s | FileCheck --check-prefix=X64 --check-prefix=BWOFF64 %s
+; RUN: llc -verify-machineinstrs -fixup-byte-word-insts=1 -mtriple=i386-- < %s | FileCheck --check-prefix=X32 --check-prefix=BWON32 %s
+; RUN: llc -verify-machineinstrs -fixup-byte-word-insts=0 -mtriple=i386-- < %s | FileCheck --check-prefix=X32 --check-prefix=BWOFF32 %s
+
+target datalayout = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"
+
+define i8 @test_movb(i8 %a0) {
+; BWON64-LABEL: test_movb:
+; BWON64:       # BB#0:
+; BWON64-NEXT:    movl %edi, %eax
+; BWON64-NEXT:    retq
+;
+; BWOFF64-LABEL: test_movb:
+; BWOFF64:       # BB#0:
+; BWOFF64-NEXT:    movb %dil, %al
+; BWOFF64-NEXT:    retq
+;
+; X32-LABEL: test_movb:
+; X32:       # BB#0:
+; X32-NEXT:    movb {{[0-9]+}}(%esp), %al
+; X32-NEXT:    retl
+  ret i8 %a0
+}
+
+define i16 @test_movw(i16 %a0) {
+; BWON64-LABEL: test_movw:
+; BWON64:       # BB#0:
+; BWON64-NEXT:    movl %edi, %eax
+; BWON64-NEXT:    retq
+;
+; BWOFF64-LABEL: test_movw:
+; BWOFF64:       # BB#0:
+; BWOFF64-NEXT:    movw %di, %ax
+; BWOFF64-NEXT:    retq
+;
+; BWON32-LABEL: test_movw:
+; BWON32:       # BB#0:
+; BWON32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; BWON32-NEXT:    retl
+;
+; BWOFF32-LABEL: test_movw:
+; BWOFF32:       # BB#0:
+; BWOFF32-NEXT:    movw {{[0-9]+}}(%esp), %ax
+; BWOFF32-NEXT:    retl
+  ret i16 %a0
+}
+
+; Verify we don't mess with H-reg copies (only generated in 32-bit mode).
+define i8 @test_movb_hreg(i16 %a0) {
+; X64-LABEL: test_movb_hreg:
+; X64:       # BB#0:
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    shrl $8, %eax
+; X64-NEXT:    addb %dil, %al
+; X64-NEXT:    retq
+;
+; X32-LABEL: test_movb_hreg:
+; X32:       # BB#0:
+; X32-NEXT:    movzwl {{[0-9]+}}(%esp), %eax
+; X32-NEXT:    addb %al, %ah
+; X32-NEXT:    movb %ah, %al
+; X32-NEXT:    retl
+  %tmp0 = trunc i16 %a0 to i8
+  %tmp1 = lshr i16 %a0, 8
+  %tmp2 = trunc i16 %tmp1 to i8
+  %tmp3 = add i8 %tmp0, %tmp2
+  ret i8 %tmp3
+}

test/CodeGen/X86/fixup-bw-copy.mir

@@ -0,0 +1,156 @@
+# RUN: llc -run-pass x86-fixup-bw-insts -mtriple=x86_64-- -o /dev/null %s 2>&1 | FileCheck %s
+
+# Verify that we correctly deal with the flag edge cases when replacing
+# copies by bigger copies, which is a pretty unusual transform.
+
+--- |
+  target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
+
+  define i8 @test_movb_killed(i8 %a0) {
+    ret i8 %a0
+  }
+
+  define i8 @test_movb_impuse(i8 %a0) {
+    ret i8 %a0
+  }
+
+  define i8 @test_movb_impdef_gr64(i8 %a0) {
+    ret i8 %a0
+  }
+
+  define i8 @test_movb_impdef_gr32(i8 %a0) {
+    ret i8 %a0
+  }
+
+  define i8 @test_movb_impdef_gr16(i8 %a0) {
+    ret i8 %a0
+  }
+
+  define i16 @test_movw_impdef_gr32(i16 %a0) {
+    ret i16 %a0
+  }
+
+  define i16 @test_movw_impdef_gr64(i16 %a0) {
+    ret i16 %a0
+  }
+
+...
+
+---
+name:            test_movb_killed
+allVRegsAllocated: true
+isSSA:           false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: %edi
+
+    ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
+    %al = MOV8rr killed %dil
+    RETQ killed %al
+
+...
+
+---
+name:            test_movb_impuse
+allVRegsAllocated: true
+isSSA:           false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: %edi
+
+    ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
+    %al = MOV8rr %dil, implicit %edi
+    RETQ killed %al
+
+...
+
+---
+name:            test_movb_impdef_gr64
+allVRegsAllocated: true
+isSSA:           false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: %edi
+
+    ; CHECK: %eax = MOV32rr undef %edi, implicit %dil, implicit-def %rax
+    %al = MOV8rr %dil, implicit-def %rax
+    RETQ killed %al
+
+...
+
+---
+name:            test_movb_impdef_gr32
+allVRegsAllocated: true
+isSSA:           false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: %edi
+
+    ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
+    %al = MOV8rr %dil, implicit-def %eax
+    RETQ killed %al
+
+...
+
+---
+name:            test_movb_impdef_gr16
+allVRegsAllocated: true
+isSSA:           false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: %edi
+
+    ; CHECK: %eax = MOV32rr undef %edi, implicit %dil
+    %al = MOV8rr %dil, implicit-def %ax
+    RETQ killed %al
+
+...
+
+---
+name:            test_movw_impdef_gr32
+allVRegsAllocated: true
+isSSA:           false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: %edi
+
+    ; CHECK: %eax = MOV32rr undef %edi, implicit %di
+    %ax = MOV16rr %di, implicit-def %eax
+    RETQ killed %ax
+
+...
+
+---
+name:            test_movw_impdef_gr64
+allVRegsAllocated: true
+isSSA:           false
+tracksRegLiveness: true
+liveins:
+  - { reg: '%edi' }
+body:             |
+  bb.0 (%ir-block.0):
+    liveins: %edi
+
+    ; CHECK: %eax = MOV32rr undef %edi, implicit %di, implicit-def %rax
+    %ax = MOV16rr %di, implicit-def %rax
+    RETQ killed %ax
+
+...