From 9570c96e67f00fd85d55c360ec1d29816f30e7e5 Mon Sep 17 00:00:00 2001 From: Ashish Trivedi Date: Tue, 10 Sep 2024 19:04:27 -0700 Subject: [PATCH 1/8] @FIR-142: Update Linux Kernel to 6.6.22-lts to get the PCI-E link and driver up. The changes involved are 1. Update kernel to 6.6.22 2. Port bittware FPGA supported code to 6.6.22 from 5.15.90-lts --- arch/arm64/boot/dts/intel/Makefile | 1 + .../dts/intel/socfpga_agilex_bittware.dts | 188 ++++++++++++++++++ 2 files changed, 189 insertions(+) create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/intel/Makefile index 5cd8e793e2cc..2bc3d55e6091 100644 --- a/arch/arm64/boot/dts/intel/Makefile +++ b/arch/arm64/boot/dts/intel/Makefile @@ -2,6 +2,7 @@ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \ socfpga_agilex_socdk.dtb \ socfpga_agilex_socdk_nand.dtb \ + socfpga_agilex_bittware.dtb \ socfpga_agilex5_socdk.dtb \ socfpga_agilex_n6010.dtb \ socfpga_agilex5_socdk.dtb \ diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts new file mode 100644 index 000000000000..92307404588e --- /dev/null +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019, Intel Corporation + */ +#include "socfpga_agilex.dtsi" +#include "socfpga_agilex_pcie_root_port.dtsi" +/ { + model = "SoCFPGA Agilex BittWare"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + led0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + led1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + led2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac2 { + status = "disabled"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&nand { + status = "okay"; + nand-bus-width = <8>; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + nand-bus-width = <8>; + + partition@0 { + label = "u-boot"; + reg = <0 0x200000>; + }; + partition@200000 { + label = "root"; + reg = <0x200000 0x1fe00000>; + }; + }; +}; + +&osc1 { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; + +&temp_volt { + voltage { + #address-cells = <1>; + #size-cells = <0>; + input@2 { + label = "0.8V VCC"; + reg = <2>; + }; + + input@3 { + label = "1.8V VCCIO_SDM"; + reg = <3>; + }; + + input@4 { + label = "1.8V VCCPT"; + reg = <4>; + }; + + input@5 { + label = "1.2V VCCCRCORE"; + reg = <5>; + }; + + input@6 { + label = "0.9V VCCH"; + reg = <6>; + }; + + input@7 { + label = "0.8V VCCL"; + reg = <7>; + }; + }; + + temperature { + #address-cells = <1>; + #size-cells = <0>; + + input@0 { + label = "Main Die SDM"; + reg = <0x0>; + }; + + input@10000 { + label = "Main Die corner bottom left max"; + reg = <0x10000>; + }; + + input@20000 { + label = "Main Die corner top left max"; + reg = <0x20000>; + }; + + input@30000 { + label = "Main Die corner bottom right max"; + reg = <0x30000>; + }; + + input@40000 { + label = "Main Die corner top right max"; + reg = <0x40000>; + }; + }; +}; + +&pcie_0_pcie_aglx { + status = "okay"; + compatible = "altr,pcie-root-port-3.0-f-tile"; +}; + From 6c68d53a742e04e5a09252b9f810e32845e7b3aa Mon Sep 17 00:00:00 2001 From: atrivedi-tsavoritesi Date: Mon, 16 Sep 2024 11:29:48 -0700 Subject: [PATCH 2/8] @FIR-151: Enable /dev/mem to facilitate troubleshooting (#1) Co-authored-by: Ashish Trivedi --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index cdba832e5ac9..6737d1550bf2 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1595,3 +1595,5 @@ CONFIG_CORESIGHT_STM=m CONFIG_CORESIGHT_CPU_DEBUG=m CONFIG_CORESIGHT_CTI=m CONFIG_MEMTEST=y +CONFIG_STRICT_DEVMEM=n +CONFIG_IO_STRICT_DEVMEM=n From 0593b4ae1c690139038cf4cc10476e1c09c3c2b2 Mon Sep 17 00:00:00 2001 From: atrivedi-tsavoritesi Date: Tue, 24 Sep 2024 18:54:25 -0700 Subject: [PATCH 3/8] FIR: Added reserved memory area and turned on HugeTLB and dev/mem (#2) * @FIR-151: Enable /dev/mem to facilitate troubleshooting * @FIR-165: Making changes to Linux to have a TXE reserved memory The changes consist of 1. Reserved memory area from 0x7F00_0000 to 0x7F1F_FFFF for TXE 2. Enabling the flag to turn on HUGETLB --------- Co-authored-by: Ashish Trivedi --- .../dts/intel/socfpga_agilex_bittware.dts | 32 +++++++++++++++++-- arch/arm64/configs/defconfig | 1 + 2 files changed, 31 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts index 92307404588e..6b1419d91474 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts @@ -41,6 +41,34 @@ /* We expect the bootloader to fill in the reg */ reg = <0 0 0 0>; }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges;*/ + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x200000>; + alignment = <0x2000>; + linux,cma-default; + }; + + /* current allocation is 2 MB from 0x7F00_0000 to 0x7F1F_FFFF + * these allocaiton will change when we add more TXEs and standardize on + * the space every TXE needs + */ + display_reserved: framebuffer@7F000000 { + reg = <0x7F000000 0x100000>; + }; + + restricted_dma_reserved: restricted-dma-pool@FF1000000 { + compatible = "restricted-dma-pool"; + reg = <0x7F100000 0x100000>; + }; + }; + }; &gpio1 { @@ -181,8 +209,8 @@ }; }; -&pcie_0_pcie_aglx { +/*&pcie_0_pcie_aglx { status = "okay"; compatible = "altr,pcie-root-port-3.0-f-tile"; -}; +};*/ diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 6737d1550bf2..3dac140c645d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1597,3 +1597,4 @@ CONFIG_CORESIGHT_CTI=m CONFIG_MEMTEST=y CONFIG_STRICT_DEVMEM=n CONFIG_IO_STRICT_DEVMEM=n +CONFIG_HUGETLB_PAGE=y \ No newline at end of file From eac483186b17898e769160ced98bf1494fe75ff3 Mon Sep 17 00:00:00 2001 From: atrivedi-tsavoritesi Date: Mon, 30 Sep 2024 11:02:52 -0700 Subject: [PATCH 4/8] FIR - 165 Fix typo in the DTS file (#3) * @FIR-151: Enable /dev/mem to facilitate troubleshooting * @FIR-165: Making changes to Linux to have a TXE reserved memory The changes consist of 1. Reserved memory area from 0x7F00_0000 to 0x7F1F_FFFF for TXE 2. Enabling the flag to turn on HUGETLB * @FIR-165: Fixing the typo in DTS 1. fixed the typo in DTS file 2. disabled the DTS structure --------- Co-authored-by: Ashish Trivedi --- arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts | 10 +++++----- arch/arm64/configs/defconfig | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts index 6b1419d91474..63cf533430b4 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts @@ -42,24 +42,24 @@ reg = <0 0 0 0>; }; - reserved-memory { + /*reserved-memory { #address-cells = <1>; #size-cells = <1>; ranges;*/ /* global autoconfigured region for contiguous allocations */ - linux,cma { + /*linux,cma { compatible = "shared-dma-pool"; reusable; size = <0x200000>; alignment = <0x2000>; linux,cma-default; - }; + };*/ /* current allocation is 2 MB from 0x7F00_0000 to 0x7F1F_FFFF * these allocaiton will change when we add more TXEs and standardize on * the space every TXE needs */ - display_reserved: framebuffer@7F000000 { + /* display_reserved: framebuffer@7F000000 { reg = <0x7F000000 0x100000>; }; @@ -67,7 +67,7 @@ compatible = "restricted-dma-pool"; reg = <0x7F100000 0x100000>; }; - }; + };*/ }; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 3dac140c645d..c6da56166e35 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1597,4 +1597,4 @@ CONFIG_CORESIGHT_CTI=m CONFIG_MEMTEST=y CONFIG_STRICT_DEVMEM=n CONFIG_IO_STRICT_DEVMEM=n -CONFIG_HUGETLB_PAGE=y \ No newline at end of file +CONFIG_HUGETLB_PAGE=y From 96acbd034e391982a1b025f8f71ef10b129d18b2 Mon Sep 17 00:00:00 2001 From: atrivedi-tsavoritesi Date: Tue, 1 Oct 2024 12:10:39 -0700 Subject: [PATCH 5/8] @FIR-172: Move the Memory reservation to DTSI file (#4) 1. These changes move the memory reservation to DTSI file 2. Remove the commented out memroy reservation from DTS file Co-authored-by: Ashish Trivedi --- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 6 ++++ .../dts/intel/socfpga_agilex_bittware.dts | 28 ------------------- 2 files changed, 6 insertions(+), 28 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index f0aadd977efb..ad0f8565d374 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -25,6 +25,12 @@ alignment = <0x1000>; no-map; }; + service_reserved1: svcbuffer@1 { + compatible = "shared-dma-pool"; + reg = <0x0 0x7F000000 0x0 0x7FFFFFFF>; + alignment = <0x1000>; + no-map; + }; }; cpus { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts index 63cf533430b4..6e06d5491f38 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts @@ -41,34 +41,6 @@ /* We expect the bootloader to fill in the reg */ reg = <0 0 0 0>; }; - - /*reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges;*/ - /* global autoconfigured region for contiguous allocations */ - /*linux,cma { - compatible = "shared-dma-pool"; - reusable; - size = <0x200000>; - alignment = <0x2000>; - linux,cma-default; - };*/ - - /* current allocation is 2 MB from 0x7F00_0000 to 0x7F1F_FFFF - * these allocaiton will change when we add more TXEs and standardize on - * the space every TXE needs - */ - /* display_reserved: framebuffer@7F000000 { - reg = <0x7F000000 0x100000>; - }; - - restricted_dma_reserved: restricted-dma-pool@FF1000000 { - compatible = "restricted-dma-pool"; - reg = <0x7F100000 0x100000>; - }; - };*/ - }; &gpio1 { From d3f9e5ee3717319a2be685dea31af9fefe03fe5c Mon Sep 17 00:00:00 2001 From: atrivedi-tsavoritesi Date: Fri, 11 Oct 2024 16:55:12 -0700 Subject: [PATCH 6/8] Ssd patch (#5) * @FIR-204: Fix NVME changes and pushed into a repo These changes are based off of what works in Meera's repo * @FIR-204: Remove print debug statements before main branch push This change picks up Meera's working image and is ready for main branch The change consistent of validating Meera's SSD changes work and we are forcing the IO Queues to 4 and are applying these boot params ; bridge enable 7; md 0xffd11028 1 ; mw 0xffd11028 0x00021ffe ; mw 0xffc03204 0x000c0000; ; mw 0xffc03200 0x00000000; mw 0xffc03304 0x00000013; mw 0xffc03300 0x00000010; ; setenv bootargs " ${bootargs} nvme_core.default_ps_max_latency_us=0 pcie_aspm=off nvme_core.io_timeout=60 nvme.poll_queues=4 pci=nomsi " ; run nandfitload; run nandfitboot; * @FIR-204: Added changes to remove drivers/pci/controller/pcie-altera.c --------- Co-authored-by: Ashish Trivedi --- arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts | 7 +++++-- .../boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi | 1 + arch/arm64/configs/defconfig | 6 ++++++ drivers/nvme/host/core.c | 3 ++- drivers/nvme/host/pci.c | 1 + 5 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts index 6e06d5491f38..6757577c5c42 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts @@ -183,6 +183,9 @@ /*&pcie_0_pcie_aglx { status = "okay"; - compatible = "altr,pcie-root-port-3.0-f-tile"; -};*/ + compatible = "altr,pcie-root-port-3.0-f-tile";*/ + /* interrupts = <0 0 0>; */ +/* interrupts = <32 IRQ_TYPE_LEVEL_HIGH>; + interupt_parent = <&intc>; */ +/*};*/ diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi index d8ed797d08bb..5ffcef255b5c 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi @@ -27,6 +27,7 @@ interrupt-controller; #interrupt-cells = <0x1>; device_type = "pci"; + max-link-speed = <2>; /* MM addded */ bus-range = <0x0000000 0x000000ff>; ranges = <0x82000000 0x00000000 0x00100000 0x00000000 0x10000000 0x00000000 0x0ff00000>; msi-parent = <&pcie_0_msi_irq>; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index c6da56166e35..b7c8611c3875 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1598,3 +1598,9 @@ CONFIG_MEMTEST=y CONFIG_STRICT_DEVMEM=n CONFIG_IO_STRICT_DEVMEM=n CONFIG_HUGETLB_PAGE=y +##MM includes +CONFIG_BLK_DEV_NVME=y +CONFIG_NVME_MULTIPATH=y +CONFIG_NVME_VERBOSE_ERRORS=y +#CONFIG_NVME_HWMON=y +#CONFIG_NVME_FC=y diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c index d4564a2517eb..d5331eee139d 100644 --- a/drivers/nvme/host/core.c +++ b/drivers/nvme/host/core.c @@ -2320,7 +2320,8 @@ int nvme_enable_ctrl(struct nvme_ctrl *ctrl) if (ret) return ret; return nvme_wait_ready(ctrl, NVME_CSTS_RDY, NVME_CSTS_RDY, - (timeout + 1) / 2, "initialisation"); + (timeout + 1) * 2, "initialisation"); +/*MM : PATCH (timeout + 1) / 2, "initialisation"); */ } EXPORT_SYMBOL_GPL(nvme_enable_ctrl); diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index f8e92404a659..17fbf4e95cfb 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -2270,6 +2270,7 @@ static int nvme_setup_io_queues(struct nvme_dev *dev) dev->nr_poll_queues = poll_queues; nr_io_queues = dev->nr_allocated_queues - 1; + nr_io_queues = 4; result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); if (result < 0) return result; From cc2bbeac49eaab05692c22f11049735b5de84425 Mon Sep 17 00:00:00 2001 From: Ashish Trivedi Date: Fri, 11 Oct 2024 22:53:12 -0700 Subject: [PATCH 7/8] @FIR-204: Remove not needed changes from SSD Removed following changes from patch 1. Enable PCI-E root port in DTS 2. Remove forcing of Gen 2 in DTS 3. Remove forcing of 4 io queues 4. Remove increased timeouts in nvme code --- arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts | 6 +++--- .../arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi | 1 - drivers/nvme/host/core.c | 3 +-- drivers/nvme/host/pci.c | 1 - 4 files changed, 4 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts index 6757577c5c42..c221d31f2eb1 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts @@ -181,11 +181,11 @@ }; }; -/*&pcie_0_pcie_aglx { +&pcie_0_pcie_aglx { status = "okay"; - compatible = "altr,pcie-root-port-3.0-f-tile";*/ + compatible = "altr,pcie-root-port-3.0-f-tile"; /* interrupts = <0 0 0>; */ /* interrupts = <32 IRQ_TYPE_LEVEL_HIGH>; interupt_parent = <&intc>; */ -/*};*/ +}; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi index 5ffcef255b5c..d8ed797d08bb 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi @@ -27,7 +27,6 @@ interrupt-controller; #interrupt-cells = <0x1>; device_type = "pci"; - max-link-speed = <2>; /* MM addded */ bus-range = <0x0000000 0x000000ff>; ranges = <0x82000000 0x00000000 0x00100000 0x00000000 0x10000000 0x00000000 0x0ff00000>; msi-parent = <&pcie_0_msi_irq>; diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c index d5331eee139d..89ff5934458d 100644 --- a/drivers/nvme/host/core.c +++ b/drivers/nvme/host/core.c @@ -2320,8 +2320,7 @@ int nvme_enable_ctrl(struct nvme_ctrl *ctrl) if (ret) return ret; return nvme_wait_ready(ctrl, NVME_CSTS_RDY, NVME_CSTS_RDY, - (timeout + 1) * 2, "initialisation"); -/*MM : PATCH (timeout + 1) / 2, "initialisation"); */ + (timeout + 1) / 2, "initialisation"); } EXPORT_SYMBOL_GPL(nvme_enable_ctrl); diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c index 17fbf4e95cfb..f8e92404a659 100644 --- a/drivers/nvme/host/pci.c +++ b/drivers/nvme/host/pci.c @@ -2270,7 +2270,6 @@ static int nvme_setup_io_queues(struct nvme_dev *dev) dev->nr_poll_queues = poll_queues; nr_io_queues = dev->nr_allocated_queues - 1; - nr_io_queues = 4; result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); if (result < 0) return result; From 2e5b926ac4f934e17c8e67b25797aed95a9694eb Mon Sep 17 00:00:00 2001 From: Ashish Trivedi Date: Sun, 13 Oct 2024 09:47:10 -0700 Subject: [PATCH 8/8] @FIR-204: Removed the config flags which are not needed Removed config flags which are not needed The NVME Multipath and the NVME Debug Errors are not needed --- arch/arm64/configs/defconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b7c8611c3875..efbae2191b96 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1600,7 +1600,7 @@ CONFIG_IO_STRICT_DEVMEM=n CONFIG_HUGETLB_PAGE=y ##MM includes CONFIG_BLK_DEV_NVME=y -CONFIG_NVME_MULTIPATH=y -CONFIG_NVME_VERBOSE_ERRORS=y +#CONFIG_NVME_MULTIPATH=y +#CONFIG_NVME_VERBOSE_ERRORS=y #CONFIG_NVME_HWMON=y #CONFIG_NVME_FC=y