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davem330davem330
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Merge branch 'net-800Gbps-support'
Petr Machata says: ==================== net: Add support for 800Gbps speed Amit Cohen <[email protected]> writes: The next Nvidia Spectrum ASIC will support 800Gbps speed. The IEEE 802 LAN/MAN Standards Committee already published standards for 800Gbps, see the last update [1] and the list of approved changes [2]. As first phase, add support for 800Gbps over 8 lanes (100Gbps/lane). In the future 800Gbps over 4 lanes can be supported also. Extend ethtool to support the relevant PMDs and extend mlxsw and bonding drivers to support 800Gbps. ==================== Signed-off-by: David S. Miller <[email protected]>
2 parents c1aa0a9 + 41305d3 commit ea5ed0f

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‎drivers/net/bonding/bond_3ad.c‎

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -75,6 +75,7 @@ enum ad_link_speed_type {
7575
AD_LINK_SPEED_100000MBPS,
7676
AD_LINK_SPEED_200000MBPS,
7777
AD_LINK_SPEED_400000MBPS,
78+
AD_LINK_SPEED_800000MBPS,
7879
};
7980

8081
/* compare MAC addresses */
@@ -251,6 +252,7 @@ static inline int __check_agg_selection_timer(struct port *port)
251252
* %AD_LINK_SPEED_100000MBPS
252253
* %AD_LINK_SPEED_200000MBPS
253254
* %AD_LINK_SPEED_400000MBPS
255+
* %AD_LINK_SPEED_800000MBPS
254256
*/
255257
static u16 __get_link_speed(struct port *port)
256258
{
@@ -326,6 +328,10 @@ static u16 __get_link_speed(struct port *port)
326328
speed = AD_LINK_SPEED_400000MBPS;
327329
break;
328330

331+
case SPEED_800000:
332+
speed = AD_LINK_SPEED_800000MBPS;
333+
break;
334+
329335
default:
330336
/* unknown speed value from ethtool. shouldn't happen */
331337
if (slave->speed != SPEED_UNKNOWN)
@@ -753,6 +759,9 @@ static u32 __get_agg_bandwidth(struct aggregator *aggregator)
753759
case AD_LINK_SPEED_400000MBPS:
754760
bandwidth = nports * 400000;
755761
break;
762+
case AD_LINK_SPEED_800000MBPS:
763+
bandwidth = nports * 800000;
764+
break;
756765
default:
757766
bandwidth = 0; /* to silence the compiler */
758767
}

‎drivers/net/ethernet/mellanox/mlxsw/reg.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4620,6 +4620,7 @@ MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
46204620
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_100GAUI_2_100GBASE_CR2_KR2 BIT(10)
46214621
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_200GAUI_4_200GBASE_CR4_KR4 BIT(12)
46224622
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_400GAUI_8 BIT(15)
4623+
#define MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8 BIT(19)
46234624

46244625
/* reg_ptys_ext_eth_proto_cap
46254626
* Extended Ethernet port supported speeds and protocols.

‎drivers/net/ethernet/mellanox/mlxsw/spectrum_ethtool.c‎

Lines changed: 21 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1672,6 +1672,19 @@ mlxsw_sp2_mask_ethtool_400gaui_8[] = {
16721672
#define MLXSW_SP2_MASK_ETHTOOL_400GAUI_8_LEN \
16731673
ARRAY_SIZE(mlxsw_sp2_mask_ethtool_400gaui_8)
16741674

1675+
static const enum ethtool_link_mode_bit_indices
1676+
mlxsw_sp2_mask_ethtool_800gaui_8[] = {
1677+
ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT,
1678+
ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT,
1679+
ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT,
1680+
ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT,
1681+
ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT,
1682+
ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT,
1683+
};
1684+
1685+
#define MLXSW_SP2_MASK_ETHTOOL_800GAUI_8_LEN \
1686+
ARRAY_SIZE(mlxsw_sp2_mask_ethtool_800gaui_8)
1687+
16751688
#define MLXSW_SP_PORT_MASK_WIDTH_1X BIT(0)
16761689
#define MLXSW_SP_PORT_MASK_WIDTH_2X BIT(1)
16771690
#define MLXSW_SP_PORT_MASK_WIDTH_4X BIT(2)
@@ -1820,6 +1833,14 @@ static const struct mlxsw_sp2_port_link_mode mlxsw_sp2_port_link_mode[] = {
18201833
.speed = SPEED_400000,
18211834
.width = 8,
18221835
},
1836+
{
1837+
.mask = MLXSW_REG_PTYS_EXT_ETH_SPEED_800GAUI_8,
1838+
.mask_ethtool = mlxsw_sp2_mask_ethtool_800gaui_8,
1839+
.m_ethtool_len = MLXSW_SP2_MASK_ETHTOOL_800GAUI_8_LEN,
1840+
.mask_sup_width = MLXSW_SP_PORT_MASK_WIDTH_8X,
1841+
.speed = SPEED_800000,
1842+
.width = 8,
1843+
},
18231844
};
18241845

18251846
#define MLXSW_SP2_PORT_LINK_MODE_LEN ARRAY_SIZE(mlxsw_sp2_port_link_mode)

‎drivers/net/phy/phy-core.c‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@
1313
*/
1414
const char *phy_speed_to_str(int speed)
1515
{
16-
BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 93,
16+
BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 99,
1717
"Enum ethtool_link_mode_bit_indices and phylib are out of sync. "
1818
"If a speed or mode has been added please update phy_speed_to_str "
1919
"and the PHY settings array.\n");
@@ -49,6 +49,8 @@ const char *phy_speed_to_str(int speed)
4949
return "200Gbps";
5050
case SPEED_400000:
5151
return "400Gbps";
52+
case SPEED_800000:
53+
return "800Gbps";
5254
case SPEED_UNKNOWN:
5355
return "Unknown";
5456
default:
@@ -157,6 +159,13 @@ EXPORT_SYMBOL_GPL(phy_interface_num_ports);
157159
.bit = ETHTOOL_LINK_MODE_ ## b ## _BIT}
158160

159161
static const struct phy_setting settings[] = {
162+
/* 800G */
163+
PHY_SETTING( 800000, FULL, 800000baseCR8_Full ),
164+
PHY_SETTING( 800000, FULL, 800000baseKR8_Full ),
165+
PHY_SETTING( 800000, FULL, 800000baseDR8_Full ),
166+
PHY_SETTING( 800000, FULL, 800000baseDR8_2_Full ),
167+
PHY_SETTING( 800000, FULL, 800000baseSR8_Full ),
168+
PHY_SETTING( 800000, FULL, 800000baseVR8_Full ),
160169
/* 400G */
161170
PHY_SETTING( 400000, FULL, 400000baseCR8_Full ),
162171
PHY_SETTING( 400000, FULL, 400000baseKR8_Full ),

‎include/uapi/linux/ethtool.h‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1737,6 +1737,13 @@ enum ethtool_link_mode_bit_indices {
17371737
ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90,
17381738
ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91,
17391739
ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 92,
1740+
ETHTOOL_LINK_MODE_800000baseCR8_Full_BIT = 93,
1741+
ETHTOOL_LINK_MODE_800000baseKR8_Full_BIT = 94,
1742+
ETHTOOL_LINK_MODE_800000baseDR8_Full_BIT = 95,
1743+
ETHTOOL_LINK_MODE_800000baseDR8_2_Full_BIT = 96,
1744+
ETHTOOL_LINK_MODE_800000baseSR8_Full_BIT = 97,
1745+
ETHTOOL_LINK_MODE_800000baseVR8_Full_BIT = 98,
1746+
17401747
/* must be last entry */
17411748
__ETHTOOL_LINK_MODE_MASK_NBITS
17421749
};
@@ -1848,6 +1855,7 @@ enum ethtool_link_mode_bit_indices {
18481855
#define SPEED_100000 100000
18491856
#define SPEED_200000 200000
18501857
#define SPEED_400000 400000
1858+
#define SPEED_800000 800000
18511859

18521860
#define SPEED_UNKNOWN -1
18531861

‎net/ethtool/common.c‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -202,6 +202,12 @@ const char link_mode_names[][ETH_GSTRING_LEN] = {
202202
__DEFINE_LINK_MODE_NAME(100, FX, Half),
203203
__DEFINE_LINK_MODE_NAME(100, FX, Full),
204204
__DEFINE_LINK_MODE_NAME(10, T1L, Full),
205+
__DEFINE_LINK_MODE_NAME(800000, CR8, Full),
206+
__DEFINE_LINK_MODE_NAME(800000, KR8, Full),
207+
__DEFINE_LINK_MODE_NAME(800000, DR8, Full),
208+
__DEFINE_LINK_MODE_NAME(800000, DR8_2, Full),
209+
__DEFINE_LINK_MODE_NAME(800000, SR8, Full),
210+
__DEFINE_LINK_MODE_NAME(800000, VR8, Full),
205211
};
206212
static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
207213

@@ -238,6 +244,8 @@ static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS);
238244
#define __LINK_MODE_LANES_X 1
239245
#define __LINK_MODE_LANES_FX 1
240246
#define __LINK_MODE_LANES_T1L 1
247+
#define __LINK_MODE_LANES_VR8 8
248+
#define __LINK_MODE_LANES_DR8_2 8
241249

242250
#define __DEFINE_LINK_MODE_PARAMS(_speed, _type, _duplex) \
243251
[ETHTOOL_LINK_MODE(_speed, _type, _duplex)] = { \
@@ -352,6 +360,12 @@ const struct link_mode_info link_mode_params[] = {
352360
__DEFINE_LINK_MODE_PARAMS(100, FX, Half),
353361
__DEFINE_LINK_MODE_PARAMS(100, FX, Full),
354362
__DEFINE_LINK_MODE_PARAMS(10, T1L, Full),
363+
__DEFINE_LINK_MODE_PARAMS(800000, CR8, Full),
364+
__DEFINE_LINK_MODE_PARAMS(800000, KR8, Full),
365+
__DEFINE_LINK_MODE_PARAMS(800000, DR8, Full),
366+
__DEFINE_LINK_MODE_PARAMS(800000, DR8_2, Full),
367+
__DEFINE_LINK_MODE_PARAMS(800000, SR8, Full),
368+
__DEFINE_LINK_MODE_PARAMS(800000, VR8, Full),
355369
};
356370
static_assert(ARRAY_SIZE(link_mode_params) == __ETHTOOL_LINK_MODE_MASK_NBITS);
357371

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