Simmadha/qsfp mem controller driver (#20)

KrishnaSimmadhari · preetam-narayan · commit e24c7f18c4cc · 2025-05-19T12:12:57.000+05:30
fpga: QSFP controller subsystem driver for Intel FPGAs

Qsfp controller driver to include platform and DFL interface driver. DFL driver is used
for the host which accesses the QSFP controller subsystem using the PCIe bus and
the platform driver is used where the subsystem is accessed through the AXI/AXI-Lite bus.

Signed-off-by: Krishna Kumar S R simmadhari.ramadass.krishna.kumar@intel.com
diff --git a/Documentation/devicetree/bindings/phy/intel,qsfp-mem.txt b/Documentation/devicetree/bindings/phy/intel,qsfp-mem.txt
@@ -0,0 +1,16 @@
+* Intel QSFP Memory controller subsystem
+
+Required properties:
+- compatible: Should be "intel,qsfp-mem"
+- reg: Address and length of the register set for the device. It contains
+  the information of registers in the same order as described by reg-names
+- reg-names: Should contain the reg names
+
+Example:
+
+		qsfp_eth0: qsfp-eth0 {
+			   compatible = "intel,qsfp-mem";
+			   reg-names = "qsfp-mem-controller";
+			   reg = <0x00000001 0x80112000 0x00001000>,
+			   status = "okay";
+		};
diff --git a/arch/arm64/boot/dts/intel/socfpga_acadp_ptp_soln.dts b/arch/arm64/boot/dts/intel/socfpga_acadp_ptp_soln.dts
@@ -1,6 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0
+// SPDX-License-Identifier: GPL
 /*
- * Copyright (C) 2022,2023, Intel Corporation
+ * Copyright (C) 2022,2023 Intel Corporation
  */
 #include "socfpga_agilex.dtsi"
 
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
@@ -77,13 +77,28 @@ config SFP
 	depends on HWMON || HWMON=n
 	select MDIO_I2C
 
-config QSFP
-	tristate "QSFP cage support"
-	depends on I2C && PHYLINK
+config QSFP_MEM_CORE
+	tristate "QSFP Controller subsystem core code" if COMPILE_TEST
 	depends on HWMON || HWMON=n
-	select MDIO_I2C
 	help
-	  Currently supports SFF-8636 Rev2.9 QSFP connectors or cables.
+	  The core code for the QSFP Controller subsystem for Intel FPGAs used
+	  by other interafce module drivers for access to the QSFP controller
+	  subsystem registers
+
+config QSFP_MEM
+	tristate "Memory based platform driver for QSFP Controller subsystem in Intel FPGAs"
+	select QSFP_MEM_CORE
+	help
+	  Adds support for a QSFP controller subsystem that shadows the QSFP module's
+	  memory pages in memory
+
+config QSFP_MEM_DFL
+	tristate "DFL bus driver for QSFP Controller subsystem in Intel FPGAs"
+	depends on FPGA_DFL
+	select QSFP_MEM_CORE
+	help
+	  This is a Device Feature List (DFL) bus driver for the
+	  QSFP Controller subsystem in Intel FPGAs.
 
 comment "MII PHY device drivers"
 
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
@@ -33,10 +33,14 @@ obj-$(CONFIG_SFP)		+= sfp.o
 sfp-obj-$(CONFIG_SFP)		+= sfp-bus.o
 obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
 
-obj-$(CONFIG_QSFP)		+= qsfp.o qsfp-mem.o
+obj-$(CONFIG_QSFP)		+= qsfp.o
 qsfp-obj-$(CONFIG_QSFP)		+= qsfp_bus.o
 obj-y				+= $(qsfp-obj-y) $(qsfp-obj-m)
 
+obj-$(CONFIG_QSFP_MEM_CORE)     += qsfp-mem-core.o
+obj-$(CONFIG_QSFP_MEM_DFL)      += qsfp-mem-dfl.o
+obj-$(CONFIG_QSFP_MEM)          += qsfp-mem-platform.o
+
 obj-$(CONFIG_ADIN_PHY)		+= adin.o
 obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
 obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
diff --git a/drivers/net/phy/qsfp-mem-core.c b/drivers/net/phy/qsfp-mem-core.c
@@ -0,0 +1,177 @@
+// SPDX-License-Identifier: GPL
+
+/* Intel(R) Memory based QSFP driver.
+ *
+ * Copyright (C) 2020,2022 Intel Corporation. All rights reserved.
+ */
+
+#include <linux/bitfield.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/i2c.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/regmap.h>
+#include <linux/uaccess.h>
+#include <linux/phy/qsfp-mem.h>
+
+#define CONF_OFF	0x20
+#define CONF_RST_MOD	BIT(0)
+#define CONF_RST_CON	BIT(1)
+#define CONF_MOD_SEL	BIT(2)
+#define CONF_LOW_POW	BIT(3)
+#define CONF_POLL_EN	BIT(4)
+
+#define STAT_OFF	0x28
+#define MODPRSL         BIT(0)
+#define DELAY_REG       0x38
+#define DELAY_VALUE       0xffffff
+
+#define I2C_CTRL        0x48
+#define I2C_CTRL_EN	BIT(0)
+#define I2C_CTRL_BSP	BIT(1)
+#define I2C_CTRL_FIFO  GENMASK(3, 2)
+#define I2C_CTRL_FIFO_NOT_FULL 3
+
+#define I2C_ISER	0x4c
+#define I2C_ISER_TXRDY	BIT(0)
+#define I2C_ISER_RXRDY	BIT(1)
+#define I2C_SCL_LOW	0x60
+#define COUNT_PERIOD_LOW 0x82
+#define I2C_SCL_HIGH	0x64
+#define COUNT_PERIOD_HIGH 0x3c
+#define I2C_SDA_HOLD	0x68
+#define COUNT_PERIOD_HOLD 0x28
+
+#define QSFP_SHADOW_CSRS_BASE_OFF	0x100
+#define QSFP_SHADOW_CSRS_BASE_END	0x3f8
+
+#define DELAY_US 1000
+
+#define QSFP_CHECK_TIME 500
+
+static const struct regmap_range qsfp_mem_regmap_range[] = {
+	regmap_reg_range(CONF_OFF, STAT_OFF),
+	regmap_reg_range(QSFP_SHADOW_CSRS_BASE_OFF, QSFP_SHADOW_CSRS_BASE_END),
+};
+
+static const struct regmap_access_table qsfp_mem_access_table = {
+	.yes_ranges	= qsfp_mem_regmap_range,
+	.n_yes_ranges	= ARRAY_SIZE(qsfp_mem_regmap_range),
+};
+
+static void qsfp_init_i2c(struct qsfp *qsfp)
+{
+	writel(I2C_ISER_TXRDY | I2C_ISER_RXRDY, qsfp->base + I2C_ISER);
+	writel(COUNT_PERIOD_LOW, qsfp->base + I2C_SCL_LOW);
+	writel(COUNT_PERIOD_HIGH, qsfp->base + I2C_SCL_HIGH);
+	writel(COUNT_PERIOD_HOLD, qsfp->base + I2C_SDA_HOLD);
+
+	writel(FIELD_PREP(I2C_CTRL_FIFO, I2C_CTRL_FIFO_NOT_FULL) |
+			I2C_CTRL_EN | I2C_CTRL_BSP, qsfp->base + I2C_CTRL);
+}
+
+static const struct regmap_config mmio_cfg = {
+	.reg_bits = 64,
+	.reg_stride = 8,
+	.val_bits = 64,
+	.fast_io = true,
+	.rd_table = &qsfp_mem_access_table,
+	.max_register = QSFP_SHADOW_CSRS_BASE_END,
+};
+
+static void qsfp_init(struct qsfp *qsfp)
+{
+	writeq(CONF_RST_MOD | CONF_RST_CON | CONF_MOD_SEL, qsfp->base + CONF_OFF);
+	udelay(DELAY_US);
+	writeq(CONF_MOD_SEL, qsfp->base + CONF_OFF);
+	udelay(DELAY_US);
+
+	qsfp_init_i2c(qsfp);
+
+	udelay(DELAY_US);
+	writeq(DELAY_VALUE, qsfp->base + DELAY_REG);
+
+	writeq(CONF_POLL_EN | CONF_MOD_SEL, qsfp->base + CONF_OFF);
+	udelay(DELAY_US);
+}
+
+int check_qsfp_plugin(struct qsfp *qsfp)
+{
+	u64 status;
+
+	status = readq(qsfp->base + STAT_OFF);
+
+	return (!(status & MODPRSL));
+}
+EXPORT_SYMBOL_GPL(check_qsfp_plugin);
+
+u32 qsfp_connected_show(struct qsfp *qsfp)
+{
+	u32 plugin;
+
+	mutex_lock(&qsfp->lock);
+	plugin = check_qsfp_plugin(qsfp) && (qsfp->init == QSFP_INIT_DONE);
+	mutex_unlock(&qsfp->lock);
+
+	return plugin;
+}
+EXPORT_SYMBOL_GPL(qsfp_connected_show);
+
+void qsfp_check_hotplug(struct work_struct *work)
+{
+	struct delayed_work *dwork;
+	struct qsfp *qsfp;
+	u64 status;
+
+	dwork = to_delayed_work(work);
+	qsfp = container_of(dwork, struct qsfp, dwork);
+
+	mutex_lock(&qsfp->lock);
+
+	status = readq(qsfp->base + STAT_OFF);
+	dev_dbg(qsfp->dev, "qsfp status 0x%llx\n", status);
+
+	if (check_qsfp_plugin(qsfp) && qsfp->init == QSFP_INIT_RESET) {
+		dev_info(qsfp->dev, "detected QSFP plugin\n");
+		qsfp_init(qsfp);
+		WRITE_ONCE(qsfp->init, QSFP_INIT_DONE);
+	} else if (!check_qsfp_plugin(qsfp) &&
+		   qsfp->init == QSFP_INIT_DONE) {
+		dev_info(qsfp->dev, "detected QSFP unplugin\n");
+		WRITE_ONCE(qsfp->init, QSFP_INIT_RESET);
+	}
+	mutex_unlock(&qsfp->lock);
+
+	schedule_delayed_work(&qsfp->dwork, msecs_to_jiffies(QSFP_CHECK_TIME));
+}
+
+int qsfp_init_work(struct qsfp *qsfp)
+{
+	qsfp->init = QSFP_INIT_RESET;
+	INIT_DELAYED_WORK(&qsfp->dwork, qsfp_check_hotplug);
+	qsfp_check_hotplug(&qsfp->dwork.work);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(qsfp_init_work);
+
+int qsfp_register_regmap(struct qsfp *qsfp)
+{
+	struct device *dev = qsfp->dev;
+
+	qsfp->regmap = devm_regmap_init_mmio(dev, qsfp->base, &mmio_cfg);
+	if (IS_ERR(qsfp->regmap))
+		dev_err(dev, "Failed to create qsfp regmap\n");
+
+	return PTR_ERR_OR_ZERO(qsfp->regmap);
+}
+EXPORT_SYMBOL_GPL(qsfp_register_regmap);
+
+void qsfp_remove_device(struct qsfp *qsfp)
+{
+	writeq(CONF_MOD_SEL, qsfp->base + CONF_OFF);
+	cancel_delayed_work_sync(&qsfp->dwork);
+}
+EXPORT_SYMBOL_GPL(qsfp_remove_device);
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/phy/qsfp-mem-dfl.c b/drivers/net/phy/qsfp-mem-dfl.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Intel(R) Memory based QSFP driver For DFL based devices.
+ *
+ * Copyright (C) 2022 Intel Corporation. All rights reserved.
+ */
+#include <linux/dfl.h>
+#include <linux/phy/qsfp-mem.h>
+#include <linux/module.h>
+
+ssize_t dfl_qsfp_connected_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+	struct qsfp *qsfp = dev_get_drvdata(dev);
+	u32 plugin = qsfp_connected_show(qsfp);
+
+	return sysfs_emit(buf, "%u\n", plugin);
+}
+
+static DEVICE_ATTR_RO(dfl_qsfp_connected);
+
+static struct attribute *qsfp_mem_attrs[] = {
+	&dev_attr_dfl_qsfp_connected.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(qsfp_mem);
+
+static int qsfp_dfl_probe(struct dfl_device *dfl_dev)
+{
+	struct device *dev = &dfl_dev->dev;
+	struct qsfp *qsfp;
+	int ret = 0;
+
+	qsfp = devm_kzalloc(dev, sizeof(*qsfp), GFP_KERNEL);
+	if (!qsfp)
+		return -ENOMEM;
+
+	qsfp->base = devm_ioremap_resource(dev, &dfl_dev->mmio_res);
+	if (!qsfp->base)
+		return -ENOMEM;
+
+	qsfp->dev = dev;
+	mutex_init(&qsfp->lock);
+
+	dev_set_drvdata(dev, qsfp);
+
+	ret = qsfp_init_work(qsfp);
+	if (ret != 0) {
+		dev_err(dev, "Failed to initialize delayed work to read QSFP\n");
+		return ret;
+	}
+	return qsfp_register_regmap(qsfp);
+}
+
+static void qsfp_dfl_remove(struct dfl_device *dfl_dev)
+{
+	struct device *dev = &dfl_dev->dev;
+	struct qsfp *qsfp = dev_get_drvdata(dev);
+
+	qsfp_remove_device(qsfp);
+	mutex_destroy(&qsfp->lock);
+}
+
+#define FME_FEATURE_ID_QSFP 0x13
+
+static const struct dfl_device_id qsfp_ids[] = {
+	{ FME_ID, FME_FEATURE_ID_QSFP },
+	{ }
+};
+
+static struct dfl_driver qsfp_driver = {
+	.drv = {
+		.name = "qsfp-mem",
+		.dev_groups = qsfp_mem_groups,
+	},
+	.id_table = qsfp_ids,
+	.probe = qsfp_dfl_probe,
+	.remove = qsfp_dfl_remove,
+};
+
+module_dfl_driver(qsfp_driver);
+MODULE_DEVICE_TABLE(dfl, qsfp_ids);
+MODULE_DESCRIPTION("Intel(R) Memory based QSFP DFL driver");
+MODULE_AUTHOR("Intel Corporation");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/phy/qsfp-mem-platform.c b/drivers/net/phy/qsfp-mem-platform.c
diff --git a/drivers/net/phy/qsfp-mem.c b/drivers/net/phy/qsfp-mem.c
diff --git a/include/linux/phy/qsfp-mem.h b/include/linux/phy/qsfp-mem.h
