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Hante MeulemanKalle Valo
Hante Meuleman
authored and
Kalle Valo
committed
brcmfmac: remove pcie gen1 support
The PCIE bus driver supports older gen1 (v1) chips, but there is no actual device which is using this older pcie core which is supported by brcmfmac. Remove all gen1 related code. Reviewed-by: Arend Van Spriel <[email protected]> Reviewed-by: Franky (Zhenhui) Lin <[email protected]> Reviewed-by: Pieter-Paul Giesberts <[email protected]> Signed-off-by: Hante Meuleman <[email protected]> Signed-off-by: Arend van Spriel <[email protected]> Signed-off-by: Kalle Valo <[email protected]>
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  • drivers/net/wireless/broadcom/brcm80211/brcmfmac

1 file changed

+20
-115
lines changed

‎drivers/net/wireless/broadcom/brcm80211/brcmfmac/pcie.c‎

Lines changed: 20 additions & 115 deletions
Original file line numberDiff line numberDiff line change
@@ -100,9 +100,6 @@ static struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
100100
#define BRCMF_PCIE_PCIE2REG_CONFIGDATA 0x124
101101
#define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX 0x140
102102

103-
#define BRCMF_PCIE_GENREV1 1
104-
#define BRCMF_PCIE_GENREV2 2
105-
106103
#define BRCMF_PCIE2_INTA 0x01
107104
#define BRCMF_PCIE2_INTB 0x02
108105

@@ -257,9 +254,7 @@ struct brcmf_pciedev_info {
257254
u32 ram_size;
258255
struct brcmf_chip *ci;
259256
u32 coreid;
260-
u32 generic_corerev;
261257
struct brcmf_pcie_shared_info shared;
262-
void (*ringbell)(struct brcmf_pciedev_info *devinfo);
263258
wait_queue_head_t mbdata_resp_wait;
264259
bool mbdata_completed;
265260
bool irq_allocated;
@@ -746,68 +741,22 @@ static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo)
746741
}
747742

748743

749-
static __used void brcmf_pcie_ringbell_v1(struct brcmf_pciedev_info *devinfo)
750-
{
751-
u32 reg_value;
752-
753-
brcmf_dbg(PCIE, "RING !\n");
754-
reg_value = brcmf_pcie_read_reg32(devinfo,
755-
BRCMF_PCIE_PCIE2REG_MAILBOXINT);
756-
reg_value |= BRCMF_PCIE2_INTB;
757-
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
758-
reg_value);
759-
}
760-
761-
762-
static void brcmf_pcie_ringbell_v2(struct brcmf_pciedev_info *devinfo)
763-
{
764-
brcmf_dbg(PCIE, "RING !\n");
765-
/* Any arbitrary value will do, lets use 1 */
766-
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
767-
}
768-
769-
770744
static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
771745
{
772-
if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
773-
pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
774-
0);
775-
else
776-
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
777-
0);
746+
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK, 0);
778747
}
779748

780749

781750
static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
782751
{
783-
if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1)
784-
pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTMASK,
785-
BRCMF_PCIE_INT_DEF);
786-
else
787-
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
788-
BRCMF_PCIE_MB_INT_D2H_DB |
789-
BRCMF_PCIE_MB_INT_FN0_0 |
790-
BRCMF_PCIE_MB_INT_FN0_1);
752+
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
753+
BRCMF_PCIE_MB_INT_D2H_DB |
754+
BRCMF_PCIE_MB_INT_FN0_0 |
755+
BRCMF_PCIE_MB_INT_FN0_1);
791756
}
792757

793758

794-
static irqreturn_t brcmf_pcie_quick_check_isr_v1(int irq, void *arg)
795-
{
796-
struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
797-
u32 status;
798-
799-
status = 0;
800-
pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
801-
if (status) {
802-
brcmf_pcie_intr_disable(devinfo);
803-
brcmf_dbg(PCIE, "Enter\n");
804-
return IRQ_WAKE_THREAD;
805-
}
806-
return IRQ_NONE;
807-
}
808-
809-
810-
static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
759+
static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
811760
{
812761
struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
813762

@@ -820,29 +769,7 @@ static irqreturn_t brcmf_pcie_quick_check_isr_v2(int irq, void *arg)
820769
}
821770

822771

823-
static irqreturn_t brcmf_pcie_isr_thread_v1(int irq, void *arg)
824-
{
825-
struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
826-
const struct pci_dev *pdev = devinfo->pdev;
827-
u32 status;
828-
829-
devinfo->in_irq = true;
830-
status = 0;
831-
pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
832-
brcmf_dbg(PCIE, "Enter %x\n", status);
833-
if (status) {
834-
pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
835-
if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
836-
brcmf_proto_msgbuf_rx_trigger(&devinfo->pdev->dev);
837-
}
838-
if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
839-
brcmf_pcie_intr_enable(devinfo);
840-
devinfo->in_irq = false;
841-
return IRQ_HANDLED;
842-
}
843-
844-
845-
static irqreturn_t brcmf_pcie_isr_thread_v2(int irq, void *arg)
772+
static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg)
846773
{
847774
struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
848775
u32 status;
@@ -879,28 +806,14 @@ static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
879806
brcmf_pcie_intr_disable(devinfo);
880807

881808
brcmf_dbg(PCIE, "Enter\n");
882-
/* is it a v1 or v2 implementation */
809+
883810
pci_enable_msi(pdev);
884-
if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
885-
if (request_threaded_irq(pdev->irq,
886-
brcmf_pcie_quick_check_isr_v1,
887-
brcmf_pcie_isr_thread_v1,
888-
IRQF_SHARED, "brcmf_pcie_intr",
889-
devinfo)) {
890-
pci_disable_msi(pdev);
891-
brcmf_err("Failed to request IRQ %d\n", pdev->irq);
892-
return -EIO;
893-
}
894-
} else {
895-
if (request_threaded_irq(pdev->irq,
896-
brcmf_pcie_quick_check_isr_v2,
897-
brcmf_pcie_isr_thread_v2,
898-
IRQF_SHARED, "brcmf_pcie_intr",
899-
devinfo)) {
900-
pci_disable_msi(pdev);
901-
brcmf_err("Failed to request IRQ %d\n", pdev->irq);
902-
return -EIO;
903-
}
811+
if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr,
812+
brcmf_pcie_isr_thread, IRQF_SHARED,
813+
"brcmf_pcie_intr", devinfo)) {
814+
pci_disable_msi(pdev);
815+
brcmf_err("Failed to request IRQ %d\n", pdev->irq);
816+
return -EIO;
904817
}
905818
devinfo->irq_allocated = true;
906819
return 0;
@@ -931,16 +844,9 @@ static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
931844
if (devinfo->in_irq)
932845
brcmf_err("Still in IRQ (processing) !!!\n");
933846

934-
if (devinfo->generic_corerev == BRCMF_PCIE_GENREV1) {
935-
status = 0;
936-
pci_read_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, &status);
937-
pci_write_config_dword(pdev, BRCMF_PCIE_REG_INTSTATUS, status);
938-
} else {
939-
status = brcmf_pcie_read_reg32(devinfo,
940-
BRCMF_PCIE_PCIE2REG_MAILBOXINT);
941-
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT,
942-
status);
943-
}
847+
status = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT);
848+
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_MAILBOXINT, status);
849+
944850
devinfo->irq_allocated = false;
945851
}
946852

@@ -989,7 +895,9 @@ static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
989895
if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
990896
return -EIO;
991897

992-
devinfo->ringbell(devinfo);
898+
brcmf_dbg(PCIE, "RING !\n");
899+
/* Any arbitrary value will do, lets use 1 */
900+
brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_H2D_MAILBOX, 1);
993901

994902
return 0;
995903
}
@@ -1503,9 +1411,6 @@ static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
15031411
u32 address;
15041412
u32 resetintr;
15051413

1506-
devinfo->ringbell = brcmf_pcie_ringbell_v2;
1507-
devinfo->generic_corerev = BRCMF_PCIE_GENREV2;
1508-
15091414
brcmf_dbg(PCIE, "Halt ARM.\n");
15101415
err = brcmf_pcie_enter_download_state(devinfo);
15111416
if (err)

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