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Merge branch 'add-4-rx-tx-queue-support-for-mikrotik-10-25g-nic'
Gatis Peisenieks says: ==================== add 4 RX/TX queue support for Mikrotik 10/25G NIC More RX/TX queues on a network card help spread the CPU load among cores and achieve higher overall networking performance. This patch set adds support for 4 RX/TX queues available on Mikrotik 10/25G NIC. v4: - addressed comments from Jakub Kicinski: - split up the change in more manageable chunks - changed member order in structs for tighter packing - fixed style issues - reverted to calling napi_alloc_skb only from within poll as before v3: - fix kernel-doc complaints on comments as pointed out by David Miller v2: - rebase on net-next master as requested by David Miller ==================== Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2 parents 91b17a4 + 057f4af commit cf5e129

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3 files changed

+368
-237
lines changed

3 files changed

+368
-237
lines changed

drivers/net/ethernet/atheros/atl1c/atl1c.h

Lines changed: 13 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@
6363

6464
#define AT_MAX_RECEIVE_QUEUE 4
6565
#define AT_DEF_RECEIVE_QUEUE 1
66-
#define AT_MAX_TRANSMIT_QUEUE 2
66+
#define AT_MAX_TRANSMIT_QUEUE 4
6767

6868
#define AT_DMA_HI_ADDR_MASK 0xffffffff00000000ULL
6969
#define AT_DMA_LO_ADDR_MASK 0x00000000ffffffffULL
@@ -294,11 +294,6 @@ enum atl1c_nic_type {
294294
athr_mt,
295295
};
296296

297-
enum atl1c_trans_queue {
298-
atl1c_trans_normal = 0,
299-
atl1c_trans_high = 1
300-
};
301-
302297
struct atl1c_hw_stats {
303298
/* rx */
304299
unsigned long rx_ok; /* The number of good packet received. */
@@ -475,13 +470,16 @@ struct atl1c_buffer {
475470

476471
/* transimit packet descriptor (tpd) ring */
477472
struct atl1c_tpd_ring {
473+
struct atl1c_adapter *adapter;
478474
void *desc; /* descriptor ring virtual address */
479475
dma_addr_t dma; /* descriptor ring physical address */
476+
u16 num;
480477
u16 size; /* descriptor ring length in bytes */
481478
u16 count; /* number of descriptors in the ring */
482479
u16 next_to_use;
483480
atomic_t next_to_clean;
484481
struct atl1c_buffer *buffer_info;
482+
struct napi_struct napi;
485483
};
486484

487485
/* receive free descriptor (rfd) ring */
@@ -497,27 +495,30 @@ struct atl1c_rfd_ring {
497495

498496
/* receive return descriptor (rrd) ring */
499497
struct atl1c_rrd_ring {
498+
struct atl1c_adapter *adapter;
500499
void *desc; /* descriptor ring virtual address */
501500
dma_addr_t dma; /* descriptor ring physical address */
501+
u16 num;
502502
u16 size; /* descriptor ring length in bytes */
503503
u16 count; /* number of descriptors in the ring */
504504
u16 next_to_use;
505505
u16 next_to_clean;
506+
struct napi_struct napi;
507+
struct page *rx_page;
508+
unsigned int rx_page_offset;
506509
};
507510

508511
/* board specific private data structure */
509512
struct atl1c_adapter {
510513
struct net_device *netdev;
511514
struct pci_dev *pdev;
512-
struct napi_struct napi;
513-
struct napi_struct tx_napi;
514-
struct page *rx_page;
515-
unsigned int rx_page_offset;
516515
unsigned int rx_frag_size;
517516
struct atl1c_hw hw;
518517
struct atl1c_hw_stats hw_stats;
519518
struct mii_if_info mii; /* MII interface info */
520519
u16 rx_buffer_len;
520+
unsigned int tx_queue_count;
521+
unsigned int rx_queue_count;
521522

522523
unsigned long flags;
523524
#define __AT_TESTING 0x0001
@@ -543,8 +544,8 @@ struct atl1c_adapter {
543544
/* All Descriptor memory */
544545
struct atl1c_ring_header ring_header;
545546
struct atl1c_tpd_ring tpd_ring[AT_MAX_TRANSMIT_QUEUE];
546-
struct atl1c_rfd_ring rfd_ring;
547-
struct atl1c_rrd_ring rrd_ring;
547+
struct atl1c_rfd_ring rfd_ring[AT_MAX_RECEIVE_QUEUE];
548+
struct atl1c_rrd_ring rrd_ring[AT_MAX_RECEIVE_QUEUE];
548549
u32 bd_number; /* board number;*/
549550
};
550551

drivers/net/ethernet/atheros/atl1c/atl1c_hw.h

Lines changed: 31 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -528,15 +528,24 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
528528
#define REG_RX_BASE_ADDR_HI 0x1540
529529
#define REG_TX_BASE_ADDR_HI 0x1544
530530
#define REG_RFD0_HEAD_ADDR_LO 0x1550
531+
#define REG_RFD1_HEAD_ADDR_LO 0x1554
532+
#define REG_RFD2_HEAD_ADDR_LO 0x1558
533+
#define REG_RFD3_HEAD_ADDR_LO 0x155C
531534
#define REG_RFD_RING_SIZE 0x1560
532535
#define RFD_RING_SIZE_MASK 0x0FFF
533536
#define REG_RX_BUF_SIZE 0x1564
534537
#define RX_BUF_SIZE_MASK 0xFFFF
535538
#define REG_RRD0_HEAD_ADDR_LO 0x1568
539+
#define REG_RRD1_HEAD_ADDR_LO 0x156C
540+
#define REG_RRD2_HEAD_ADDR_LO 0x1570
541+
#define REG_RRD3_HEAD_ADDR_LO 0x1574
536542
#define REG_RRD_RING_SIZE 0x1578
537543
#define RRD_RING_SIZE_MASK 0x0FFF
538544
#define REG_TPD_PRI1_ADDR_LO 0x157C
539545
#define REG_TPD_PRI0_ADDR_LO 0x1580
546+
#define REG_TPD_PRI2_ADDR_LO 0x1F10
547+
#define REG_TPD_PRI3_ADDR_LO 0x1F14
548+
540549
#define REG_TPD_RING_SIZE 0x1584
541550
#define TPD_RING_SIZE_MASK 0xFFFF
542551

@@ -655,15 +664,26 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
655664
/* Mail box */
656665
#define MB_RFDX_PROD_IDX_MASK 0xFFFF
657666
#define REG_MB_RFD0_PROD_IDX 0x15E0
667+
#define REG_MB_RFD1_PROD_IDX 0x15E4
668+
#define REG_MB_RFD2_PROD_IDX 0x15E8
669+
#define REG_MB_RFD3_PROD_IDX 0x15EC
658670

659671
#define REG_TPD_PRI1_PIDX 0x15F0 /* 16bit,hi-tpd producer idx */
660672
#define REG_TPD_PRI0_PIDX 0x15F2 /* 16bit,lo-tpd producer idx */
661673
#define REG_TPD_PRI1_CIDX 0x15F4 /* 16bit,hi-tpd consumer idx */
662674
#define REG_TPD_PRI0_CIDX 0x15F6 /* 16bit,lo-tpd consumer idx */
675+
#define REG_TPD_PRI3_PIDX 0x1F18
676+
#define REG_TPD_PRI2_PIDX 0x1F1A
677+
#define REG_TPD_PRI3_CIDX 0x1F1C
678+
#define REG_TPD_PRI2_CIDX 0x1F1E
679+
663680

664681
#define REG_MB_RFD01_CONS_IDX 0x15F8
665682
#define MB_RFD0_CONS_IDX_MASK 0x0000FFFF
666683
#define MB_RFD1_CONS_IDX_MASK 0xFFFF0000
684+
#define REG_MB_RFD23_CONS_IDX 0x15FC
685+
#define MB_RFD2_CONS_IDX_MASK 0x0000FFFF
686+
#define MB_RFD3_CONS_IDX_MASK 0xFFFF0000
667687

668688
/* Interrupt Status Register */
669689
#define REG_ISR 0x1600
@@ -687,7 +707,7 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
687707
/* GPHY low power state interrupt */
688708
#define ISR_GPHY_LPW 0x00002000
689709
#define ISR_TXQ_TO_RST 0x00004000
690-
#define ISR_TX_PKT 0x00008000
710+
#define ISR_TX_PKT_0 0x00008000
691711
#define ISR_RX_PKT_0 0x00010000
692712
#define ISR_RX_PKT_1 0x00020000
693713
#define ISR_RX_PKT_2 0x00040000
@@ -699,6 +719,9 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
699719
#define ISR_NFERR_DETECTED 0x01000000
700720
#define ISR_CERR_DETECTED 0x02000000
701721
#define ISR_PHY_LINKDOWN 0x04000000
722+
#define ISR_TX_PKT_1 0x10000000
723+
#define ISR_TX_PKT_2 0x20000000
724+
#define ISR_TX_PKT_3 0x40000000
702725
#define ISR_DIS_INT 0x80000000
703726

704727
/* Interrupt Mask Register */
@@ -713,11 +736,15 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
713736
ISR_TXQ_TO_RST |\
714737
ISR_DMAW_TO_RST |\
715738
ISR_GPHY |\
716-
ISR_TX_PKT |\
717-
ISR_RX_PKT_0 |\
718739
ISR_GPHY_LPW |\
719740
ISR_PHY_LINKDOWN)
720741

742+
#define ISR_TX_PKT ( \
743+
ISR_TX_PKT_0 | \
744+
ISR_TX_PKT_1 | \
745+
ISR_TX_PKT_2 | \
746+
ISR_TX_PKT_3)
747+
721748
#define ISR_RX_PKT (\
722749
ISR_RX_PKT_0 |\
723750
ISR_RX_PKT_1 |\
@@ -771,6 +798,7 @@ void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed);
771798
#define REG_MT_VERSION 0x1F0C
772799

773800
#define MT_MAGIC 0xaabb1234
801+
#define MT_MODE_4Q BIT(0)
774802

775803
#define L1D_MPW_PHYID1 0xD01C /* V7 */
776804
#define L1D_MPW_PHYID2 0xD01D /* V1-V6 */

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