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4 | 4 | * |
5 | 5 | * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/ |
6 | 6 | */ |
| 7 | +#include <dt-bindings/phy/phy-am654-serdes.h> |
7 | 8 |
|
8 | 9 | &cbass_main { |
9 | 10 | msmc_ram: sram@70000000 { |
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61 | 62 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
62 | 63 | }; |
63 | 64 |
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| 65 | + serdes0: serdes@900000 { |
| 66 | + compatible = "ti,phy-am654-serdes"; |
| 67 | + reg = <0x0 0x900000 0x0 0x2000>; |
| 68 | + reg-names = "serdes"; |
| 69 | + #phy-cells = <2>; |
| 70 | + power-domains = <&k3_pds 153>; |
| 71 | + clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; |
| 72 | + clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; |
| 73 | + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; |
| 74 | + assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; |
| 75 | + ti,serdes-clk = <&serdes0_clk>; |
| 76 | + #clock-cells = <1>; |
| 77 | + mux-controls = <&serdes_mux 0>; |
| 78 | + }; |
| 79 | + |
| 80 | + serdes1: serdes@910000 { |
| 81 | + compatible = "ti,phy-am654-serdes"; |
| 82 | + reg = <0x0 0x910000 0x0 0x2000>; |
| 83 | + reg-names = "serdes"; |
| 84 | + #phy-cells = <2>; |
| 85 | + power-domains = <&k3_pds 154>; |
| 86 | + clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; |
| 87 | + clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; |
| 88 | + assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; |
| 89 | + assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; |
| 90 | + ti,serdes-clk = <&serdes1_clk>; |
| 91 | + #clock-cells = <1>; |
| 92 | + mux-controls = <&serdes_mux 1>; |
| 93 | + }; |
| 94 | + |
64 | 95 | main_uart0: serial@2800000 { |
65 | 96 | compatible = "ti,am654-uart"; |
66 | 97 | reg = <0x00 0x02800000 0x00 0x100>; |
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234 | 265 | #size-cells = <1>; |
235 | 266 | ranges = <0x0 0x0 0x00100000 0x1c000>; |
236 | 267 |
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| 268 | + serdes0_clk: serdes_clk@4080 { |
| 269 | + compatible = "syscon"; |
| 270 | + reg = <0x00004080 0x4>; |
| 271 | + }; |
| 272 | + |
| 273 | + serdes1_clk: serdes_clk@4090 { |
| 274 | + compatible = "syscon"; |
| 275 | + reg = <0x00004090 0x4>; |
| 276 | + }; |
| 277 | + |
237 | 278 | serdes_mux: mux-controller { |
238 | 279 | compatible = "mmio-mux"; |
239 | 280 | #mux-control-cells = <1>; |
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