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jayxurockchipLinus Walleij
jayxurockchip
authored and
Linus Walleij
committed
pinctrl: rockchip: add support for rk3568
RK3568 SoCs have 5 gpio controllers, each gpio has 32 pins. GPIO supports set iomux, pull, drive strength and schmitt. Signed-off-by: Jianqun Xu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
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‎drivers/pinctrl/pinctrl-rockchip.c‎

Lines changed: 290 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -63,8 +63,17 @@ enum rockchip_pinctrl_type {
6363
RK3308,
6464
RK3368,
6565
RK3399,
66+
RK3568,
6667
};
6768

69+
70+
/**
71+
* Generate a bitmask for setting a value (v) with a write mask bit in hiword
72+
* register 31:16 area.
73+
*/
74+
#define WRITE_MASK_VAL(h, l, v) \
75+
(GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l))))
76+
6877
/*
6978
* Encode variants of iomux registers into a type variable
7079
*/
@@ -292,6 +301,25 @@ struct rockchip_pin_bank {
292301
.pull_type[3] = pull3, \
293302
}
294303

304+
#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \
305+
{ \
306+
.bank_num = ID, \
307+
.pin = PIN, \
308+
.func = FUNC, \
309+
.route_offset = REG, \
310+
.route_val = VAL, \
311+
.route_location = FLAG, \
312+
}
313+
314+
#define RK_MUXROUTE_SAME(ID, PIN, FUNC, REG, VAL) \
315+
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_SAME)
316+
317+
#define RK_MUXROUTE_GRF(ID, PIN, FUNC, REG, VAL) \
318+
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_GRF)
319+
320+
#define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \
321+
PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU)
322+
295323
/**
296324
* struct rockchip_mux_recalced_data: represent a pin iomux data.
297325
* @num: bank number.
@@ -1396,6 +1424,102 @@ static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
13961424
},
13971425
};
13981426

1427+
static struct rockchip_mux_route_data rk3568_mux_route_data[] = {
1428+
RK_MUXROUTE_PMU(0, RK_PB7, 1, 0x0110, WRITE_MASK_VAL(1, 0, 0)), /* PWM0 IO mux M0 */
1429+
RK_MUXROUTE_PMU(0, RK_PC7, 2, 0x0110, WRITE_MASK_VAL(1, 0, 1)), /* PWM0 IO mux M1 */
1430+
RK_MUXROUTE_PMU(0, RK_PC0, 1, 0x0110, WRITE_MASK_VAL(3, 2, 0)), /* PWM1 IO mux M0 */
1431+
RK_MUXROUTE_PMU(0, RK_PB5, 4, 0x0110, WRITE_MASK_VAL(3, 2, 1)), /* PWM1 IO mux M1 */
1432+
RK_MUXROUTE_PMU(0, RK_PC1, 1, 0x0110, WRITE_MASK_VAL(5, 4, 0)), /* PWM2 IO mux M0 */
1433+
RK_MUXROUTE_PMU(0, RK_PB6, 4, 0x0110, WRITE_MASK_VAL(5, 4, 1)), /* PWM2 IO mux M1 */
1434+
RK_MUXROUTE_PMU(0, RK_PB3, 2, 0x0300, WRITE_MASK_VAL(0, 0, 0)), /* CAN0 IO mux M0 */
1435+
RK_MUXROUTE_GRF(2, RK_PA1, 4, 0x0300, WRITE_MASK_VAL(0, 0, 1)), /* CAN0 IO mux M1 */
1436+
RK_MUXROUTE_GRF(1, RK_PA1, 3, 0x0300, WRITE_MASK_VAL(2, 2, 0)), /* CAN1 IO mux M0 */
1437+
RK_MUXROUTE_GRF(4, RK_PC3, 3, 0x0300, WRITE_MASK_VAL(2, 2, 1)), /* CAN1 IO mux M1 */
1438+
RK_MUXROUTE_GRF(4, RK_PB5, 3, 0x0300, WRITE_MASK_VAL(4, 4, 0)), /* CAN2 IO mux M0 */
1439+
RK_MUXROUTE_GRF(2, RK_PB2, 4, 0x0300, WRITE_MASK_VAL(4, 4, 1)), /* CAN2 IO mux M1 */
1440+
RK_MUXROUTE_GRF(4, RK_PC4, 1, 0x0300, WRITE_MASK_VAL(6, 6, 0)), /* HPDIN IO mux M0 */
1441+
RK_MUXROUTE_PMU(0, RK_PC2, 2, 0x0300, WRITE_MASK_VAL(6, 6, 1)), /* HPDIN IO mux M1 */
1442+
RK_MUXROUTE_GRF(3, RK_PB1, 3, 0x0300, WRITE_MASK_VAL(8, 8, 0)), /* GMAC1 IO mux M0 */
1443+
RK_MUXROUTE_GRF(4, RK_PA7, 3, 0x0300, WRITE_MASK_VAL(8, 8, 1)), /* GMAC1 IO mux M1 */
1444+
RK_MUXROUTE_GRF(4, RK_PD1, 1, 0x0300, WRITE_MASK_VAL(10, 10, 0)), /* HDMITX IO mux M0 */
1445+
RK_MUXROUTE_PMU(0, RK_PC7, 1, 0x0300, WRITE_MASK_VAL(10, 10, 1)), /* HDMITX IO mux M1 */
1446+
RK_MUXROUTE_PMU(0, RK_PB6, 1, 0x0300, WRITE_MASK_VAL(14, 14, 0)), /* I2C2 IO mux M0 */
1447+
RK_MUXROUTE_GRF(4, RK_PB4, 1, 0x0300, WRITE_MASK_VAL(14, 14, 1)), /* I2C2 IO mux M1 */
1448+
RK_MUXROUTE_GRF(1, RK_PA0, 1, 0x0304, WRITE_MASK_VAL(0, 0, 0)), /* I2C3 IO mux M0 */
1449+
RK_MUXROUTE_GRF(3, RK_PB6, 4, 0x0304, WRITE_MASK_VAL(0, 0, 1)), /* I2C3 IO mux M1 */
1450+
RK_MUXROUTE_GRF(4, RK_PB2, 1, 0x0304, WRITE_MASK_VAL(2, 2, 0)), /* I2C4 IO mux M0 */
1451+
RK_MUXROUTE_GRF(2, RK_PB1, 2, 0x0304, WRITE_MASK_VAL(2, 2, 1)), /* I2C4 IO mux M1 */
1452+
RK_MUXROUTE_GRF(3, RK_PB4, 4, 0x0304, WRITE_MASK_VAL(4, 4, 0)), /* I2C5 IO mux M0 */
1453+
RK_MUXROUTE_GRF(4, RK_PD0, 2, 0x0304, WRITE_MASK_VAL(4, 4, 1)), /* I2C5 IO mux M1 */
1454+
RK_MUXROUTE_GRF(3, RK_PB1, 5, 0x0304, WRITE_MASK_VAL(14, 14, 0)), /* PWM8 IO mux M0 */
1455+
RK_MUXROUTE_GRF(1, RK_PD5, 4, 0x0304, WRITE_MASK_VAL(14, 14, 1)), /* PWM8 IO mux M1 */
1456+
RK_MUXROUTE_GRF(3, RK_PB2, 5, 0x0308, WRITE_MASK_VAL(0, 0, 0)), /* PWM9 IO mux M0 */
1457+
RK_MUXROUTE_GRF(1, RK_PD6, 4, 0x0308, WRITE_MASK_VAL(0, 0, 1)), /* PWM9 IO mux M1 */
1458+
RK_MUXROUTE_GRF(3, RK_PB5, 5, 0x0308, WRITE_MASK_VAL(2, 2, 0)), /* PWM10 IO mux M0 */
1459+
RK_MUXROUTE_GRF(2, RK_PA1, 2, 0x0308, WRITE_MASK_VAL(2, 2, 1)), /* PWM10 IO mux M1 */
1460+
RK_MUXROUTE_GRF(3, RK_PB6, 5, 0x0308, WRITE_MASK_VAL(4, 4, 0)), /* PWM11 IO mux M0 */
1461+
RK_MUXROUTE_GRF(4, RK_PC0, 3, 0x0308, WRITE_MASK_VAL(4, 4, 1)), /* PWM11 IO mux M1 */
1462+
RK_MUXROUTE_GRF(3, RK_PB7, 2, 0x0308, WRITE_MASK_VAL(6, 6, 0)), /* PWM12 IO mux M0 */
1463+
RK_MUXROUTE_GRF(4, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(6, 6, 1)), /* PWM12 IO mux M1 */
1464+
RK_MUXROUTE_GRF(3, RK_PC0, 2, 0x0308, WRITE_MASK_VAL(8, 8, 0)), /* PWM13 IO mux M0 */
1465+
RK_MUXROUTE_GRF(4, RK_PC6, 1, 0x0308, WRITE_MASK_VAL(8, 8, 1)), /* PWM13 IO mux M1 */
1466+
RK_MUXROUTE_GRF(3, RK_PC4, 1, 0x0308, WRITE_MASK_VAL(10, 10, 0)), /* PWM14 IO mux M0 */
1467+
RK_MUXROUTE_GRF(4, RK_PC2, 1, 0x0308, WRITE_MASK_VAL(10, 10, 1)), /* PWM14 IO mux M1 */
1468+
RK_MUXROUTE_GRF(3, RK_PC5, 1, 0x0308, WRITE_MASK_VAL(12, 12, 0)), /* PWM15 IO mux M0 */
1469+
RK_MUXROUTE_GRF(4, RK_PC3, 1, 0x0308, WRITE_MASK_VAL(12, 12, 1)), /* PWM15 IO mux M1 */
1470+
RK_MUXROUTE_GRF(3, RK_PD2, 3, 0x0308, WRITE_MASK_VAL(14, 14, 0)), /* SDMMC2 IO mux M0 */
1471+
RK_MUXROUTE_GRF(3, RK_PA5, 5, 0x0308, WRITE_MASK_VAL(14, 14, 1)), /* SDMMC2 IO mux M1 */
1472+
RK_MUXROUTE_PMU(0, RK_PB5, 2, 0x030c, WRITE_MASK_VAL(0, 0, 0)), /* SPI0 IO mux M0 */
1473+
RK_MUXROUTE_GRF(2, RK_PD3, 3, 0x030c, WRITE_MASK_VAL(0, 0, 1)), /* SPI0 IO mux M1 */
1474+
RK_MUXROUTE_GRF(2, RK_PB5, 3, 0x030c, WRITE_MASK_VAL(2, 2, 0)), /* SPI1 IO mux M0 */
1475+
RK_MUXROUTE_GRF(3, RK_PC3, 3, 0x030c, WRITE_MASK_VAL(2, 2, 1)), /* SPI1 IO mux M1 */
1476+
RK_MUXROUTE_GRF(2, RK_PC1, 4, 0x030c, WRITE_MASK_VAL(4, 4, 0)), /* SPI2 IO mux M0 */
1477+
RK_MUXROUTE_GRF(3, RK_PA0, 3, 0x030c, WRITE_MASK_VAL(4, 4, 1)), /* SPI2 IO mux M1 */
1478+
RK_MUXROUTE_GRF(4, RK_PB3, 4, 0x030c, WRITE_MASK_VAL(6, 6, 0)), /* SPI3 IO mux M0 */
1479+
RK_MUXROUTE_GRF(4, RK_PC2, 2, 0x030c, WRITE_MASK_VAL(6, 6, 1)), /* SPI3 IO mux M1 */
1480+
RK_MUXROUTE_GRF(2, RK_PB4, 2, 0x030c, WRITE_MASK_VAL(8, 8, 0)), /* UART1 IO mux M0 */
1481+
RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(8, 8, 1)), /* UART1 IO mux M1 */
1482+
RK_MUXROUTE_PMU(0, RK_PD1, 1, 0x030c, WRITE_MASK_VAL(10, 10, 0)), /* UART2 IO mux M0 */
1483+
RK_MUXROUTE_GRF(1, RK_PD5, 2, 0x030c, WRITE_MASK_VAL(10, 10, 1)), /* UART2 IO mux M1 */
1484+
RK_MUXROUTE_GRF(1, RK_PA1, 2, 0x030c, WRITE_MASK_VAL(12, 12, 0)), /* UART3 IO mux M0 */
1485+
RK_MUXROUTE_GRF(3, RK_PB7, 4, 0x030c, WRITE_MASK_VAL(12, 12, 1)), /* UART3 IO mux M1 */
1486+
RK_MUXROUTE_GRF(1, RK_PA6, 2, 0x030c, WRITE_MASK_VAL(14, 14, 0)), /* UART4 IO mux M0 */
1487+
RK_MUXROUTE_GRF(3, RK_PB2, 4, 0x030c, WRITE_MASK_VAL(14, 14, 1)), /* UART4 IO mux M1 */
1488+
RK_MUXROUTE_GRF(2, RK_PA2, 3, 0x0310, WRITE_MASK_VAL(0, 0, 0)), /* UART5 IO mux M0 */
1489+
RK_MUXROUTE_GRF(3, RK_PC2, 4, 0x0310, WRITE_MASK_VAL(0, 0, 1)), /* UART5 IO mux M1 */
1490+
RK_MUXROUTE_GRF(2, RK_PA4, 3, 0x0310, WRITE_MASK_VAL(2, 2, 0)), /* UART6 IO mux M0 */
1491+
RK_MUXROUTE_GRF(1, RK_PD5, 3, 0x0310, WRITE_MASK_VAL(2, 2, 1)), /* UART6 IO mux M1 */
1492+
RK_MUXROUTE_GRF(2, RK_PA6, 3, 0x0310, WRITE_MASK_VAL(5, 4, 0)), /* UART7 IO mux M0 */
1493+
RK_MUXROUTE_GRF(3, RK_PC4, 4, 0x0310, WRITE_MASK_VAL(5, 4, 1)), /* UART7 IO mux M1 */
1494+
RK_MUXROUTE_GRF(4, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(5, 4, 2)), /* UART7 IO mux M2 */
1495+
RK_MUXROUTE_GRF(2, RK_PC5, 3, 0x0310, WRITE_MASK_VAL(6, 6, 0)), /* UART8 IO mux M0 */
1496+
RK_MUXROUTE_GRF(2, RK_PD7, 4, 0x0310, WRITE_MASK_VAL(6, 6, 1)), /* UART8 IO mux M1 */
1497+
RK_MUXROUTE_GRF(2, RK_PB0, 3, 0x0310, WRITE_MASK_VAL(9, 8, 0)), /* UART9 IO mux M0 */
1498+
RK_MUXROUTE_GRF(4, RK_PC5, 4, 0x0310, WRITE_MASK_VAL(9, 8, 1)), /* UART9 IO mux M1 */
1499+
RK_MUXROUTE_GRF(4, RK_PA4, 4, 0x0310, WRITE_MASK_VAL(9, 8, 2)), /* UART9 IO mux M2 */
1500+
RK_MUXROUTE_GRF(1, RK_PA2, 1, 0x0310, WRITE_MASK_VAL(11, 10, 0)), /* I2S1 IO mux M0 */
1501+
RK_MUXROUTE_GRF(3, RK_PC6, 4, 0x0310, WRITE_MASK_VAL(11, 10, 1)), /* I2S1 IO mux M1 */
1502+
RK_MUXROUTE_GRF(2, RK_PD0, 5, 0x0310, WRITE_MASK_VAL(11, 10, 2)), /* I2S1 IO mux M2 */
1503+
RK_MUXROUTE_GRF(2, RK_PC1, 1, 0x0310, WRITE_MASK_VAL(12, 12, 0)), /* I2S2 IO mux M0 */
1504+
RK_MUXROUTE_GRF(4, RK_PB6, 5, 0x0310, WRITE_MASK_VAL(12, 12, 1)), /* I2S2 IO mux M1 */
1505+
RK_MUXROUTE_GRF(3, RK_PA2, 4, 0x0310, WRITE_MASK_VAL(14, 14, 0)), /* I2S3 IO mux M0 */
1506+
RK_MUXROUTE_GRF(4, RK_PC2, 5, 0x0310, WRITE_MASK_VAL(14, 14, 1)), /* I2S3 IO mux M1 */
1507+
RK_MUXROUTE_GRF(1, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1508+
RK_MUXROUTE_GRF(1, RK_PA6, 3, 0x0314, WRITE_MASK_VAL(1, 0, 0)), /* PDM IO mux M0 */
1509+
RK_MUXROUTE_GRF(3, RK_PD6, 5, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1510+
RK_MUXROUTE_GRF(4, RK_PA0, 4, 0x0314, WRITE_MASK_VAL(1, 0, 1)), /* PDM IO mux M1 */
1511+
RK_MUXROUTE_GRF(3, RK_PC4, 5, 0x0314, WRITE_MASK_VAL(1, 0, 2)), /* PDM IO mux M2 */
1512+
RK_MUXROUTE_PMU(0, RK_PA5, 3, 0x0314, WRITE_MASK_VAL(3, 2, 0)), /* PCIE20 IO mux M0 */
1513+
RK_MUXROUTE_GRF(2, RK_PD0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 1)), /* PCIE20 IO mux M1 */
1514+
RK_MUXROUTE_GRF(1, RK_PB0, 4, 0x0314, WRITE_MASK_VAL(3, 2, 2)), /* PCIE20 IO mux M2 */
1515+
RK_MUXROUTE_PMU(0, RK_PA4, 3, 0x0314, WRITE_MASK_VAL(5, 4, 0)), /* PCIE30X1 IO mux M0 */
1516+
RK_MUXROUTE_GRF(2, RK_PD2, 4, 0x0314, WRITE_MASK_VAL(5, 4, 1)), /* PCIE30X1 IO mux M1 */
1517+
RK_MUXROUTE_GRF(1, RK_PA5, 4, 0x0314, WRITE_MASK_VAL(5, 4, 2)), /* PCIE30X1 IO mux M2 */
1518+
RK_MUXROUTE_PMU(0, RK_PA6, 2, 0x0314, WRITE_MASK_VAL(7, 6, 0)), /* PCIE30X2 IO mux M0 */
1519+
RK_MUXROUTE_GRF(2, RK_PD4, 4, 0x0314, WRITE_MASK_VAL(7, 6, 1)), /* PCIE30X2 IO mux M1 */
1520+
RK_MUXROUTE_GRF(4, RK_PC2, 4, 0x0314, WRITE_MASK_VAL(7, 6, 2)), /* PCIE30X2 IO mux M2 */
1521+
};
1522+
13991523
static bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin,
14001524
int mux, u32 *loc, u32 *reg, u32 *value)
14011525
{
@@ -2104,6 +2228,68 @@ static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
21042228
*bit = (pin_num % 8) * 2;
21052229
}
21062230

2231+
#define RK3568_PULL_PMU_OFFSET 0x20
2232+
#define RK3568_PULL_GRF_OFFSET 0x80
2233+
#define RK3568_PULL_BITS_PER_PIN 2
2234+
#define RK3568_PULL_PINS_PER_REG 8
2235+
#define RK3568_PULL_BANK_STRIDE 0x10
2236+
2237+
static void rk3568_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
2238+
int pin_num, struct regmap **regmap,
2239+
int *reg, u8 *bit)
2240+
{
2241+
struct rockchip_pinctrl *info = bank->drvdata;
2242+
2243+
if (bank->bank_num == 0) {
2244+
*regmap = info->regmap_pmu;
2245+
*reg = RK3568_PULL_PMU_OFFSET;
2246+
*reg += bank->bank_num * RK3568_PULL_BANK_STRIDE;
2247+
*reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
2248+
2249+
*bit = pin_num % RK3568_PULL_PINS_PER_REG;
2250+
*bit *= RK3568_PULL_BITS_PER_PIN;
2251+
} else {
2252+
*regmap = info->regmap_base;
2253+
*reg = RK3568_PULL_GRF_OFFSET;
2254+
*reg += (bank->bank_num - 1) * RK3568_PULL_BANK_STRIDE;
2255+
*reg += ((pin_num / RK3568_PULL_PINS_PER_REG) * 4);
2256+
2257+
*bit = (pin_num % RK3568_PULL_PINS_PER_REG);
2258+
*bit *= RK3568_PULL_BITS_PER_PIN;
2259+
}
2260+
}
2261+
2262+
#define RK3568_DRV_PMU_OFFSET 0x70
2263+
#define RK3568_DRV_GRF_OFFSET 0x200
2264+
#define RK3568_DRV_BITS_PER_PIN 8
2265+
#define RK3568_DRV_PINS_PER_REG 2
2266+
#define RK3568_DRV_BANK_STRIDE 0x40
2267+
2268+
static void rk3568_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
2269+
int pin_num, struct regmap **regmap,
2270+
int *reg, u8 *bit)
2271+
{
2272+
struct rockchip_pinctrl *info = bank->drvdata;
2273+
2274+
/* The first 32 pins of the first bank are located in PMU */
2275+
if (bank->bank_num == 0) {
2276+
*regmap = info->regmap_pmu;
2277+
*reg = RK3568_DRV_PMU_OFFSET;
2278+
*reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
2279+
2280+
*bit = pin_num % RK3568_DRV_PINS_PER_REG;
2281+
*bit *= RK3568_DRV_BITS_PER_PIN;
2282+
} else {
2283+
*regmap = info->regmap_base;
2284+
*reg = RK3568_DRV_GRF_OFFSET;
2285+
*reg += (bank->bank_num - 1) * RK3568_DRV_BANK_STRIDE;
2286+
*reg += ((pin_num / RK3568_DRV_PINS_PER_REG) * 4);
2287+
2288+
*bit = (pin_num % RK3568_DRV_PINS_PER_REG);
2289+
*bit *= RK3568_DRV_BITS_PER_PIN;
2290+
}
2291+
}
2292+
21072293
static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = {
21082294
{ 2, 4, 8, 12, -1, -1, -1, -1 },
21092295
{ 3, 6, 9, 12, -1, -1, -1, -1 },
@@ -2204,6 +2390,11 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
22042390
bank->bank_num, pin_num, strength);
22052391

22062392
ctrl->drv_calc_reg(bank, pin_num, &regmap, &reg, &bit);
2393+
if (ctrl->type == RK3568) {
2394+
rmask_bits = RK3568_DRV_BITS_PER_PIN;
2395+
ret = (1 << (strength + 1)) - 1;
2396+
goto config;
2397+
}
22072398

22082399
ret = -EINVAL;
22092400
for (i = 0; i < ARRAY_SIZE(rockchip_perpin_drv_list[drv_type]); i++) {
@@ -2273,6 +2464,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
22732464
return -EINVAL;
22742465
}
22752466

2467+
config:
22762468
/* enable the write to the equivalent lower bits */
22772469
data = ((1 << rmask_bits) - 1) << (bit + 16);
22782470
rmask = data | (data >> 16);
@@ -2375,6 +2567,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
23752567
case RK3308:
23762568
case RK3368:
23772569
case RK3399:
2570+
case RK3568:
23782571
pull_type = bank->pull_type[pin_num / 8];
23792572
ret = -EINVAL;
23802573
for (i = 0; i < ARRAY_SIZE(rockchip_pull_list[pull_type]);
@@ -2384,6 +2577,14 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
23842577
break;
23852578
}
23862579
}
2580+
/*
2581+
* In the TRM, pull-up being 1 for everything except the GPIO0_D0-D6,
2582+
* where that pull up value becomes 3.
2583+
*/
2584+
if (ctrl->type == RK3568 && bank->bank_num == 0 && pin_num >= 27 && pin_num <= 30) {
2585+
if (ret == 1)
2586+
ret = 3;
2587+
}
23872588

23882589
if (ret < 0) {
23892590
dev_err(info->dev, "unsupported pull setting %d\n",
@@ -2428,6 +2629,35 @@ static int rk3328_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
24282629
return 0;
24292630
}
24302631

2632+
#define RK3568_SCHMITT_BITS_PER_PIN 2
2633+
#define RK3568_SCHMITT_PINS_PER_REG 8
2634+
#define RK3568_SCHMITT_BANK_STRIDE 0x10
2635+
#define RK3568_SCHMITT_GRF_OFFSET 0xc0
2636+
#define RK3568_SCHMITT_PMUGRF_OFFSET 0x30
2637+
2638+
static int rk3568_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
2639+
int pin_num,
2640+
struct regmap **regmap,
2641+
int *reg, u8 *bit)
2642+
{
2643+
struct rockchip_pinctrl *info = bank->drvdata;
2644+
2645+
if (bank->bank_num == 0) {
2646+
*regmap = info->regmap_pmu;
2647+
*reg = RK3568_SCHMITT_PMUGRF_OFFSET;
2648+
} else {
2649+
*regmap = info->regmap_base;
2650+
*reg = RK3568_SCHMITT_GRF_OFFSET;
2651+
*reg += (bank->bank_num - 1) * RK3568_SCHMITT_BANK_STRIDE;
2652+
}
2653+
2654+
*reg += ((pin_num / RK3568_SCHMITT_PINS_PER_REG) * 4);
2655+
*bit = pin_num % RK3568_SCHMITT_PINS_PER_REG;
2656+
*bit *= RK3568_SCHMITT_BITS_PER_PIN;
2657+
2658+
return 0;
2659+
}
2660+
24312661
static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
24322662
{
24332663
struct rockchip_pinctrl *info = bank->drvdata;
@@ -2446,6 +2676,13 @@ static int rockchip_get_schmitt(struct rockchip_pin_bank *bank, int pin_num)
24462676
return ret;
24472677

24482678
data >>= bit;
2679+
switch (ctrl->type) {
2680+
case RK3568:
2681+
return data & ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1);
2682+
default:
2683+
break;
2684+
}
2685+
24492686
return data & 0x1;
24502687
}
24512688

@@ -2467,8 +2704,17 @@ static int rockchip_set_schmitt(struct rockchip_pin_bank *bank,
24672704
return ret;
24682705

24692706
/* enable the write to the equivalent lower bits */
2470-
data = BIT(bit + 16) | (enable << bit);
2471-
rmask = BIT(bit + 16) | BIT(bit);
2707+
switch (ctrl->type) {
2708+
case RK3568:
2709+
data = ((1 << RK3568_SCHMITT_BITS_PER_PIN) - 1) << (bit + 16);
2710+
rmask = data | (data >> 16);
2711+
data |= ((enable ? 0x2 : 0x1) << bit);
2712+
break;
2713+
default:
2714+
data = BIT(bit + 16) | (enable << bit);
2715+
rmask = BIT(bit + 16) | BIT(bit);
2716+
break;
2717+
}
24722718

24732719
return regmap_update_bits(regmap, reg, rmask, data);
24742720
}
@@ -2642,6 +2888,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
26422888
case RK3308:
26432889
case RK3368:
26442890
case RK3399:
2891+
case RK3568:
26452892
return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
26462893
}
26472894

@@ -4213,6 +4460,45 @@ static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
42134460
.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
42144461
};
42154462

4463+
static struct rockchip_pin_bank rk3568_pin_banks[] = {
4464+
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4465+
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4466+
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT,
4467+
IOMUX_SOURCE_PMU | IOMUX_WIDTH_4BIT),
4468+
PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", IOMUX_WIDTH_4BIT,
4469+
IOMUX_WIDTH_4BIT,
4470+
IOMUX_WIDTH_4BIT,
4471+
IOMUX_WIDTH_4BIT),
4472+
PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", IOMUX_WIDTH_4BIT,
4473+
IOMUX_WIDTH_4BIT,
4474+
IOMUX_WIDTH_4BIT,
4475+
IOMUX_WIDTH_4BIT),
4476+
PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", IOMUX_WIDTH_4BIT,
4477+
IOMUX_WIDTH_4BIT,
4478+
IOMUX_WIDTH_4BIT,
4479+
IOMUX_WIDTH_4BIT),
4480+
PIN_BANK_IOMUX_FLAGS(4, 32, "gpio4", IOMUX_WIDTH_4BIT,
4481+
IOMUX_WIDTH_4BIT,
4482+
IOMUX_WIDTH_4BIT,
4483+
IOMUX_WIDTH_4BIT),
4484+
};
4485+
4486+
static struct rockchip_pin_ctrl rk3568_pin_ctrl = {
4487+
.pin_banks = rk3568_pin_banks,
4488+
.nr_banks = ARRAY_SIZE(rk3568_pin_banks),
4489+
.label = "RK3568-GPIO",
4490+
.type = RK3568,
4491+
.grf_mux_offset = 0x0,
4492+
.pmu_mux_offset = 0x0,
4493+
.grf_drv_offset = 0x0200,
4494+
.pmu_drv_offset = 0x0070,
4495+
.iomux_routes = rk3568_mux_route_data,
4496+
.niomux_routes = ARRAY_SIZE(rk3568_mux_route_data),
4497+
.pull_calc_reg = rk3568_calc_pull_reg_and_bit,
4498+
.drv_calc_reg = rk3568_calc_drv_reg_and_bit,
4499+
.schmitt_calc_reg = rk3568_calc_schmitt_reg_and_bit,
4500+
};
4501+
42164502
static const struct of_device_id rockchip_pinctrl_dt_match[] = {
42174503
{ .compatible = "rockchip,px30-pinctrl",
42184504
.data = &px30_pin_ctrl },
@@ -4242,6 +4528,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
42424528
.data = &rk3368_pin_ctrl },
42434529
{ .compatible = "rockchip,rk3399-pinctrl",
42444530
.data = &rk3399_pin_ctrl },
4531+
{ .compatible = "rockchip,rk3568-pinctrl",
4532+
.data = &rk3568_pin_ctrl },
42454533
{},
42464534
};
42474535

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