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7 | 7 | * |
8 | 8 | * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved. |
9 | 9 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
10 | | - * Copyright(c) 2016 Intel Deutschland GmbH |
| 10 | + * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
11 | 11 | * |
12 | 12 | * This program is free software; you can redistribute it and/or modify |
13 | 13 | * it under the terms of version 2 of the GNU General Public License as |
|
34 | 34 | * |
35 | 35 | * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved. |
36 | 36 | * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH |
37 | | - * Copyright(c) 2016 Intel Deutschland GmbH |
| 37 | + * Copyright(c) 2016 - 2017 Intel Deutschland GmbH |
38 | 38 | * All rights reserved. |
39 | 39 | * |
40 | 40 | * Redistribution and use in source and binary forms, with or without |
@@ -2075,48 +2075,32 @@ static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block) |
2075 | 2075 |
|
2076 | 2076 | void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq) |
2077 | 2077 | { |
2078 | | - struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); |
2079 | | - u32 scd_sram_addr; |
2080 | | - u8 buf[16]; |
2081 | | - int cnt; |
| 2078 | + u32 txq_id = txq->id; |
| 2079 | + u32 status; |
| 2080 | + bool active; |
| 2081 | + u8 fifo; |
2082 | 2082 |
|
2083 | | - IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n", |
2084 | | - txq->read_ptr, txq->write_ptr); |
2085 | | - |
2086 | | - if (trans->cfg->use_tfh) |
| 2083 | + if (trans->cfg->use_tfh) { |
| 2084 | + IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id, |
| 2085 | + txq->read_ptr, txq->write_ptr); |
2087 | 2086 | /* TODO: access new SCD registers and dump them */ |
2088 | 2087 | return; |
2089 | | - |
2090 | | - scd_sram_addr = trans_pcie->scd_base_addr + |
2091 | | - SCD_TX_STTS_QUEUE_OFFSET(txq->id); |
2092 | | - iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf)); |
2093 | | - |
2094 | | - iwl_print_hex_error(trans, buf, sizeof(buf)); |
2095 | | - |
2096 | | - for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++) |
2097 | | - IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt, |
2098 | | - iwl_read_direct32(trans, FH_TX_TRB_REG(cnt))); |
2099 | | - |
2100 | | - for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) { |
2101 | | - u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt)); |
2102 | | - u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; |
2103 | | - bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); |
2104 | | - u32 tbl_dw = |
2105 | | - iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr + |
2106 | | - SCD_TRANS_TBL_OFFSET_QUEUE(cnt)); |
2107 | | - |
2108 | | - if (cnt & 0x1) |
2109 | | - tbl_dw = (tbl_dw & 0xFFFF0000) >> 16; |
2110 | | - else |
2111 | | - tbl_dw = tbl_dw & 0x0000FFFF; |
2112 | | - |
2113 | | - IWL_ERR(trans, |
2114 | | - "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n", |
2115 | | - cnt, active ? "" : "in", fifo, tbl_dw, |
2116 | | - iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) & |
2117 | | - (TFD_QUEUE_SIZE_MAX - 1), |
2118 | | - iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt))); |
2119 | 2088 | } |
| 2089 | + |
| 2090 | + status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id)); |
| 2091 | + fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7; |
| 2092 | + active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE)); |
| 2093 | + |
| 2094 | + IWL_ERR(trans, |
| 2095 | + "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n", |
| 2096 | + txq_id, active ? "" : "in", fifo, |
| 2097 | + jiffies_to_msecs(txq->wd_timeout), |
| 2098 | + txq->read_ptr, txq->write_ptr, |
| 2099 | + iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) & |
| 2100 | + (TFD_QUEUE_SIZE_MAX - 1), |
| 2101 | + iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) & |
| 2102 | + (TFD_QUEUE_SIZE_MAX - 1), |
| 2103 | + iwl_read_direct32(trans, FH_TX_TRB_REG(fifo))); |
2120 | 2104 | } |
2121 | 2105 |
|
2122 | 2106 | static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm) |
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