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Ander Conselvan de Oliveira
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drm/i915: Move shared dpll struct definitions to separate header file
Move the declarations related to shared dplls from i915_drv.h to their own header file. The code that became the shared dpll infrastructre was first introcude in commit ee7b9f9 ("drm/i915: manage PCH PLLs separately from pipes"), hence the 2012-2016 copyright years in the new header file. Signed-off-by: Ander Conselvan de Oliveira <[email protected]> Reviewed-by: Maarten Lankhorst <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/1457451987-17466-6-git-send-email-ander.conselvan.de.oliveira@intel.com
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‎drivers/gpu/drm/i915/i915_drv.h‎

Lines changed: 1 addition & 75 deletions
Original file line numberDiff line numberDiff line change
@@ -53,6 +53,7 @@
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include "intel_guc.h"
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#include "intel_dpll_mgr.h"
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/* General customization:
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*/
@@ -340,81 +341,6 @@ struct drm_i915_file_private {
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unsigned int bsd_ring;
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};
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343-
enum intel_dpll_id {
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DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
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/* real shared dpll ids must be >= 0 */
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DPLL_ID_PCH_PLL_A = 0,
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DPLL_ID_PCH_PLL_B = 1,
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/* hsw/bdw */
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DPLL_ID_WRPLL1 = 0,
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DPLL_ID_WRPLL2 = 1,
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DPLL_ID_SPLL = 2,
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/* skl */
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DPLL_ID_SKL_DPLL1 = 0,
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DPLL_ID_SKL_DPLL2 = 1,
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DPLL_ID_SKL_DPLL3 = 2,
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};
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#define I915_NUM_PLLS 3
359-
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struct intel_dpll_hw_state {
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/* i9xx, pch plls */
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uint32_t dpll;
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uint32_t dpll_md;
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uint32_t fp0;
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uint32_t fp1;
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/* hsw, bdw */
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uint32_t wrpll;
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uint32_t spll;
370-
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/* skl */
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/*
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* DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
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* lower part of ctrl1 and they get shifted into position when writing
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* the register. This allows us to easily compare the state to share
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* the DPLL.
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*/
378-
uint32_t ctrl1;
379-
/* HDMI only, 0 when used for DP */
380-
uint32_t cfgcr1, cfgcr2;
381-
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/* bxt */
383-
uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
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pcsdw12;
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};
386-
387-
struct intel_shared_dpll_config {
388-
unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
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struct intel_dpll_hw_state hw_state;
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};
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struct intel_shared_dpll {
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struct intel_shared_dpll_config config;
394-
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int active; /* count of number of active CRTCs (i.e. DPMS on) */
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bool on; /* is the PLL actually active? Disabled during modeset */
397-
const char *name;
398-
/* should match the index in the dev_priv->shared_dplls array */
399-
enum intel_dpll_id id;
400-
/* The mode_set hook is optional and should be used together with the
401-
* intel_prepare_shared_dpll function. */
402-
void (*mode_set)(struct drm_i915_private *dev_priv,
403-
struct intel_shared_dpll *pll);
404-
void (*enable)(struct drm_i915_private *dev_priv,
405-
struct intel_shared_dpll *pll);
406-
void (*disable)(struct drm_i915_private *dev_priv,
407-
struct intel_shared_dpll *pll);
408-
bool (*get_hw_state)(struct drm_i915_private *dev_priv,
409-
struct intel_shared_dpll *pll,
410-
struct intel_dpll_hw_state *hw_state);
411-
};
412-
413-
#define SKL_DPLL0 0
414-
#define SKL_DPLL1 1
415-
#define SKL_DPLL2 2
416-
#define SKL_DPLL3 3
417-
418344
/* Used by dp and fdi links */
419345
struct intel_link_m_n {
420346
uint32_t tu;

‎drivers/gpu/drm/i915/intel_dpll_mgr.h‎

Lines changed: 106 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,106 @@
1+
/*
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* Copyright © 2012-2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#ifndef _INTEL_DPLL_MGR_H_
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#define _INTEL_DPLL_MGR_H_
27+
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struct drm_i915_private;
29+
30+
enum intel_dpll_id {
31+
DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
32+
/* real shared dpll ids must be >= 0 */
33+
DPLL_ID_PCH_PLL_A = 0,
34+
DPLL_ID_PCH_PLL_B = 1,
35+
/* hsw/bdw */
36+
DPLL_ID_WRPLL1 = 0,
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DPLL_ID_WRPLL2 = 1,
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DPLL_ID_SPLL = 2,
39+
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/* skl */
41+
DPLL_ID_SKL_DPLL1 = 0,
42+
DPLL_ID_SKL_DPLL2 = 1,
43+
DPLL_ID_SKL_DPLL3 = 2,
44+
};
45+
#define I915_NUM_PLLS 3
46+
47+
struct intel_dpll_hw_state {
48+
/* i9xx, pch plls */
49+
uint32_t dpll;
50+
uint32_t dpll_md;
51+
uint32_t fp0;
52+
uint32_t fp1;
53+
54+
/* hsw, bdw */
55+
uint32_t wrpll;
56+
uint32_t spll;
57+
58+
/* skl */
59+
/*
60+
* DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
61+
* lower part of ctrl1 and they get shifted into position when writing
62+
* the register. This allows us to easily compare the state to share
63+
* the DPLL.
64+
*/
65+
uint32_t ctrl1;
66+
/* HDMI only, 0 when used for DP */
67+
uint32_t cfgcr1, cfgcr2;
68+
69+
/* bxt */
70+
uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
71+
pcsdw12;
72+
};
73+
74+
struct intel_shared_dpll_config {
75+
unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
76+
struct intel_dpll_hw_state hw_state;
77+
};
78+
79+
struct intel_shared_dpll {
80+
struct intel_shared_dpll_config config;
81+
82+
int active; /* count of number of active CRTCs (i.e. DPMS on) */
83+
bool on; /* is the PLL actually active? Disabled during modeset */
84+
const char *name;
85+
/* should match the index in the dev_priv->shared_dplls array */
86+
enum intel_dpll_id id;
87+
/* The mode_set hook is optional and should be used together with the
88+
* intel_prepare_shared_dpll function. */
89+
void (*mode_set)(struct drm_i915_private *dev_priv,
90+
struct intel_shared_dpll *pll);
91+
void (*enable)(struct drm_i915_private *dev_priv,
92+
struct intel_shared_dpll *pll);
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void (*disable)(struct drm_i915_private *dev_priv,
94+
struct intel_shared_dpll *pll);
95+
bool (*get_hw_state)(struct drm_i915_private *dev_priv,
96+
struct intel_shared_dpll *pll,
97+
struct intel_dpll_hw_state *hw_state);
98+
};
99+
100+
#define SKL_DPLL0 0
101+
#define SKL_DPLL1 1
102+
#define SKL_DPLL2 2
103+
#define SKL_DPLL3 3
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106+
#endif /* _INTEL_DPLL_MGR_H_ */

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