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tmlindFelipe Balbi
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usb: musb: Remove ifdefs for musb_host_rx in musb_host.c part5
Remove ifdefs for musb_host_rx to get closer to building in all the DMA drivers. Signed-off-by: Tony Lindgren <[email protected]> Signed-off-by: Felipe Balbi <[email protected]>
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drivers/usb/musb/musb_host.c

Lines changed: 140 additions & 114 deletions
Original file line numberDiff line numberDiff line change
@@ -1661,6 +1661,122 @@ static int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
16611661

16621662
return done;
16631663
}
1664+
1665+
/* Disadvantage of using mode 1:
1666+
* It's basically usable only for mass storage class; essentially all
1667+
* other protocols also terminate transfers on short packets.
1668+
*
1669+
* Details:
1670+
* An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1671+
* If you try to use mode 1 for (transfer_buffer_length - 512), and try
1672+
* to use the extra IN token to grab the last packet using mode 0, then
1673+
* the problem is that you cannot be sure when the device will send the
1674+
* last packet and RxPktRdy set. Sometimes the packet is recd too soon
1675+
* such that it gets lost when RxCSR is re-set at the end of the mode 1
1676+
* transfer, while sometimes it is recd just a little late so that if you
1677+
* try to configure for mode 0 soon after the mode 1 transfer is
1678+
* completed, you will find rxcount 0. Okay, so you might think why not
1679+
* wait for an interrupt when the pkt is recd. Well, you won't get any!
1680+
*/
1681+
static int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma,
1682+
struct musb_hw_ep *hw_ep,
1683+
struct musb_qh *qh,
1684+
struct urb *urb,
1685+
size_t len,
1686+
u8 iso_err)
1687+
{
1688+
struct musb *musb = hw_ep->musb;
1689+
void __iomem *epio = hw_ep->regs;
1690+
struct dma_channel *channel = hw_ep->rx_channel;
1691+
u16 rx_count, val;
1692+
int length, pipe, done;
1693+
dma_addr_t buf;
1694+
1695+
rx_count = musb_readw(epio, MUSB_RXCOUNT);
1696+
pipe = urb->pipe;
1697+
1698+
if (usb_pipeisoc(pipe)) {
1699+
int d_status = 0;
1700+
struct usb_iso_packet_descriptor *d;
1701+
1702+
d = urb->iso_frame_desc + qh->iso_idx;
1703+
1704+
if (iso_err) {
1705+
d_status = -EILSEQ;
1706+
urb->error_count++;
1707+
}
1708+
if (rx_count > d->length) {
1709+
if (d_status == 0) {
1710+
d_status = -EOVERFLOW;
1711+
urb->error_count++;
1712+
}
1713+
dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",
1714+
rx_count, d->length);
1715+
1716+
length = d->length;
1717+
} else
1718+
length = rx_count;
1719+
d->status = d_status;
1720+
buf = urb->transfer_dma + d->offset;
1721+
} else {
1722+
length = rx_count;
1723+
buf = urb->transfer_dma + urb->actual_length;
1724+
}
1725+
1726+
channel->desired_mode = 0;
1727+
#ifdef USE_MODE1
1728+
/* because of the issue below, mode 1 will
1729+
* only rarely behave with correct semantics.
1730+
*/
1731+
if ((urb->transfer_flags & URB_SHORT_NOT_OK)
1732+
&& (urb->transfer_buffer_length - urb->actual_length)
1733+
> qh->maxpacket)
1734+
channel->desired_mode = 1;
1735+
if (rx_count < hw_ep->max_packet_sz_rx) {
1736+
length = rx_count;
1737+
channel->desired_mode = 0;
1738+
} else {
1739+
length = urb->transfer_buffer_length;
1740+
}
1741+
#endif
1742+
1743+
/* See comments above on disadvantages of using mode 1 */
1744+
val = musb_readw(epio, MUSB_RXCSR);
1745+
val &= ~MUSB_RXCSR_H_REQPKT;
1746+
1747+
if (channel->desired_mode == 0)
1748+
val &= ~MUSB_RXCSR_H_AUTOREQ;
1749+
else
1750+
val |= MUSB_RXCSR_H_AUTOREQ;
1751+
val |= MUSB_RXCSR_DMAENAB;
1752+
1753+
/* autoclear shouldn't be set in high bandwidth */
1754+
if (qh->hb_mult == 1)
1755+
val |= MUSB_RXCSR_AUTOCLEAR;
1756+
1757+
musb_writew(epio, MUSB_RXCSR, MUSB_RXCSR_H_WZC_BITS | val);
1758+
1759+
/* REVISIT if when actual_length != 0,
1760+
* transfer_buffer_length needs to be
1761+
* adjusted first...
1762+
*/
1763+
done = dma->channel_program(channel, qh->maxpacket,
1764+
channel->desired_mode,
1765+
buf, length);
1766+
1767+
if (!done) {
1768+
dma->channel_release(channel);
1769+
hw_ep->rx_channel = NULL;
1770+
channel = NULL;
1771+
val = musb_readw(epio, MUSB_RXCSR);
1772+
val &= ~(MUSB_RXCSR_DMAENAB
1773+
| MUSB_RXCSR_H_AUTOREQ
1774+
| MUSB_RXCSR_AUTOCLEAR);
1775+
musb_writew(epio, MUSB_RXCSR, val);
1776+
}
1777+
1778+
return done;
1779+
}
16641780
#else
16651781
static inline int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
16661782
struct musb_hw_ep *hw_ep,
@@ -1670,6 +1786,16 @@ static inline int musb_rx_dma_inventra_cppi41(struct dma_controller *dma,
16701786
{
16711787
return false;
16721788
}
1789+
1790+
static inline int musb_rx_dma_in_inventra_cppi41(struct dma_controller *dma,
1791+
struct musb_hw_ep *hw_ep,
1792+
struct musb_qh *qh,
1793+
struct urb *urb,
1794+
size_t len,
1795+
u8 iso_err)
1796+
{
1797+
return false;
1798+
}
16731799
#endif
16741800

16751801
/*
@@ -1859,121 +1985,21 @@ void musb_host_rx(struct musb *musb, u8 epnum)
18591985
/* we are expecting IN packets */
18601986
if ((musb_dma_inventra(musb) || musb_dma_ux500(musb) ||
18611987
musb_dma_cppi41(musb)) && dma) {
1862-
struct dma_controller *c;
1863-
u16 rx_count;
1864-
int ret, length;
1865-
dma_addr_t buf;
1866-
1867-
rx_count = musb_readw(epio, MUSB_RXCOUNT);
1868-
1869-
dev_dbg(musb->controller, "RX%d count %d, buffer 0x%llx len %d/%d\n",
1870-
epnum, rx_count,
1871-
(unsigned long long) urb->transfer_dma
1872-
+ urb->actual_length,
1873-
qh->offset,
1874-
urb->transfer_buffer_length);
1875-
1876-
c = musb->dma_controller;
1877-
1878-
if (usb_pipeisoc(pipe)) {
1879-
int d_status = 0;
1880-
struct usb_iso_packet_descriptor *d;
1881-
1882-
d = urb->iso_frame_desc + qh->iso_idx;
1883-
1884-
if (iso_err) {
1885-
d_status = -EILSEQ;
1886-
urb->error_count++;
1887-
}
1888-
if (rx_count > d->length) {
1889-
if (d_status == 0) {
1890-
d_status = -EOVERFLOW;
1891-
urb->error_count++;
1892-
}
1893-
dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
1894-
rx_count, d->length);
1895-
1896-
length = d->length;
1897-
} else
1898-
length = rx_count;
1899-
d->status = d_status;
1900-
buf = urb->transfer_dma + d->offset;
1901-
} else {
1902-
length = rx_count;
1903-
buf = urb->transfer_dma +
1904-
urb->actual_length;
1905-
}
1906-
1907-
dma->desired_mode = 0;
1908-
#ifdef USE_MODE1
1909-
/* because of the issue below, mode 1 will
1910-
* only rarely behave with correct semantics.
1911-
*/
1912-
if ((urb->transfer_flags &
1913-
URB_SHORT_NOT_OK)
1914-
&& (urb->transfer_buffer_length -
1915-
urb->actual_length)
1916-
> qh->maxpacket)
1917-
dma->desired_mode = 1;
1918-
if (rx_count < hw_ep->max_packet_sz_rx) {
1919-
length = rx_count;
1920-
dma->desired_mode = 0;
1921-
} else {
1922-
length = urb->transfer_buffer_length;
1923-
}
1924-
#endif
1925-
1926-
/* Disadvantage of using mode 1:
1927-
* It's basically usable only for mass storage class; essentially all
1928-
* other protocols also terminate transfers on short packets.
1929-
*
1930-
* Details:
1931-
* An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1932-
* If you try to use mode 1 for (transfer_buffer_length - 512), and try
1933-
* to use the extra IN token to grab the last packet using mode 0, then
1934-
* the problem is that you cannot be sure when the device will send the
1935-
* last packet and RxPktRdy set. Sometimes the packet is recd too soon
1936-
* such that it gets lost when RxCSR is re-set at the end of the mode 1
1937-
* transfer, while sometimes it is recd just a little late so that if you
1938-
* try to configure for mode 0 soon after the mode 1 transfer is
1939-
* completed, you will find rxcount 0. Okay, so you might think why not
1940-
* wait for an interrupt when the pkt is recd. Well, you won't get any!
1941-
*/
1942-
1943-
val = musb_readw(epio, MUSB_RXCSR);
1944-
val &= ~MUSB_RXCSR_H_REQPKT;
1945-
1946-
if (dma->desired_mode == 0)
1947-
val &= ~MUSB_RXCSR_H_AUTOREQ;
1988+
dev_dbg(hw_ep->musb->controller,
1989+
"RX%d count %d, buffer 0x%llx len %d/%d\n",
1990+
epnum, musb_readw(epio, MUSB_RXCOUNT),
1991+
(unsigned long long) urb->transfer_dma
1992+
+ urb->actual_length,
1993+
qh->offset,
1994+
urb->transfer_buffer_length);
1995+
1996+
done = musb_rx_dma_in_inventra_cppi41(c, hw_ep, qh,
1997+
urb, xfer_len,
1998+
iso_err);
1999+
if (done)
2000+
goto finish;
19482001
else
1949-
val |= MUSB_RXCSR_H_AUTOREQ;
1950-
val |= MUSB_RXCSR_DMAENAB;
1951-
1952-
/* autoclear shouldn't be set in high bandwidth */
1953-
if (qh->hb_mult == 1)
1954-
val |= MUSB_RXCSR_AUTOCLEAR;
1955-
1956-
musb_writew(epio, MUSB_RXCSR,
1957-
MUSB_RXCSR_H_WZC_BITS | val);
1958-
1959-
/* REVISIT if when actual_length != 0,
1960-
* transfer_buffer_length needs to be
1961-
* adjusted first...
1962-
*/
1963-
ret = c->channel_program(
1964-
dma, qh->maxpacket,
1965-
dma->desired_mode, buf, length);
1966-
1967-
if (!ret) {
1968-
c->channel_release(dma);
1969-
hw_ep->rx_channel = NULL;
1970-
dma = NULL;
1971-
val = musb_readw(epio, MUSB_RXCSR);
1972-
val &= ~(MUSB_RXCSR_DMAENAB
1973-
| MUSB_RXCSR_H_AUTOREQ
1974-
| MUSB_RXCSR_AUTOCLEAR);
1975-
musb_writew(epio, MUSB_RXCSR, val);
1976-
}
2002+
dev_err(musb->controller, "error: rx_dma failed\n");
19772003
}
19782004

19792005
if (!dma) {

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