@@ -98,6 +98,49 @@ struct e1000_info;
9898
9999#define DEFAULT_JUMBO 9234
100100
101+ /* BM/HV Specific Registers */
102+ #define BM_PORT_CTRL_PAGE 769
103+
104+ #define PHY_UPPER_SHIFT 21
105+ #define BM_PHY_REG (page , reg ) \
106+ (((reg) & MAX_PHY_REG_ADDRESS) |\
107+ (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\
108+ (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)))
109+
110+ /* PHY Wakeup Registers and defines */
111+ #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
112+ #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
113+ #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
114+ #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
115+ #define BM_RAR_L (_i ) (BM_PHY_REG(BM_WUC_PAGE, 16 + ((_i) << 2)))
116+ #define BM_RAR_M (_i ) (BM_PHY_REG(BM_WUC_PAGE, 17 + ((_i) << 2)))
117+ #define BM_RAR_H (_i ) (BM_PHY_REG(BM_WUC_PAGE, 18 + ((_i) << 2)))
118+ #define BM_RAR_CTRL (_i ) (BM_PHY_REG(BM_WUC_PAGE, 19 + ((_i) << 2)))
119+ #define BM_MTA (_i ) (BM_PHY_REG(BM_WUC_PAGE, 128 + ((_i) << 1)))
120+
121+ #define BM_RCTL_UPE 0x0001 /* Unicast Promiscuous Mode */
122+ #define BM_RCTL_MPE 0x0002 /* Multicast Promiscuous Mode */
123+ #define BM_RCTL_MO_SHIFT 3 /* Multicast Offset Shift */
124+ #define BM_RCTL_MO_MASK (3 << 3) /* Multicast Offset Mask */
125+ #define BM_RCTL_BAM 0x0020 /* Broadcast Accept Mode */
126+ #define BM_RCTL_PMCF 0x0040 /* Pass MAC Control Frames */
127+ #define BM_RCTL_RFCE 0x0080 /* Rx Flow Control Enable */
128+
129+ #define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */
130+ #define HV_SCC_LOWER PHY_REG(778, 17)
131+ #define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */
132+ #define HV_ECOL_LOWER PHY_REG(778, 19)
133+ #define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */
134+ #define HV_MCC_LOWER PHY_REG(778, 21)
135+ #define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */
136+ #define HV_LATECOL_LOWER PHY_REG(778, 24)
137+ #define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */
138+ #define HV_COLC_LOWER PHY_REG(778, 26)
139+ #define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */
140+ #define HV_DC_LOWER PHY_REG(778, 28)
141+ #define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */
142+ #define HV_TNCRS_LOWER PHY_REG(778, 30)
143+
101144enum e1000_boards {
102145 board_82571 ,
103146 board_82572 ,
@@ -108,6 +151,7 @@ enum e1000_boards {
108151 board_ich8lan ,
109152 board_ich9lan ,
110153 board_ich10lan ,
154+ board_pchlan ,
111155};
112156
113157struct e1000_queue_stats {
@@ -305,6 +349,7 @@ struct e1000_adapter {
305349 unsigned int flags2 ;
306350 struct work_struct downshift_task ;
307351 struct work_struct update_phy_task ;
352+ struct work_struct led_blink_task ;
308353};
309354
310355struct e1000_info {
@@ -355,6 +400,7 @@ struct e1000_info {
355400
356401/* CRC Stripping defines */
357402#define FLAG2_CRC_STRIPPING (1 << 0)
403+ #define FLAG2_HAS_PHY_WAKEUP (1 << 1)
358404
359405#define E1000_RX_DESC_PS (R , i ) \
360406 (&(((union e1000_rx_desc_packet_split *)((R).desc))[i]))
@@ -408,6 +454,7 @@ extern struct e1000_info e1000_82583_info;
408454extern struct e1000_info e1000_ich8_info ;
409455extern struct e1000_info e1000_ich9_info ;
410456extern struct e1000_info e1000_ich10_info ;
457+ extern struct e1000_info e1000_pch_info ;
411458extern struct e1000_info e1000_es2_info ;
412459
413460extern s32 e1000e_read_pba_num (struct e1000_hw * hw , u32 * pba_num );
@@ -429,6 +476,7 @@ extern void e1000e_disable_gig_wol_ich8lan(struct e1000_hw *hw);
429476extern s32 e1000e_check_for_copper_link (struct e1000_hw * hw );
430477extern s32 e1000e_check_for_fiber_link (struct e1000_hw * hw );
431478extern s32 e1000e_check_for_serdes_link (struct e1000_hw * hw );
479+ extern s32 e1000e_setup_led_generic (struct e1000_hw * hw );
432480extern s32 e1000e_cleanup_led_generic (struct e1000_hw * hw );
433481extern s32 e1000e_led_on_generic (struct e1000_hw * hw );
434482extern s32 e1000e_led_off_generic (struct e1000_hw * hw );
@@ -497,6 +545,15 @@ extern s32 e1000e_phy_reset_dsp(struct e1000_hw *hw);
497545extern s32 e1000e_read_phy_reg_mdic (struct e1000_hw * hw , u32 offset , u16 * data );
498546extern s32 e1000e_write_phy_reg_mdic (struct e1000_hw * hw , u32 offset , u16 data );
499547extern s32 e1000e_check_downshift (struct e1000_hw * hw );
548+ extern s32 e1000_read_phy_reg_hv (struct e1000_hw * hw , u32 offset , u16 * data );
549+ extern s32 e1000_write_phy_reg_hv (struct e1000_hw * hw , u32 offset , u16 data );
550+ extern s32 e1000_set_mdio_slow_mode_hv (struct e1000_hw * hw , bool slow );
551+ extern s32 e1000_link_stall_workaround_hv (struct e1000_hw * hw );
552+ extern s32 e1000_copper_link_setup_82577 (struct e1000_hw * hw );
553+ extern s32 e1000_check_polarity_82577 (struct e1000_hw * hw );
554+ extern s32 e1000_get_phy_info_82577 (struct e1000_hw * hw );
555+ extern s32 e1000_phy_force_speed_duplex_82577 (struct e1000_hw * hw );
556+ extern s32 e1000_get_cable_length_82577 (struct e1000_hw * hw );
500557
501558static inline s32 e1000_phy_hw_reset (struct e1000_hw * hw )
502559{
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