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Peter UjfalusiPaul Walmsley
Peter Ujfalusi
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Paul Walmsley
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ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8
Add missing data for all McASP ports for the dra7 family Signed-off-by: Peter Ujfalusi <[email protected]> Signed-off-by: Paul Walmsley <[email protected]>
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‎arch/arm/mach-omap2/omap_hwmod_7xx_data.c‎

Lines changed: 237 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1374,6 +1374,52 @@ static struct omap_hwmod_class dra7xx_mcasp_hwmod_class = {
13741374
.sysc = &dra7xx_mcasp_sysc,
13751375
};
13761376

1377+
/* mcasp1 */
1378+
static struct omap_hwmod_opt_clk mcasp1_opt_clks[] = {
1379+
{ .role = "ahclkx", .clk = "mcasp1_ahclkx_mux" },
1380+
{ .role = "ahclkr", .clk = "mcasp1_ahclkr_mux" },
1381+
};
1382+
1383+
static struct omap_hwmod dra7xx_mcasp1_hwmod = {
1384+
.name = "mcasp1",
1385+
.class = &dra7xx_mcasp_hwmod_class,
1386+
.clkdm_name = "ipu_clkdm",
1387+
.main_clk = "mcasp1_aux_gfclk_mux",
1388+
.flags = HWMOD_OPT_CLKS_NEEDED,
1389+
.prcm = {
1390+
.omap4 = {
1391+
.clkctrl_offs = DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET,
1392+
.context_offs = DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET,
1393+
.modulemode = MODULEMODE_SWCTRL,
1394+
},
1395+
},
1396+
.opt_clks = mcasp1_opt_clks,
1397+
.opt_clks_cnt = ARRAY_SIZE(mcasp1_opt_clks),
1398+
};
1399+
1400+
/* mcasp2 */
1401+
static struct omap_hwmod_opt_clk mcasp2_opt_clks[] = {
1402+
{ .role = "ahclkx", .clk = "mcasp2_ahclkx_mux" },
1403+
{ .role = "ahclkr", .clk = "mcasp2_ahclkr_mux" },
1404+
};
1405+
1406+
static struct omap_hwmod dra7xx_mcasp2_hwmod = {
1407+
.name = "mcasp2",
1408+
.class = &dra7xx_mcasp_hwmod_class,
1409+
.clkdm_name = "l4per2_clkdm",
1410+
.main_clk = "mcasp2_aux_gfclk_mux",
1411+
.flags = HWMOD_OPT_CLKS_NEEDED,
1412+
.prcm = {
1413+
.omap4 = {
1414+
.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET,
1415+
.context_offs = DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET,
1416+
.modulemode = MODULEMODE_SWCTRL,
1417+
},
1418+
},
1419+
.opt_clks = mcasp2_opt_clks,
1420+
.opt_clks_cnt = ARRAY_SIZE(mcasp2_opt_clks),
1421+
};
1422+
13771423
/* mcasp3 */
13781424
static struct omap_hwmod_opt_clk mcasp3_opt_clks[] = {
13791425
{ .role = "ahclkx", .clk = "mcasp3_ahclkx_mux" },
@@ -1396,6 +1442,116 @@ static struct omap_hwmod dra7xx_mcasp3_hwmod = {
13961442
.opt_clks_cnt = ARRAY_SIZE(mcasp3_opt_clks),
13971443
};
13981444

1445+
/* mcasp4 */
1446+
static struct omap_hwmod_opt_clk mcasp4_opt_clks[] = {
1447+
{ .role = "ahclkx", .clk = "mcasp4_ahclkx_mux" },
1448+
};
1449+
1450+
static struct omap_hwmod dra7xx_mcasp4_hwmod = {
1451+
.name = "mcasp4",
1452+
.class = &dra7xx_mcasp_hwmod_class,
1453+
.clkdm_name = "l4per2_clkdm",
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.main_clk = "mcasp4_aux_gfclk_mux",
1455+
.flags = HWMOD_OPT_CLKS_NEEDED,
1456+
.prcm = {
1457+
.omap4 = {
1458+
.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET,
1459+
.context_offs = DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET,
1460+
.modulemode = MODULEMODE_SWCTRL,
1461+
},
1462+
},
1463+
.opt_clks = mcasp4_opt_clks,
1464+
.opt_clks_cnt = ARRAY_SIZE(mcasp4_opt_clks),
1465+
};
1466+
1467+
/* mcasp5 */
1468+
static struct omap_hwmod_opt_clk mcasp5_opt_clks[] = {
1469+
{ .role = "ahclkx", .clk = "mcasp5_ahclkx_mux" },
1470+
};
1471+
1472+
static struct omap_hwmod dra7xx_mcasp5_hwmod = {
1473+
.name = "mcasp5",
1474+
.class = &dra7xx_mcasp_hwmod_class,
1475+
.clkdm_name = "l4per2_clkdm",
1476+
.main_clk = "mcasp5_aux_gfclk_mux",
1477+
.flags = HWMOD_OPT_CLKS_NEEDED,
1478+
.prcm = {
1479+
.omap4 = {
1480+
.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET,
1481+
.context_offs = DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET,
1482+
.modulemode = MODULEMODE_SWCTRL,
1483+
},
1484+
},
1485+
.opt_clks = mcasp5_opt_clks,
1486+
.opt_clks_cnt = ARRAY_SIZE(mcasp5_opt_clks),
1487+
};
1488+
1489+
/* mcasp6 */
1490+
static struct omap_hwmod_opt_clk mcasp6_opt_clks[] = {
1491+
{ .role = "ahclkx", .clk = "mcasp6_ahclkx_mux" },
1492+
};
1493+
1494+
static struct omap_hwmod dra7xx_mcasp6_hwmod = {
1495+
.name = "mcasp6",
1496+
.class = &dra7xx_mcasp_hwmod_class,
1497+
.clkdm_name = "l4per2_clkdm",
1498+
.main_clk = "mcasp6_aux_gfclk_mux",
1499+
.flags = HWMOD_OPT_CLKS_NEEDED,
1500+
.prcm = {
1501+
.omap4 = {
1502+
.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET,
1503+
.context_offs = DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET,
1504+
.modulemode = MODULEMODE_SWCTRL,
1505+
},
1506+
},
1507+
.opt_clks = mcasp6_opt_clks,
1508+
.opt_clks_cnt = ARRAY_SIZE(mcasp6_opt_clks),
1509+
};
1510+
1511+
/* mcasp7 */
1512+
static struct omap_hwmod_opt_clk mcasp7_opt_clks[] = {
1513+
{ .role = "ahclkx", .clk = "mcasp7_ahclkx_mux" },
1514+
};
1515+
1516+
static struct omap_hwmod dra7xx_mcasp7_hwmod = {
1517+
.name = "mcasp7",
1518+
.class = &dra7xx_mcasp_hwmod_class,
1519+
.clkdm_name = "l4per2_clkdm",
1520+
.main_clk = "mcasp7_aux_gfclk_mux",
1521+
.flags = HWMOD_OPT_CLKS_NEEDED,
1522+
.prcm = {
1523+
.omap4 = {
1524+
.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET,
1525+
.context_offs = DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET,
1526+
.modulemode = MODULEMODE_SWCTRL,
1527+
},
1528+
},
1529+
.opt_clks = mcasp7_opt_clks,
1530+
.opt_clks_cnt = ARRAY_SIZE(mcasp7_opt_clks),
1531+
};
1532+
1533+
/* mcasp8 */
1534+
static struct omap_hwmod_opt_clk mcasp8_opt_clks[] = {
1535+
{ .role = "ahclkx", .clk = "mcasp8_ahclkx_mux" },
1536+
};
1537+
1538+
static struct omap_hwmod dra7xx_mcasp8_hwmod = {
1539+
.name = "mcasp8",
1540+
.class = &dra7xx_mcasp_hwmod_class,
1541+
.clkdm_name = "l4per2_clkdm",
1542+
.main_clk = "mcasp8_aux_gfclk_mux",
1543+
.flags = HWMOD_OPT_CLKS_NEEDED,
1544+
.prcm = {
1545+
.omap4 = {
1546+
.clkctrl_offs = DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET,
1547+
.context_offs = DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET,
1548+
.modulemode = MODULEMODE_SWCTRL,
1549+
},
1550+
},
1551+
.opt_clks = mcasp8_opt_clks,
1552+
.opt_clks_cnt = ARRAY_SIZE(mcasp8_opt_clks),
1553+
};
1554+
13991555
/*
14001556
* 'mmc' class
14011557
*
@@ -2726,6 +2882,38 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
27262882
.user = OCP_USER_MPU | OCP_USER_SDMA,
27272883
};
27282884

2885+
/* l4_per2 -> mcasp1 */
2886+
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp1 = {
2887+
.master = &dra7xx_l4_per2_hwmod,
2888+
.slave = &dra7xx_mcasp1_hwmod,
2889+
.clk = "l4_root_clk_div",
2890+
.user = OCP_USER_MPU | OCP_USER_SDMA,
2891+
};
2892+
2893+
/* l3_main_1 -> mcasp1 */
2894+
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp1 = {
2895+
.master = &dra7xx_l3_main_1_hwmod,
2896+
.slave = &dra7xx_mcasp1_hwmod,
2897+
.clk = "l3_iclk_div",
2898+
.user = OCP_USER_MPU | OCP_USER_SDMA,
2899+
};
2900+
2901+
/* l4_per2 -> mcasp2 */
2902+
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp2 = {
2903+
.master = &dra7xx_l4_per2_hwmod,
2904+
.slave = &dra7xx_mcasp2_hwmod,
2905+
.clk = "l4_root_clk_div",
2906+
.user = OCP_USER_MPU | OCP_USER_SDMA,
2907+
};
2908+
2909+
/* l3_main_1 -> mcasp2 */
2910+
static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp2 = {
2911+
.master = &dra7xx_l3_main_1_hwmod,
2912+
.slave = &dra7xx_mcasp2_hwmod,
2913+
.clk = "l3_iclk_div",
2914+
.user = OCP_USER_MPU | OCP_USER_SDMA,
2915+
};
2916+
27292917
/* l4_per2 -> mcasp3 */
27302918
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp3 = {
27312919
.master = &dra7xx_l4_per2_hwmod,
@@ -2742,6 +2930,46 @@ static struct omap_hwmod_ocp_if dra7xx_l3_main_1__mcasp3 = {
27422930
.user = OCP_USER_MPU | OCP_USER_SDMA,
27432931
};
27442932

2933+
/* l4_per2 -> mcasp4 */
2934+
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp4 = {
2935+
.master = &dra7xx_l4_per2_hwmod,
2936+
.slave = &dra7xx_mcasp4_hwmod,
2937+
.clk = "l4_root_clk_div",
2938+
.user = OCP_USER_MPU | OCP_USER_SDMA,
2939+
};
2940+
2941+
/* l4_per2 -> mcasp5 */
2942+
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp5 = {
2943+
.master = &dra7xx_l4_per2_hwmod,
2944+
.slave = &dra7xx_mcasp5_hwmod,
2945+
.clk = "l4_root_clk_div",
2946+
.user = OCP_USER_MPU | OCP_USER_SDMA,
2947+
};
2948+
2949+
/* l4_per2 -> mcasp6 */
2950+
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp6 = {
2951+
.master = &dra7xx_l4_per2_hwmod,
2952+
.slave = &dra7xx_mcasp6_hwmod,
2953+
.clk = "l4_root_clk_div",
2954+
.user = OCP_USER_MPU | OCP_USER_SDMA,
2955+
};
2956+
2957+
/* l4_per2 -> mcasp7 */
2958+
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp7 = {
2959+
.master = &dra7xx_l4_per2_hwmod,
2960+
.slave = &dra7xx_mcasp7_hwmod,
2961+
.clk = "l4_root_clk_div",
2962+
.user = OCP_USER_MPU | OCP_USER_SDMA,
2963+
};
2964+
2965+
/* l4_per2 -> mcasp8 */
2966+
static struct omap_hwmod_ocp_if dra7xx_l4_per2__mcasp8 = {
2967+
.master = &dra7xx_l4_per2_hwmod,
2968+
.slave = &dra7xx_mcasp8_hwmod,
2969+
.clk = "l4_root_clk_div",
2970+
.user = OCP_USER_MPU | OCP_USER_SDMA,
2971+
};
2972+
27452973
/* l4_per1 -> elm */
27462974
static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
27472975
.master = &dra7xx_l4_per1_hwmod,
@@ -3484,8 +3712,17 @@ static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
34843712
&dra7xx_l4_wkup__dcan1,
34853713
&dra7xx_l4_per2__dcan2,
34863714
&dra7xx_l4_per2__cpgmac0,
3715+
&dra7xx_l4_per2__mcasp1,
3716+
&dra7xx_l3_main_1__mcasp1,
3717+
&dra7xx_l4_per2__mcasp2,
3718+
&dra7xx_l3_main_1__mcasp2,
34873719
&dra7xx_l4_per2__mcasp3,
34883720
&dra7xx_l3_main_1__mcasp3,
3721+
&dra7xx_l4_per2__mcasp4,
3722+
&dra7xx_l4_per2__mcasp5,
3723+
&dra7xx_l4_per2__mcasp6,
3724+
&dra7xx_l4_per2__mcasp7,
3725+
&dra7xx_l4_per2__mcasp8,
34893726
&dra7xx_gmac__mdio,
34903727
&dra7xx_l4_cfg__dma_system,
34913728
&dra7xx_l3_main_1__tpcc,

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