|
67 | 67 | #endif |
68 | 68 | .endm |
69 | 69 |
|
70 | | - .macro uaccess_save, tmp |
71 | 70 | #ifdef CONFIG_CPU_SW_DOMAIN_PAN |
72 | | - mrc p15, 0, \tmp, c3, c0, 0 |
73 | | - str \tmp, [sp, #SVC_DACR] |
74 | | -#endif |
75 | | - .endm |
76 | | - |
77 | | - .macro uaccess_restore |
78 | | -#ifdef CONFIG_CPU_SW_DOMAIN_PAN |
79 | | - ldr r0, [sp, #SVC_DACR] |
80 | | - mcr p15, 0, r0, c3, c0, 0 |
| 71 | +#define DACR(x...) x |
| 72 | +#else |
| 73 | +#define DACR(x...) |
81 | 74 | #endif |
82 | | - .endm |
83 | 75 |
|
84 | 76 | /* |
85 | 77 | * Save the address limit on entry to a privileged exception and |
86 | 78 | * if using PAN, save and disable usermode access. |
87 | 79 | */ |
88 | 80 | .macro uaccess_entry, tsk, tmp0, tmp1, tmp2, disable |
89 | | - ldr \tmp0, [\tsk, #TI_ADDR_LIMIT] |
90 | | - mov \tmp1, #TASK_SIZE |
91 | | - str \tmp1, [\tsk, #TI_ADDR_LIMIT] |
92 | | - str \tmp0, [sp, #SVC_ADDR_LIMIT] |
93 | | - uaccess_save \tmp0 |
| 81 | + ldr \tmp1, [\tsk, #TI_ADDR_LIMIT] |
| 82 | + mov \tmp2, #TASK_SIZE |
| 83 | + str \tmp2, [\tsk, #TI_ADDR_LIMIT] |
| 84 | + DACR( mrc p15, 0, \tmp0, c3, c0, 0) |
| 85 | + DACR( str \tmp0, [sp, #SVC_DACR]) |
| 86 | + str \tmp1, [sp, #SVC_ADDR_LIMIT] |
94 | 87 | .if \disable |
95 | 88 | uaccess_disable \tmp0 |
96 | 89 | .endif |
|
99 | 92 | /* Restore the user access state previously saved by uaccess_entry */ |
100 | 93 | .macro uaccess_exit, tsk, tmp0, tmp1 |
101 | 94 | ldr \tmp1, [sp, #SVC_ADDR_LIMIT] |
102 | | - uaccess_restore |
| 95 | + DACR( ldr \tmp0, [sp, #SVC_DACR]) |
103 | 96 | str \tmp1, [\tsk, #TI_ADDR_LIMIT] |
| 97 | + DACR( mcr p15, 0, \tmp0, c3, c0, 0) |
104 | 98 | .endm |
105 | 99 |
|
| 100 | +#undef DACR |
| 101 | + |
106 | 102 | #endif /* __ASM_UACCESS_ASM_H__ */ |
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