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1 | 1 | * Qualcomm Atheros ath10k wireless devices |
2 | 2 |
|
3 | | -For ath10k devices the calibration data can be provided through Device |
4 | | -Tree. The node is a child node of the PCI controller. |
5 | | - |
6 | 3 | Required properties: |
7 | | --compatible : Should be "qcom,ath10k" |
| 4 | +- compatible: Should be one of the following: |
| 5 | + * "qcom,ath10k" |
| 6 | + * "qcom,ipq4019-wifi" |
| 7 | + |
| 8 | +PCI based devices uses compatible string "qcom,ath10k" and takes only |
| 9 | +calibration data via "qcom,ath10k-calibration-data". Rest of the properties |
| 10 | +are not applicable for PCI based devices. |
| 11 | + |
| 12 | +AHB based devices (i.e. ipq4019) uses compatible string "qcom,ipq4019-wifi" |
| 13 | +and also uses most of the properties defined in this doc. |
8 | 14 |
|
9 | 15 | Optional properties: |
| 16 | +- reg: Address and length of the register set for the device. |
| 17 | +- resets: Must contain an entry for each entry in reset-names. |
| 18 | + See ../reset/reseti.txt for details. |
| 19 | +- reset-names: Must include the list of following reset names, |
| 20 | + "wifi_cpu_init" |
| 21 | + "wifi_radio_srif" |
| 22 | + "wifi_radio_warm" |
| 23 | + "wifi_radio_cold" |
| 24 | + "wifi_core_warm" |
| 25 | + "wifi_core_cold" |
| 26 | +- clocks: List of clock specifiers, must contain an entry for each required |
| 27 | + entry in clock-names. |
| 28 | +- clock-names: Should contain the clock names "wifi_wcss_cmd", "wifi_wcss_ref", |
| 29 | + "wifi_wcss_rtc". |
| 30 | +- interrupts: List of interrupt lines. Must contain an entry |
| 31 | + for each entry in the interrupt-names property. |
| 32 | +- interrupt-names: Must include the entries for MSI interrupt |
| 33 | + names ("msi0" to "msi15") and legacy interrupt |
| 34 | + name ("legacy"), |
| 35 | +- qcom,msi_addr: MSI interrupt address. |
| 36 | +- qcom,msi_base: Base value to add before writing MSI data into |
| 37 | + MSI address register. |
10 | 38 | - qcom,ath10k-calibration-data : calibration data as an array, the |
11 | 39 | length can vary between hw versions |
12 | 40 |
|
| 41 | +Example (to supply the calibration data alone): |
13 | 42 |
|
14 | | -Example: |
| 43 | +In this example, the node is defined as child node of the PCI controller. |
15 | 44 |
|
16 | 45 | pci { |
17 | 46 | pcie@0 { |
|
28 | 57 | }; |
29 | 58 | }; |
30 | 59 | }; |
| 60 | + |
| 61 | +Example (to supply ipq4019 SoC wifi block details): |
| 62 | + |
| 63 | +wifi0: wifi@a000000 { |
| 64 | + compatible = "qcom,ipq4019-wifi"; |
| 65 | + reg = <0xa000000 0x200000>; |
| 66 | + resets = <&gcc WIFI0_CPU_INIT_RESET>, |
| 67 | + <&gcc WIFI0_RADIO_SRIF_RESET>, |
| 68 | + <&gcc WIFI0_RADIO_WARM_RESET>, |
| 69 | + <&gcc WIFI0_RADIO_COLD_RESET>, |
| 70 | + <&gcc WIFI0_CORE_WARM_RESET>, |
| 71 | + <&gcc WIFI0_CORE_COLD_RESET>; |
| 72 | + reset-names = "wifi_cpu_init", |
| 73 | + "wifi_radio_srif", |
| 74 | + "wifi_radio_warm", |
| 75 | + "wifi_radio_cold", |
| 76 | + "wifi_core_warm", |
| 77 | + "wifi_core_cold"; |
| 78 | + clocks = <&gcc GCC_WCSS2G_CLK>, |
| 79 | + <&gcc GCC_WCSS2G_REF_CLK>, |
| 80 | + <&gcc GCC_WCSS2G_RTC_CLK>; |
| 81 | + clock-names = "wifi_wcss_cmd", |
| 82 | + "wifi_wcss_ref", |
| 83 | + "wifi_wcss_rtc"; |
| 84 | + interrupts = <0 0x20 0x1>, |
| 85 | + <0 0x21 0x1>, |
| 86 | + <0 0x22 0x1>, |
| 87 | + <0 0x23 0x1>, |
| 88 | + <0 0x24 0x1>, |
| 89 | + <0 0x25 0x1>, |
| 90 | + <0 0x26 0x1>, |
| 91 | + <0 0x27 0x1>, |
| 92 | + <0 0x28 0x1>, |
| 93 | + <0 0x29 0x1>, |
| 94 | + <0 0x2a 0x1>, |
| 95 | + <0 0x2b 0x1>, |
| 96 | + <0 0x2c 0x1>, |
| 97 | + <0 0x2d 0x1>, |
| 98 | + <0 0x2e 0x1>, |
| 99 | + <0 0x2f 0x1>, |
| 100 | + <0 0xa8 0x0>; |
| 101 | + interrupt-names = "msi0", "msi1", "msi2", "msi3", |
| 102 | + "msi4", "msi5", "msi6", "msi7", |
| 103 | + "msi8", "msi9", "msi10", "msi11", |
| 104 | + "msi12", "msi13", "msi14", "msi15", |
| 105 | + "legacy"; |
| 106 | + qcom,msi_addr = <0x0b006040>; |
| 107 | + qcom,msi_base = <0x40>; |
| 108 | + qcom,ath10k-calibration-data = [ 01 02 03 ... ]; |
| 109 | +}; |
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