@@ -644,7 +644,7 @@ static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
644644 pci_read_config_word (pm8001_ha -> pdev , PCI_DEVICE_ID , & deviceid );
645645 /* 8081 controllers need BAR shift to access MPI space
646646 * as this is shared with BIOS data */
647- if (deviceid == 0x8081 ) {
647+ if (deviceid == 0x8081 || deviceid == 0x0042 ) {
648648 if (-1 == pm8001_bar4_shift (pm8001_ha , GSM_SM_BASE )) {
649649 PM8001_FAIL_DBG (pm8001_ha ,
650650 pm8001_printk ("Shift Bar4 to 0x%x failed\n" ,
@@ -673,7 +673,7 @@ static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
673673 for (i = 0 ; i < PM8001_MAX_OUTB_NUM ; i ++ )
674674 update_outbnd_queue_table (pm8001_ha , i );
675675 /* 8081 controller donot require these operations */
676- if (deviceid != 0x8081 ) {
676+ if (deviceid != 0x8081 && deviceid != 0x0042 ) {
677677 mpi_set_phys_g3_with_ssc (pm8001_ha , 0 );
678678 /* 7->130ms, 34->500ms, 119->1.5s */
679679 mpi_set_open_retry_interval_reg (pm8001_ha , 119 );
@@ -701,7 +701,7 @@ static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
701701 u32 gst_len_mpistate ;
702702 u16 deviceid ;
703703 pci_read_config_word (pm8001_ha -> pdev , PCI_DEVICE_ID , & deviceid );
704- if (deviceid == 0x8081 ) {
704+ if (deviceid == 0x8081 || deviceid == 0x0042 ) {
705705 if (-1 == pm8001_bar4_shift (pm8001_ha , GSM_SM_BASE )) {
706706 PM8001_FAIL_DBG (pm8001_ha ,
707707 pm8001_printk ("Shift Bar4 to 0x%x failed\n" ,
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