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41 | 41 | #define JZ_REG_MMC_RESP_FIFO 0x34 |
42 | 42 | #define JZ_REG_MMC_RXFIFO 0x38 |
43 | 43 | #define JZ_REG_MMC_TXFIFO 0x3C |
| 44 | +#define JZ_REG_MMC_LPM 0x40 |
44 | 45 | #define JZ_REG_MMC_DMAC 0x44 |
45 | 46 |
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46 | 47 | #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7) |
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100 | 101 | #define JZ_MMC_DMAC_DMA_SEL BIT(1) |
101 | 102 | #define JZ_MMC_DMAC_DMA_EN BIT(0) |
102 | 103 |
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| 104 | +#define JZ_MMC_LPM_DRV_RISING BIT(31) |
| 105 | +#define JZ_MMC_LPM_DRV_RISING_QTR_PHASE_DLY BIT(31) |
| 106 | +#define JZ_MMC_LPM_DRV_RISING_1NS_DLY BIT(30) |
| 107 | +#define JZ_MMC_LPM_SMP_RISING_QTR_OR_HALF_PHASE_DLY BIT(29) |
| 108 | +#define JZ_MMC_LPM_LOW_POWER_MODE_EN BIT(0) |
| 109 | + |
103 | 110 | #define JZ_MMC_CLK_RATE 24000000 |
104 | 111 |
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105 | 112 | enum jz4740_mmc_version { |
@@ -856,6 +863,22 @@ static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) |
856 | 863 | } |
857 | 864 |
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858 | 865 | writew(div, host->base + JZ_REG_MMC_CLKRT); |
| 866 | + |
| 867 | + if (real_rate > 25000000) { |
| 868 | + if (host->version >= JZ_MMC_X1000) { |
| 869 | + writel(JZ_MMC_LPM_DRV_RISING_QTR_PHASE_DLY | |
| 870 | + JZ_MMC_LPM_SMP_RISING_QTR_OR_HALF_PHASE_DLY | |
| 871 | + JZ_MMC_LPM_LOW_POWER_MODE_EN, |
| 872 | + host->base + JZ_REG_MMC_LPM); |
| 873 | + } else if (host->version >= JZ_MMC_JZ4760) { |
| 874 | + writel(JZ_MMC_LPM_DRV_RISING | |
| 875 | + JZ_MMC_LPM_LOW_POWER_MODE_EN, |
| 876 | + host->base + JZ_REG_MMC_LPM); |
| 877 | + } else if (host->version >= JZ_MMC_JZ4725B) |
| 878 | + writel(JZ_MMC_LPM_LOW_POWER_MODE_EN, |
| 879 | + host->base + JZ_REG_MMC_LPM); |
| 880 | + } |
| 881 | + |
859 | 882 | return real_rate; |
860 | 883 | } |
861 | 884 |
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