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Saeed Mahameeddavem330
Saeed Mahameed
authored and
davem330
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net/mlx5: Update mlx5_ifc hardware features
Adding the needed mlx5_ifc hardware bits and structs for the following feature: * Add vport to steering commands for SRIOV ACL support * Add mlcr, pcmr and mcia registers for dump module EEPROM * Add support for FCS, baeacon led and disable_link bits to hca caps * Add CQE period mode bit in CQ context for CQE based CQ moderation support * Add umr SQ bit for fragmented memory registration * Add needed bits and caps for Striding RQ support Signed-off-by: Saeed Mahameed <[email protected]> Signed-off-by: Matan Barak <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎include/linux/mlx5/mlx5_ifc.h‎

Lines changed: 124 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -513,7 +513,9 @@ struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
513513
u8 max_lso_cap[0x5];
514514
u8 reserved_at_10[0x4];
515515
u8 rss_ind_tbl_cap[0x4];
516-
u8 reserved_at_18[0x3];
516+
u8 reg_umr_sq[0x1];
517+
u8 scatter_fcs[0x1];
518+
u8 reserved_at_1a[0x1];
517519
u8 tunnel_lso_const_out_ip_id[0x1];
518520
u8 reserved_at_1c[0x2];
519521
u8 tunnel_statless_gre[0x1];
@@ -648,7 +650,7 @@ struct mlx5_ifc_vector_calc_cap_bits {
648650
enum {
649651
MLX5_WQ_TYPE_LINKED_LIST = 0x0,
650652
MLX5_WQ_TYPE_CYCLIC = 0x1,
651-
MLX5_WQ_TYPE_STRQ = 0x2,
653+
MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
652654
};
653655

654656
enum {
@@ -753,7 +755,11 @@ struct mlx5_ifc_cmd_hca_cap_bits {
753755
u8 early_vf_enable[0x1];
754756
u8 reserved_at_1a9[0x2];
755757
u8 local_ca_ack_delay[0x5];
756-
u8 reserved_at_1af[0x6];
758+
u8 reserved_at_1af[0x2];
759+
u8 ports_check[0x1];
760+
u8 reserved_at_1b2[0x1];
761+
u8 disable_link_up[0x1];
762+
u8 beacon_led[0x1];
757763
u8 port_type[0x2];
758764
u8 num_ports[0x8];
759765

@@ -778,7 +784,8 @@ struct mlx5_ifc_cmd_hca_cap_bits {
778784
u8 cqe_version[0x4];
779785

780786
u8 compact_address_vector[0x1];
781-
u8 reserved_at_200[0x3];
787+
u8 striding_rq[0x1];
788+
u8 reserved_at_201[0x2];
782789
u8 ipoib_basic_offloads[0x1];
783790
u8 reserved_at_205[0xa];
784791
u8 drain_sigerr[0x1];
@@ -807,12 +814,12 @@ struct mlx5_ifc_cmd_hca_cap_bits {
807814
u8 block_lb_mc[0x1];
808815
u8 reserved_at_229[0x1];
809816
u8 scqe_break_moderation[0x1];
810-
u8 reserved_at_22a[0x1];
817+
u8 cq_period_start_from_cqe[0x1];
811818
u8 cd[0x1];
812819
u8 reserved_at_22d[0x1];
813820
u8 apm[0x1];
814821
u8 vector_calc[0x1];
815-
u8 reserved_at_22f[0x1];
822+
u8 umr_ptr_rlky[0x1];
816823
u8 imaicl[0x1];
817824
u8 reserved_at_232[0x4];
818825
u8 qkv[0x1];
@@ -913,10 +920,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {
913920
u8 reserved_at_500[0x80];
914921

915922
u8 reserved_at_580[0x3f];
916-
u8 cqe_zip[0x1];
923+
u8 cqe_compression[0x1];
917924

918-
u8 cqe_zip_timeout[0x10];
919-
u8 cqe_zip_max_num[0x10];
925+
u8 cqe_compression_timeout[0x10];
926+
u8 cqe_compression_max_num[0x10];
920927

921928
u8 reserved_at_5e0[0x220];
922929
};
@@ -1000,7 +1007,13 @@ struct mlx5_ifc_wq_bits {
10001007
u8 reserved_at_118[0x3];
10011008
u8 log_wq_sz[0x5];
10021009

1003-
u8 reserved_at_120[0x4e0];
1010+
u8 reserved_at_120[0x15];
1011+
u8 log_wqe_num_of_strides[0x3];
1012+
u8 two_byte_shift_en[0x1];
1013+
u8 reserved_at_139[0x4];
1014+
u8 log_wqe_stride_size[0x3];
1015+
1016+
u8 reserved_at_140[0x4c0];
10041017

10051018
struct mlx5_ifc_cmd_pas_bits pas[0];
10061019
};
@@ -2199,7 +2212,8 @@ struct mlx5_ifc_sqc_bits {
21992212
u8 flush_in_error_en[0x1];
22002213
u8 reserved_at_4[0x4];
22012214
u8 state[0x4];
2202-
u8 reserved_at_c[0x14];
2215+
u8 reg_umr[0x1];
2216+
u8 reserved_at_d[0x13];
22032217

22042218
u8 reserved_at_20[0x8];
22052219
u8 user_index[0x18];
@@ -2247,7 +2261,8 @@ enum {
22472261

22482262
struct mlx5_ifc_rqc_bits {
22492263
u8 rlky[0x1];
2250-
u8 reserved_at_1[0x2];
2264+
u8 reserved_at_1[0x1];
2265+
u8 scatter_fcs[0x1];
22512266
u8 vsd[0x1];
22522267
u8 mem_rq_type[0x4];
22532268
u8 state[0x4];
@@ -2604,6 +2619,11 @@ enum {
26042619
MLX5_CQC_ST_FIRED = 0xa,
26052620
};
26062621

2622+
enum {
2623+
MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2624+
MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2625+
};
2626+
26072627
struct mlx5_ifc_cqc_bits {
26082628
u8 status[0x4];
26092629
u8 reserved_at_4[0x4];
@@ -2612,8 +2632,8 @@ struct mlx5_ifc_cqc_bits {
26122632
u8 reserved_at_c[0x1];
26132633
u8 scqe_break_moderation_en[0x1];
26142634
u8 oi[0x1];
2615-
u8 reserved_at_f[0x2];
2616-
u8 cqe_zip_en[0x1];
2635+
u8 cq_period_mode[0x2];
2636+
u8 cqe_comp_en[0x1];
26172637
u8 mini_cqe_res_format[0x2];
26182638
u8 st[0x4];
26192639
u8 reserved_at_18[0x8];
@@ -2987,7 +3007,11 @@ struct mlx5_ifc_set_fte_in_bits {
29873007
u8 reserved_at_20[0x10];
29883008
u8 op_mod[0x10];
29893009

2990-
u8 reserved_at_40[0x40];
3010+
u8 other_vport[0x1];
3011+
u8 reserved_at_41[0xf];
3012+
u8 vport_number[0x10];
3013+
3014+
u8 reserved_at_60[0x20];
29913015

29923016
u8 table_type[0x8];
29933017
u8 reserved_at_88[0x18];
@@ -5181,7 +5205,11 @@ struct mlx5_ifc_destroy_flow_table_in_bits {
51815205
u8 reserved_at_20[0x10];
51825206
u8 op_mod[0x10];
51835207

5184-
u8 reserved_at_40[0x40];
5208+
u8 other_vport[0x1];
5209+
u8 reserved_at_41[0xf];
5210+
u8 vport_number[0x10];
5211+
5212+
u8 reserved_at_60[0x20];
51855213

51865214
u8 table_type[0x8];
51875215
u8 reserved_at_88[0x18];
@@ -5208,7 +5236,11 @@ struct mlx5_ifc_destroy_flow_group_in_bits {
52085236
u8 reserved_at_20[0x10];
52095237
u8 op_mod[0x10];
52105238

5211-
u8 reserved_at_40[0x40];
5239+
u8 other_vport[0x1];
5240+
u8 reserved_at_41[0xf];
5241+
u8 vport_number[0x10];
5242+
5243+
u8 reserved_at_60[0x20];
52125244

52135245
u8 table_type[0x8];
52145246
u8 reserved_at_88[0x18];
@@ -5349,7 +5381,11 @@ struct mlx5_ifc_delete_fte_in_bits {
53495381
u8 reserved_at_20[0x10];
53505382
u8 op_mod[0x10];
53515383

5352-
u8 reserved_at_40[0x40];
5384+
u8 other_vport[0x1];
5385+
u8 reserved_at_41[0xf];
5386+
u8 vport_number[0x10];
5387+
5388+
u8 reserved_at_60[0x20];
53535389

53545390
u8 table_type[0x8];
53555391
u8 reserved_at_88[0x18];
@@ -5795,7 +5831,11 @@ struct mlx5_ifc_create_flow_table_in_bits {
57955831
u8 reserved_at_20[0x10];
57965832
u8 op_mod[0x10];
57975833

5798-
u8 reserved_at_40[0x40];
5834+
u8 other_vport[0x1];
5835+
u8 reserved_at_41[0xf];
5836+
u8 vport_number[0x10];
5837+
5838+
u8 reserved_at_60[0x20];
57995839

58005840
u8 table_type[0x8];
58015841
u8 reserved_at_88[0x18];
@@ -5839,7 +5879,11 @@ struct mlx5_ifc_create_flow_group_in_bits {
58395879
u8 reserved_at_20[0x10];
58405880
u8 op_mod[0x10];
58415881

5842-
u8 reserved_at_40[0x40];
5882+
u8 other_vport[0x1];
5883+
u8 reserved_at_41[0xf];
5884+
u8 vport_number[0x10];
5885+
5886+
u8 reserved_at_60[0x20];
58435887

58445888
u8 table_type[0x8];
58455889
u8 reserved_at_88[0x18];
@@ -6372,6 +6416,17 @@ struct mlx5_ifc_ptys_reg_bits {
63726416
u8 reserved_at_1a0[0x60];
63736417
};
63746418

6419+
struct mlx5_ifc_mlcr_reg_bits {
6420+
u8 reserved_at_0[0x8];
6421+
u8 local_port[0x8];
6422+
u8 reserved_at_10[0x20];
6423+
6424+
u8 beacon_duration[0x10];
6425+
u8 reserved_at_40[0x10];
6426+
6427+
u8 beacon_remain[0x10];
6428+
};
6429+
63756430
struct mlx5_ifc_ptas_reg_bits {
63766431
u8 reserved_at_0[0x20];
63776432

@@ -6781,6 +6836,16 @@ struct mlx5_ifc_pamp_reg_bits {
67816836
u8 index_data[18][0x10];
67826837
};
67836838

6839+
struct mlx5_ifc_pcmr_reg_bits {
6840+
u8 reserved_at_0[0x8];
6841+
u8 local_port[0x8];
6842+
u8 reserved_at_10[0x2e];
6843+
u8 fcs_cap[0x1];
6844+
u8 reserved_at_3f[0x1f];
6845+
u8 fcs_chk[0x1];
6846+
u8 reserved_at_5f[0x1];
6847+
};
6848+
67846849
struct mlx5_ifc_lane_2_module_mapping_bits {
67856850
u8 reserved_at_0[0x6];
67866851
u8 rx_lane[0x2];
@@ -7117,6 +7182,7 @@ union mlx5_ifc_ports_control_registers_document_bits {
71177182
struct mlx5_ifc_pspa_reg_bits pspa_reg;
71187183
struct mlx5_ifc_ptas_reg_bits ptas_reg;
71197184
struct mlx5_ifc_ptys_reg_bits ptys_reg;
7185+
struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
71207186
struct mlx5_ifc_pude_reg_bits pude_reg;
71217187
struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
71227188
struct mlx5_ifc_slrg_reg_bits slrg_reg;
@@ -7150,7 +7216,11 @@ struct mlx5_ifc_set_flow_table_root_in_bits {
71507216
u8 reserved_at_20[0x10];
71517217
u8 op_mod[0x10];
71527218

7153-
u8 reserved_at_40[0x40];
7219+
u8 other_vport[0x1];
7220+
u8 reserved_at_41[0xf];
7221+
u8 vport_number[0x10];
7222+
7223+
u8 reserved_at_60[0x20];
71547224

71557225
u8 table_type[0x8];
71567226
u8 reserved_at_88[0x18];
@@ -7181,7 +7251,9 @@ struct mlx5_ifc_modify_flow_table_in_bits {
71817251
u8 reserved_at_20[0x10];
71827252
u8 op_mod[0x10];
71837253

7184-
u8 reserved_at_40[0x20];
7254+
u8 other_vport[0x1];
7255+
u8 reserved_at_41[0xf];
7256+
u8 vport_number[0x10];
71857257

71867258
u8 reserved_at_60[0x10];
71877259
u8 modify_field_select[0x10];
@@ -7247,4 +7319,34 @@ struct mlx5_ifc_qtct_reg_bits {
72477319
u8 tclass[0x3];
72487320
};
72497321

7322+
struct mlx5_ifc_mcia_reg_bits {
7323+
u8 l[0x1];
7324+
u8 reserved_at_1[0x7];
7325+
u8 module[0x8];
7326+
u8 reserved_at_10[0x8];
7327+
u8 status[0x8];
7328+
7329+
u8 i2c_device_address[0x8];
7330+
u8 page_number[0x8];
7331+
u8 device_address[0x10];
7332+
7333+
u8 reserved_at_40[0x10];
7334+
u8 size[0x10];
7335+
7336+
u8 reserved_at_60[0x20];
7337+
7338+
u8 dword_0[0x20];
7339+
u8 dword_1[0x20];
7340+
u8 dword_2[0x20];
7341+
u8 dword_3[0x20];
7342+
u8 dword_4[0x20];
7343+
u8 dword_5[0x20];
7344+
u8 dword_6[0x20];
7345+
u8 dword_7[0x20];
7346+
u8 dword_8[0x20];
7347+
u8 dword_9[0x20];
7348+
u8 dword_10[0x20];
7349+
u8 dword_11[0x20];
7350+
};
7351+
72507352
#endif /* MLX5_IFC_H */

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