FogBugz #178793: Upgrade socfpga to v3.13

spi-dw-mmio: commit[1e0d191] removes free_irq
socfpga: commit[dc81058] removes of_clk_init
fpga-mgr & fgpa-bridge:
	* INIT_COMPLETION -> reinit_completion
	* use dev_groups for adding attributes to class
spi-cadence-qspi.c - add code to set maxburst to 1 for qspi, so that burst
patch will work properly.
socfpga_cyclone5.dtsi: s/snps,max-mtu/max-frame-size

Signed-off-by: Graham Moore <[email protected]>
Signed-off-by: Alan Tull <[email protected]>
Signed-off-by: Dinh Nguyen <[email protected]>

Author: Dinh Nguyen

arch/arm/boot/dts/socfpga_cyclone5.dtsi

@@ -185,6 +185,6 @@
 	txc-skew-ps = <2600>;
 	rxdv-skew-ps = <0>;
 	rxc-skew-ps = <2000>;
-	snps,max-mtu = <3800>;
+	max-frame-size = <3800>;
 	status = "okay";
 };

arch/arm/mach-socfpga/socfpga.c

@@ -275,8 +275,6 @@ static void __init socfpga_init_irq(void)
 {
 	irqchip_init();
 	socfpga_sysmgr_init();
-
-	of_clk_init(NULL);
 }
 
 static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)

drivers/fpga/fpga-mgr.c

@@ -57,10 +57,22 @@ static ssize_t fpga_mgr_status_show(struct device *dev,
 	return mgr->mops->status(mgr, buf);
 }
 
-static struct device_attribute fpga_mgr_attrs[] = {
-	__ATTR(name, S_IRUGO, fpga_mgr_name_show, NULL),
-	__ATTR(status, S_IRUGO, fpga_mgr_status_show, NULL),
-	__ATTR_NULL
+static DEVICE_ATTR(name, S_IRUGO, fpga_mgr_name_show, NULL);
+static DEVICE_ATTR(status, S_IRUGO, fpga_mgr_status_show, NULL);
+
+static struct attribute *fpga_mgr_attrs[] = {
+	&dev_attr_name.attr,
+	&dev_attr_status.attr,
+	NULL,
+};
+
+static const struct attribute_group fpga_mgr_group = {
+	.attrs = fpga_mgr_attrs,
+};
+
+const struct attribute_group *fpga_mgr_groups[] = {
+	&fpga_mgr_group,
+	NULL,
 };
 
 static int fpga_mgr_get_new_minor(struct fpga_manager *mgr, int request_nr)
@@ -219,7 +231,7 @@ static int __init fpga_mgr_dev_init(void)
 	if (IS_ERR(fpga_mgr_class))
 		return PTR_ERR(fpga_mgr_class);
 
-	fpga_mgr_class->dev_attrs = fpga_mgr_attrs;
+	fpga_mgr_class->dev_groups = fpga_mgr_groups;
 
 	ret = alloc_chrdev_region(&fpga_mgr_dev, 0, FPGA_MAX_MINORS, "fpga");
 	if (ret) {

drivers/fpga/fpga-mgrs/altera.c

@@ -259,7 +259,7 @@ static int alt_fpga_wait_for_config_done(struct fpga_manager *mgr)
 	int timeout, ret = 0;
 
 	alt_fpga_disable_irqs(mgr);
-	INIT_COMPLETION(mgr->status_complete);
+	reinit_completion(&mgr->status_complete);
 	alt_fpga_enable_irqs(mgr, ALT_FPGAMGR_MON_CONF_DONE);
 
 	timeout = wait_for_completion_interruptible_timeout(

drivers/misc/fpga-bridge/fpga-bridge.c

@@ -65,9 +65,21 @@ static ssize_t fpga_bridge_enable_set(struct device *dev,
 	return count;
 }
 
-static struct device_attribute fpga_bridge_attrs[] = {
-	__ATTR(enable, S_IRUGO | S_IWUSR, fpga_bridge_enable_show, fpga_bridge_enable_set),
-	__ATTR_NULL
+static DEVICE_ATTR(enable, S_IRUGO | S_IWUSR, fpga_bridge_enable_show,
+	       fpga_bridge_enable_set);
+
+static struct attribute *fpga_bridge_attrs[] = {
+	&dev_attr_enable.attr,
+	NULL,
+};
+
+static const struct attribute_group fpga_bridge_group = {
+	.attrs = fpga_bridge_attrs,
+};
+
+const struct attribute_group *fpga_bridge_groups[] = {
+	&fpga_bridge_group,
+	NULL,
 };
 
 static int fpga_bridge_alloc_id(struct fpga_bridge *bridge, int request_nr)
@@ -198,7 +210,7 @@ static int __init fpga_bridge_dev_init(void)
 	if (IS_ERR(fpga_bridge_class))
 		return PTR_ERR(fpga_bridge_class);
 
-	fpga_bridge_class->dev_attrs = fpga_bridge_attrs;
+	fpga_bridge_class->dev_groups = fpga_bridge_groups;
 
 	return 0;
 }

drivers/spi/spi-cadence-qspi-apb.c

@@ -442,12 +442,14 @@ static int cadence_qspi_apb_dma_start(
 		dmaconf.direction = DMA_DEV_TO_MEM;
 		dmaconf.src_addr = pdata->qspi_ahb_phy;
 		dmaconf.src_addr_width = 4;
+		dmaconf.src_maxburst = 1;
 	} else {
 		dmachan = cadence_qspi->txchan;
 		data_direction = DMA_TO_DEVICE;
 		dmaconf.direction = DMA_MEM_TO_DEV;
 		dmaconf.dst_addr = pdata->qspi_ahb_phy;
 		dmaconf.dst_addr_width = 4;
+		dmaconf.dst_maxburst = 1;
 	}
 
 	/* map the buffer address */

drivers/spi/spi-dw-mmio.c

@@ -90,14 +90,14 @@ static int dw_spi_mmio_probe(struct platform_device *pdev)
 	if(of_property_read_u32(pdev->dev.of_node, "num-chipselect", &prop)) {
 		ret = -ENXIO;
 		dev_err(&pdev->dev, "couldn't determine num-chipselect\n");
-		goto err_irq;
+		goto err_unmap;
 	}
 	dws->num_cs = prop;
 
 	if(of_property_read_u32(pdev->dev.of_node, "bus-num", &prop)) {
 		ret = -ENXIO;
 		dev_err(&pdev->dev, "couldn't determine bus-num\n");
-		goto err_irq;
+		goto err_unmap;
 	}
 	dws->bus_num = prop;
 #else