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clk: qcom: gcc-qcs404: move PLL clocks up
Move PLL clock declarations up, before clock parent tables, so that we can use pll hw clock fields in the next commit. Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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‎drivers/clk/qcom/gcc-qcs404.c‎

Lines changed: 149 additions & 149 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,155 @@ enum {
3535
P_XO,
3636
};
3737

38+
static struct clk_fixed_factor cxo = {
39+
.mult = 1,
40+
.div = 1,
41+
.hw.init = &(struct clk_init_data){
42+
.name = "cxo",
43+
.parent_names = (const char *[]){ "xo-board" },
44+
.num_parents = 1,
45+
.ops = &clk_fixed_factor_ops,
46+
},
47+
};
48+
49+
static struct clk_alpha_pll gpll0_sleep_clk_src = {
50+
.offset = 0x21000,
51+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
52+
.clkr = {
53+
.enable_reg = 0x45008,
54+
.enable_mask = BIT(23),
55+
.enable_is_inverted = true,
56+
.hw.init = &(struct clk_init_data){
57+
.name = "gpll0_sleep_clk_src",
58+
.parent_names = (const char *[]){ "cxo" },
59+
.num_parents = 1,
60+
.ops = &clk_alpha_pll_ops,
61+
},
62+
},
63+
};
64+
65+
static struct clk_alpha_pll gpll0_out_main = {
66+
.offset = 0x21000,
67+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
68+
.flags = SUPPORTS_FSM_MODE,
69+
.clkr = {
70+
.enable_reg = 0x45000,
71+
.enable_mask = BIT(0),
72+
.hw.init = &(struct clk_init_data){
73+
.name = "gpll0_out_main",
74+
.parent_names = (const char *[])
75+
{ "cxo" },
76+
.num_parents = 1,
77+
.ops = &clk_alpha_pll_ops,
78+
},
79+
},
80+
};
81+
82+
static struct clk_alpha_pll gpll0_ao_out_main = {
83+
.offset = 0x21000,
84+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
85+
.flags = SUPPORTS_FSM_MODE,
86+
.clkr = {
87+
.enable_reg = 0x45000,
88+
.enable_mask = BIT(0),
89+
.hw.init = &(struct clk_init_data){
90+
.name = "gpll0_ao_out_main",
91+
.parent_names = (const char *[]){ "cxo" },
92+
.num_parents = 1,
93+
.flags = CLK_IS_CRITICAL,
94+
.ops = &clk_alpha_pll_fixed_ops,
95+
},
96+
},
97+
};
98+
99+
static struct clk_alpha_pll gpll1_out_main = {
100+
.offset = 0x20000,
101+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
102+
.clkr = {
103+
.enable_reg = 0x45000,
104+
.enable_mask = BIT(1),
105+
.hw.init = &(struct clk_init_data){
106+
.name = "gpll1_out_main",
107+
.parent_names = (const char *[]){ "cxo" },
108+
.num_parents = 1,
109+
.ops = &clk_alpha_pll_ops,
110+
},
111+
},
112+
};
113+
114+
/* 930MHz configuration */
115+
static const struct alpha_pll_config gpll3_config = {
116+
.l = 48,
117+
.alpha = 0x0,
118+
.alpha_en_mask = BIT(24),
119+
.post_div_mask = 0xf << 8,
120+
.post_div_val = 0x1 << 8,
121+
.vco_mask = 0x3 << 20,
122+
.main_output_mask = 0x1,
123+
.config_ctl_val = 0x4001055b,
124+
};
125+
126+
static const struct pll_vco gpll3_vco[] = {
127+
{ 700000000, 1400000000, 0 },
128+
};
129+
130+
static struct clk_alpha_pll gpll3_out_main = {
131+
.offset = 0x22000,
132+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
133+
.vco_table = gpll3_vco,
134+
.num_vco = ARRAY_SIZE(gpll3_vco),
135+
.clkr = {
136+
.hw.init = &(struct clk_init_data){
137+
.name = "gpll3_out_main",
138+
.parent_names = (const char *[]){ "cxo" },
139+
.num_parents = 1,
140+
.ops = &clk_alpha_pll_ops,
141+
},
142+
},
143+
};
144+
145+
static struct clk_alpha_pll gpll4_out_main = {
146+
.offset = 0x24000,
147+
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
148+
.clkr = {
149+
.enable_reg = 0x45000,
150+
.enable_mask = BIT(5),
151+
.hw.init = &(struct clk_init_data){
152+
.name = "gpll4_out_main",
153+
.parent_names = (const char *[]){ "cxo" },
154+
.num_parents = 1,
155+
.ops = &clk_alpha_pll_ops,
156+
},
157+
},
158+
};
159+
160+
static struct clk_pll gpll6 = {
161+
.l_reg = 0x37004,
162+
.m_reg = 0x37008,
163+
.n_reg = 0x3700C,
164+
.config_reg = 0x37014,
165+
.mode_reg = 0x37000,
166+
.status_reg = 0x3701C,
167+
.status_bit = 17,
168+
.clkr.hw.init = &(struct clk_init_data){
169+
.name = "gpll6",
170+
.parent_names = (const char *[]){ "cxo" },
171+
.num_parents = 1,
172+
.ops = &clk_pll_ops,
173+
},
174+
};
175+
176+
static struct clk_regmap gpll6_out_aux = {
177+
.enable_reg = 0x45000,
178+
.enable_mask = BIT(7),
179+
.hw.init = &(struct clk_init_data){
180+
.name = "gpll6_out_aux",
181+
.parent_names = (const char *[]){ "gpll6" },
182+
.num_parents = 1,
183+
.ops = &clk_pll_vote_ops,
184+
},
185+
};
186+
38187
static const struct parent_map gcc_parent_map_0[] = {
39188
{ P_XO, 0 },
40189
{ P_GPLL0_OUT_MAIN, 1 },
@@ -224,155 +373,6 @@ static const char * const gcc_parent_names_16[] = {
224373
"gpll0_out_main",
225374
};
226375

227-
static struct clk_fixed_factor cxo = {
228-
.mult = 1,
229-
.div = 1,
230-
.hw.init = &(struct clk_init_data){
231-
.name = "cxo",
232-
.parent_names = (const char *[]){ "xo-board" },
233-
.num_parents = 1,
234-
.ops = &clk_fixed_factor_ops,
235-
},
236-
};
237-
238-
static struct clk_alpha_pll gpll0_sleep_clk_src = {
239-
.offset = 0x21000,
240-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
241-
.clkr = {
242-
.enable_reg = 0x45008,
243-
.enable_mask = BIT(23),
244-
.enable_is_inverted = true,
245-
.hw.init = &(struct clk_init_data){
246-
.name = "gpll0_sleep_clk_src",
247-
.parent_names = (const char *[]){ "cxo" },
248-
.num_parents = 1,
249-
.ops = &clk_alpha_pll_ops,
250-
},
251-
},
252-
};
253-
254-
static struct clk_alpha_pll gpll0_out_main = {
255-
.offset = 0x21000,
256-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
257-
.flags = SUPPORTS_FSM_MODE,
258-
.clkr = {
259-
.enable_reg = 0x45000,
260-
.enable_mask = BIT(0),
261-
.hw.init = &(struct clk_init_data){
262-
.name = "gpll0_out_main",
263-
.parent_names = (const char *[])
264-
{ "cxo" },
265-
.num_parents = 1,
266-
.ops = &clk_alpha_pll_ops,
267-
},
268-
},
269-
};
270-
271-
static struct clk_alpha_pll gpll0_ao_out_main = {
272-
.offset = 0x21000,
273-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
274-
.flags = SUPPORTS_FSM_MODE,
275-
.clkr = {
276-
.enable_reg = 0x45000,
277-
.enable_mask = BIT(0),
278-
.hw.init = &(struct clk_init_data){
279-
.name = "gpll0_ao_out_main",
280-
.parent_names = (const char *[]){ "cxo" },
281-
.num_parents = 1,
282-
.flags = CLK_IS_CRITICAL,
283-
.ops = &clk_alpha_pll_fixed_ops,
284-
},
285-
},
286-
};
287-
288-
static struct clk_alpha_pll gpll1_out_main = {
289-
.offset = 0x20000,
290-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
291-
.clkr = {
292-
.enable_reg = 0x45000,
293-
.enable_mask = BIT(1),
294-
.hw.init = &(struct clk_init_data){
295-
.name = "gpll1_out_main",
296-
.parent_names = (const char *[]){ "cxo" },
297-
.num_parents = 1,
298-
.ops = &clk_alpha_pll_ops,
299-
},
300-
},
301-
};
302-
303-
/* 930MHz configuration */
304-
static const struct alpha_pll_config gpll3_config = {
305-
.l = 48,
306-
.alpha = 0x0,
307-
.alpha_en_mask = BIT(24),
308-
.post_div_mask = 0xf << 8,
309-
.post_div_val = 0x1 << 8,
310-
.vco_mask = 0x3 << 20,
311-
.main_output_mask = 0x1,
312-
.config_ctl_val = 0x4001055b,
313-
};
314-
315-
static const struct pll_vco gpll3_vco[] = {
316-
{ 700000000, 1400000000, 0 },
317-
};
318-
319-
static struct clk_alpha_pll gpll3_out_main = {
320-
.offset = 0x22000,
321-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
322-
.vco_table = gpll3_vco,
323-
.num_vco = ARRAY_SIZE(gpll3_vco),
324-
.clkr = {
325-
.hw.init = &(struct clk_init_data){
326-
.name = "gpll3_out_main",
327-
.parent_names = (const char *[]){ "cxo" },
328-
.num_parents = 1,
329-
.ops = &clk_alpha_pll_ops,
330-
},
331-
},
332-
};
333-
334-
static struct clk_alpha_pll gpll4_out_main = {
335-
.offset = 0x24000,
336-
.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
337-
.clkr = {
338-
.enable_reg = 0x45000,
339-
.enable_mask = BIT(5),
340-
.hw.init = &(struct clk_init_data){
341-
.name = "gpll4_out_main",
342-
.parent_names = (const char *[]){ "cxo" },
343-
.num_parents = 1,
344-
.ops = &clk_alpha_pll_ops,
345-
},
346-
},
347-
};
348-
349-
static struct clk_pll gpll6 = {
350-
.l_reg = 0x37004,
351-
.m_reg = 0x37008,
352-
.n_reg = 0x3700C,
353-
.config_reg = 0x37014,
354-
.mode_reg = 0x37000,
355-
.status_reg = 0x3701C,
356-
.status_bit = 17,
357-
.clkr.hw.init = &(struct clk_init_data){
358-
.name = "gpll6",
359-
.parent_names = (const char *[]){ "cxo" },
360-
.num_parents = 1,
361-
.ops = &clk_pll_ops,
362-
},
363-
};
364-
365-
static struct clk_regmap gpll6_out_aux = {
366-
.enable_reg = 0x45000,
367-
.enable_mask = BIT(7),
368-
.hw.init = &(struct clk_init_data){
369-
.name = "gpll6_out_aux",
370-
.parent_names = (const char *[]){ "gpll6" },
371-
.num_parents = 1,
372-
.ops = &clk_pll_vote_ops,
373-
},
374-
};
375-
376376
static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {
377377
F(19200000, P_XO, 1, 0, 0),
378378
F(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),

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