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158 | 158 | enum mtk_iommu_plat { |
159 | 159 | M4U_MT2712, |
160 | 160 | M4U_MT6779, |
| 161 | + M4U_MT6795, |
161 | 162 | M4U_MT8167, |
162 | 163 | M4U_MT8173, |
163 | 164 | M4U_MT8183, |
@@ -1414,6 +1415,19 @@ static const struct mtk_iommu_plat_data mt6779_data = { |
1414 | 1415 | .larbid_remap = {{0}, {1}, {2}, {3}, {5}, {7, 8}, {10}, {9}}, |
1415 | 1416 | }; |
1416 | 1417 |
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| 1418 | +static const struct mtk_iommu_plat_data mt6795_data = { |
| 1419 | + .m4u_plat = M4U_MT6795, |
| 1420 | + .flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI | |
| 1421 | + HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM | |
| 1422 | + TF_PORT_TO_ADDR_MT8173, |
| 1423 | + .inv_sel_reg = REG_MMU_INV_SEL_GEN1, |
| 1424 | + .banks_num = 1, |
| 1425 | + .banks_enable = {true}, |
| 1426 | + .iova_region = single_domain, |
| 1427 | + .iova_region_nr = ARRAY_SIZE(single_domain), |
| 1428 | + .larbid_remap = {{0}, {1}, {2}, {3}, {4}}, /* Linear mapping. */ |
| 1429 | +}; |
| 1430 | + |
1417 | 1431 | static const struct mtk_iommu_plat_data mt8167_data = { |
1418 | 1432 | .m4u_plat = M4U_MT8167, |
1419 | 1433 | .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | MTK_IOMMU_TYPE_MM, |
@@ -1526,6 +1540,7 @@ static const struct mtk_iommu_plat_data mt8195_data_vpp = { |
1526 | 1540 | static const struct of_device_id mtk_iommu_of_ids[] = { |
1527 | 1541 | { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data}, |
1528 | 1542 | { .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data}, |
| 1543 | + { .compatible = "mediatek,mt6795-m4u", .data = &mt6795_data}, |
1529 | 1544 | { .compatible = "mediatek,mt8167-m4u", .data = &mt8167_data}, |
1530 | 1545 | { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data}, |
1531 | 1546 | { .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data}, |
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