@@ -27,14 +27,13 @@ static unsigned long meson_clk_cpu_dyndiv_recalc_rate(struct clk_hw *hw,
2727 NULL , 0 , data -> div .width );
2828}
2929
30- static long meson_clk_cpu_dyndiv_round_rate (struct clk_hw * hw ,
31- unsigned long rate ,
32- unsigned long * prate )
30+ static int meson_clk_cpu_dyndiv_determine_rate (struct clk_hw * hw ,
31+ struct clk_rate_request * req )
3332{
3433 struct clk_regmap * clk = to_clk_regmap (hw );
3534 struct meson_clk_cpu_dyndiv_data * data = meson_clk_cpu_dyndiv_data (clk );
3635
37- return divider_round_rate (hw , rate , prate , NULL , data -> div .width , 0 );
36+ return divider_determine_rate (hw , req , NULL , data -> div .width , 0 );
3837}
3938
4039static int meson_clk_cpu_dyndiv_set_rate (struct clk_hw * hw , unsigned long rate ,
@@ -63,7 +62,7 @@ static int meson_clk_cpu_dyndiv_set_rate(struct clk_hw *hw, unsigned long rate,
6362
6463const struct clk_ops meson_clk_cpu_dyndiv_ops = {
6564 .recalc_rate = meson_clk_cpu_dyndiv_recalc_rate ,
66- .round_rate = meson_clk_cpu_dyndiv_round_rate ,
65+ .determine_rate = meson_clk_cpu_dyndiv_determine_rate ,
6766 .set_rate = meson_clk_cpu_dyndiv_set_rate ,
6867};
6968EXPORT_SYMBOL_GPL (meson_clk_cpu_dyndiv_ops );
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