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23 | 23 | #define PWM_SIFIVE_PWMCFG 0x0 |
24 | 24 | #define PWM_SIFIVE_PWMCOUNT 0x8 |
25 | 25 | #define PWM_SIFIVE_PWMS 0x10 |
26 | | -#define PWM_SIFIVE_PWMCMP0 0x20 |
| 26 | +#define PWM_SIFIVE_PWMCMP(i) (0x20 + 4 * (i)) |
27 | 27 |
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28 | 28 | /* PWMCFG fields */ |
29 | 29 | #define PWM_SIFIVE_PWMCFG_SCALE GENMASK(3, 0) |
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36 | 36 | #define PWM_SIFIVE_PWMCFG_GANG BIT(24) |
37 | 37 | #define PWM_SIFIVE_PWMCFG_IP BIT(28) |
38 | 38 |
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39 | | -/* PWM_SIFIVE_SIZE_PWMCMP is used to calculate offset for pwmcmpX registers */ |
40 | | -#define PWM_SIFIVE_SIZE_PWMCMP 4 |
41 | 39 | #define PWM_SIFIVE_CMPWIDTH 16 |
42 | 40 | #define PWM_SIFIVE_DEFAULT_PERIOD 10000000 |
43 | 41 |
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@@ -112,8 +110,7 @@ static void pwm_sifive_get_state(struct pwm_chip *chip, struct pwm_device *pwm, |
112 | 110 | struct pwm_sifive_ddata *ddata = pwm_sifive_chip_to_ddata(chip); |
113 | 111 | u32 duty, val; |
114 | 112 |
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115 | | - duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP0 + |
116 | | - pwm->hwpwm * PWM_SIFIVE_SIZE_PWMCMP); |
| 113 | + duty = readl(ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm)); |
117 | 114 |
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118 | 115 | state->enabled = duty > 0; |
119 | 116 |
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@@ -194,8 +191,7 @@ static int pwm_sifive_apply(struct pwm_chip *chip, struct pwm_device *pwm, |
194 | 191 | pwm_sifive_update_clock(ddata, clk_get_rate(ddata->clk)); |
195 | 192 | } |
196 | 193 |
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197 | | - writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP0 + |
198 | | - pwm->hwpwm * PWM_SIFIVE_SIZE_PWMCMP); |
| 194 | + writel(frac, ddata->regs + PWM_SIFIVE_PWMCMP(pwm->hwpwm)); |
199 | 195 |
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200 | 196 | if (state->enabled != enabled) |
201 | 197 | pwm_sifive_enable(chip, state->enabled); |
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