@@ -75,7 +75,8 @@ enum BAR_ID {
7575 BAR_ID_1 /* Used for doorbells */
7676};
7777
78- static u32 qed_hw_bar_size (struct qed_hwfn * p_hwfn , enum BAR_ID bar_id )
78+ static u32 qed_hw_bar_size (struct qed_hwfn * p_hwfn ,
79+ struct qed_ptt * p_ptt , enum BAR_ID bar_id )
7980{
8081 u32 bar_reg = (bar_id == BAR_ID_0 ?
8182 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE );
@@ -84,7 +85,7 @@ static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id)
8485 if (IS_VF (p_hwfn -> cdev ))
8586 return 1 << 17 ;
8687
87- val = qed_rd (p_hwfn , p_hwfn -> p_main_ptt , bar_reg );
88+ val = qed_rd (p_hwfn , p_ptt , bar_reg );
8889 if (val )
8990 return 1 << (val + 15 );
9091
@@ -780,7 +781,7 @@ int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
780781 qed_init_clear_rt_data (p_hwfn );
781782
782783 /* prepare QM portion of runtime array */
783- qed_qm_init_pf (p_hwfn );
784+ qed_qm_init_pf (p_hwfn , p_ptt );
784785
785786 /* activate init tool on runtime array */
786787 rc = qed_init_run (p_hwfn , p_ptt , PHASE_QM_PF , p_hwfn -> rel_pf_id ,
@@ -1191,6 +1192,57 @@ static void qed_init_cau_rt_data(struct qed_dev *cdev)
11911192 }
11921193}
11931194
1195+ static void qed_init_cache_line_size (struct qed_hwfn * p_hwfn ,
1196+ struct qed_ptt * p_ptt )
1197+ {
1198+ u32 val , wr_mbs , cache_line_size ;
1199+
1200+ val = qed_rd (p_hwfn , p_ptt , PSWRQ2_REG_WR_MBS0 );
1201+ switch (val ) {
1202+ case 0 :
1203+ wr_mbs = 128 ;
1204+ break ;
1205+ case 1 :
1206+ wr_mbs = 256 ;
1207+ break ;
1208+ case 2 :
1209+ wr_mbs = 512 ;
1210+ break ;
1211+ default :
1212+ DP_INFO (p_hwfn ,
1213+ "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n" ,
1214+ val );
1215+ return ;
1216+ }
1217+
1218+ cache_line_size = min_t (u32 , L1_CACHE_BYTES , wr_mbs );
1219+ switch (cache_line_size ) {
1220+ case 32 :
1221+ val = 0 ;
1222+ break ;
1223+ case 64 :
1224+ val = 1 ;
1225+ break ;
1226+ case 128 :
1227+ val = 2 ;
1228+ break ;
1229+ case 256 :
1230+ val = 3 ;
1231+ break ;
1232+ default :
1233+ DP_INFO (p_hwfn ,
1234+ "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n" ,
1235+ cache_line_size );
1236+ }
1237+
1238+ if (L1_CACHE_BYTES > wr_mbs )
1239+ DP_INFO (p_hwfn ,
1240+ "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n" ,
1241+ L1_CACHE_BYTES , wr_mbs );
1242+
1243+ STORE_RT_REG (p_hwfn , PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET , val );
1244+ }
1245+
11941246static int qed_hw_init_common (struct qed_hwfn * p_hwfn ,
11951247 struct qed_ptt * p_ptt , int hw_mode )
11961248{
@@ -1227,17 +1279,7 @@ static int qed_hw_init_common(struct qed_hwfn *p_hwfn,
12271279
12281280 qed_cxt_hw_init_common (p_hwfn );
12291281
1230- /* Close gate from NIG to BRB/Storm; By default they are open, but
1231- * we close them to prevent NIG from passing data to reset blocks.
1232- * Should have been done in the ENGINE phase, but init-tool lacks
1233- * proper port-pretend capabilities.
1234- */
1235- qed_wr (p_hwfn , p_ptt , NIG_REG_RX_BRB_OUT_EN , 0 );
1236- qed_wr (p_hwfn , p_ptt , NIG_REG_STORM_OUT_EN , 0 );
1237- qed_port_pretend (p_hwfn , p_ptt , p_hwfn -> port_id ^ 1 );
1238- qed_wr (p_hwfn , p_ptt , NIG_REG_RX_BRB_OUT_EN , 0 );
1239- qed_wr (p_hwfn , p_ptt , NIG_REG_STORM_OUT_EN , 0 );
1240- qed_port_unpretend (p_hwfn , p_ptt );
1282+ qed_init_cache_line_size (p_hwfn , p_ptt );
12411283
12421284 rc = qed_init_run (p_hwfn , p_ptt , PHASE_ENGINE , ANY_PHASE_ID , hw_mode );
12431285 if (rc )
@@ -1320,7 +1362,7 @@ qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
13201362 int rc = 0 ;
13211363 u8 cond ;
13221364
1323- db_bar_size = qed_hw_bar_size (p_hwfn , BAR_ID_1 );
1365+ db_bar_size = qed_hw_bar_size (p_hwfn , p_ptt , BAR_ID_1 );
13241366 if (p_hwfn -> cdev -> num_hwfns > 1 )
13251367 db_bar_size /= 2 ;
13261368
@@ -1431,7 +1473,7 @@ static int qed_hw_init_pf(struct qed_hwfn *p_hwfn,
14311473 p_hwfn -> qm_info .pf_rl = 100000 ;
14321474 }
14331475
1434- qed_cxt_hw_init_pf (p_hwfn );
1476+ qed_cxt_hw_init_pf (p_hwfn , p_ptt );
14351477
14361478 qed_int_igu_init_rt (p_hwfn );
14371479
@@ -1852,18 +1894,21 @@ int qed_hw_stop(struct qed_dev *cdev)
18521894 return rc2 ;
18531895}
18541896
1855- void qed_hw_stop_fastpath (struct qed_dev * cdev )
1897+ int qed_hw_stop_fastpath (struct qed_dev * cdev )
18561898{
18571899 int j ;
18581900
18591901 for_each_hwfn (cdev , j ) {
18601902 struct qed_hwfn * p_hwfn = & cdev -> hwfns [j ];
1861- struct qed_ptt * p_ptt = p_hwfn -> p_main_ptt ;
1903+ struct qed_ptt * p_ptt ;
18621904
18631905 if (IS_VF (cdev )) {
18641906 qed_vf_pf_int_cleanup (p_hwfn );
18651907 continue ;
18661908 }
1909+ p_ptt = qed_ptt_acquire (p_hwfn );
1910+ if (!p_ptt )
1911+ return - EAGAIN ;
18671912
18681913 DP_VERBOSE (p_hwfn ,
18691914 NETIF_MSG_IFDOWN , "Shutting down the fastpath\n" );
@@ -1881,17 +1926,28 @@ void qed_hw_stop_fastpath(struct qed_dev *cdev)
18811926
18821927 /* Need to wait 1ms to guarantee SBs are cleared */
18831928 usleep_range (1000 , 2000 );
1929+ qed_ptt_release (p_hwfn , p_ptt );
18841930 }
1931+
1932+ return 0 ;
18851933}
18861934
1887- void qed_hw_start_fastpath (struct qed_hwfn * p_hwfn )
1935+ int qed_hw_start_fastpath (struct qed_hwfn * p_hwfn )
18881936{
1937+ struct qed_ptt * p_ptt ;
1938+
18891939 if (IS_VF (p_hwfn -> cdev ))
1890- return ;
1940+ return 0 ;
1941+
1942+ p_ptt = qed_ptt_acquire (p_hwfn );
1943+ if (!p_ptt )
1944+ return - EAGAIN ;
18911945
18921946 /* Re-open incoming traffic */
1893- qed_wr (p_hwfn , p_hwfn -> p_main_ptt ,
1894- NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF , 0x0 );
1947+ qed_wr (p_hwfn , p_ptt , NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF , 0x0 );
1948+ qed_ptt_release (p_hwfn , p_ptt );
1949+
1950+ return 0 ;
18951951}
18961952
18971953/* Free hwfn memory and resources acquired in hw_hwfn_prepare */
@@ -1989,12 +2045,17 @@ static void qed_hw_set_feat(struct qed_hwfn *p_hwfn)
19892045 QED_VF_L2_QUE ));
19902046 }
19912047
2048+ if (p_hwfn -> hw_info .personality == QED_PCI_ISCSI )
2049+ feat_num [QED_ISCSI_CQ ] = min_t (u32 , RESC_NUM (p_hwfn , QED_SB ),
2050+ RESC_NUM (p_hwfn ,
2051+ QED_CMDQS_CQS ));
19922052 DP_VERBOSE (p_hwfn ,
19932053 NETIF_MSG_PROBE ,
1994- "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d\n" ,
2054+ "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d ISCSI_CQ=%d #SBS=%d\n" ,
19952055 (int )FEAT_NUM (p_hwfn , QED_PF_L2_QUE ),
19962056 (int )FEAT_NUM (p_hwfn , QED_VF_L2_QUE ),
19972057 (int )FEAT_NUM (p_hwfn , QED_RDMA_CNQ ),
2058+ (int )FEAT_NUM (p_hwfn , QED_ISCSI_CQ ),
19982059 RESC_NUM (p_hwfn , QED_SB ));
19992060}
20002061
@@ -2697,9 +2758,9 @@ qed_get_hw_info(struct qed_hwfn *p_hwfn,
26972758 return qed_hw_get_resc (p_hwfn , p_ptt );
26982759}
26992760
2700- static int qed_get_dev_info (struct qed_dev * cdev )
2761+ static int qed_get_dev_info (struct qed_hwfn * p_hwfn , struct qed_ptt * p_ptt )
27012762{
2702- struct qed_hwfn * p_hwfn = QED_LEADING_HWFN ( cdev ) ;
2763+ struct qed_dev * cdev = p_hwfn -> cdev ;
27032764 u16 device_id_mask ;
27042765 u32 tmp ;
27052766
@@ -2721,15 +2782,13 @@ static int qed_get_dev_info(struct qed_dev *cdev)
27212782 return - EBUSY ;
27222783 }
27232784
2724- cdev -> chip_num = (u16 )qed_rd (p_hwfn , p_hwfn -> p_main_ptt ,
2725- MISCS_REG_CHIP_NUM );
2726- cdev -> chip_rev = (u16 )qed_rd (p_hwfn , p_hwfn -> p_main_ptt ,
2727- MISCS_REG_CHIP_REV );
2785+ cdev -> chip_num = (u16 )qed_rd (p_hwfn , p_ptt , MISCS_REG_CHIP_NUM );
2786+ cdev -> chip_rev = (u16 )qed_rd (p_hwfn , p_ptt , MISCS_REG_CHIP_REV );
2787+
27282788 MASK_FIELD (CHIP_REV , cdev -> chip_rev );
27292789
27302790 /* Learn number of HW-functions */
2731- tmp = qed_rd (p_hwfn , p_hwfn -> p_main_ptt ,
2732- MISCS_REG_CMT_ENABLED_FOR_PAIR );
2791+ tmp = qed_rd (p_hwfn , p_ptt , MISCS_REG_CMT_ENABLED_FOR_PAIR );
27332792
27342793 if (tmp & (1 << p_hwfn -> rel_pf_id )) {
27352794 DP_NOTICE (cdev -> hwfns , "device in CMT mode\n" );
@@ -2738,11 +2797,10 @@ static int qed_get_dev_info(struct qed_dev *cdev)
27382797 cdev -> num_hwfns = 1 ;
27392798 }
27402799
2741- cdev -> chip_bond_id = qed_rd (p_hwfn , p_hwfn -> p_main_ptt ,
2800+ cdev -> chip_bond_id = qed_rd (p_hwfn , p_ptt ,
27422801 MISCS_REG_CHIP_TEST_REG ) >> 4 ;
27432802 MASK_FIELD (CHIP_BOND_ID , cdev -> chip_bond_id );
2744- cdev -> chip_metal = (u16 )qed_rd (p_hwfn , p_hwfn -> p_main_ptt ,
2745- MISCS_REG_CHIP_METAL );
2803+ cdev -> chip_metal = (u16 )qed_rd (p_hwfn , p_ptt , MISCS_REG_CHIP_METAL );
27462804 MASK_FIELD (CHIP_METAL , cdev -> chip_metal );
27472805
27482806 DP_INFO (cdev -> hwfns ,
@@ -2795,7 +2853,7 @@ static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn,
27952853
27962854 /* First hwfn learns basic information, e.g., number of hwfns */
27972855 if (!p_hwfn -> my_id ) {
2798- rc = qed_get_dev_info (p_hwfn -> cdev );
2856+ rc = qed_get_dev_info (p_hwfn , p_hwfn -> p_main_ptt );
27992857 if (rc )
28002858 goto err1 ;
28012859 }
@@ -2866,11 +2924,14 @@ int qed_hw_prepare(struct qed_dev *cdev,
28662924 u8 __iomem * addr ;
28672925
28682926 /* adjust bar offset for second engine */
2869- addr = cdev -> regview + qed_hw_bar_size (p_hwfn , BAR_ID_0 ) / 2 ;
2927+ addr = cdev -> regview +
2928+ qed_hw_bar_size (p_hwfn , p_hwfn -> p_main_ptt ,
2929+ BAR_ID_0 ) / 2 ;
28702930 p_regview = addr ;
28712931
2872- /* adjust doorbell bar offset for second engine */
2873- addr = cdev -> doorbells + qed_hw_bar_size (p_hwfn , BAR_ID_1 ) / 2 ;
2932+ addr = cdev -> doorbells +
2933+ qed_hw_bar_size (p_hwfn , p_hwfn -> p_main_ptt ,
2934+ BAR_ID_1 ) / 2 ;
28742935 p_doorbell = addr ;
28752936
28762937 /* prepare second hw function */
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