|
249 | 249 |
|
250 | 250 | /* PLA_TCR1 */ |
251 | 251 | #define VERSION_MASK 0x7cf0 |
| 252 | +#define IFG_MASK (BIT(3) | BIT(9) | BIT(8)) |
| 253 | +#define IFG_144NS BIT(9) |
| 254 | +#define IFG_96NS (BIT(9) | BIT(8)) |
252 | 255 |
|
253 | 256 | /* PLA_MTPS */ |
254 | 257 | #define MTPS_JUMBO (12 * 1024 / 64) |
@@ -2747,6 +2750,29 @@ static int rtl_stop_rx(struct r8152 *tp) |
2747 | 2750 | return 0; |
2748 | 2751 | } |
2749 | 2752 |
|
| 2753 | +static void rtl_set_ifg(struct r8152 *tp, u16 speed) |
| 2754 | +{ |
| 2755 | + u32 ocp_data; |
| 2756 | + |
| 2757 | + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); |
| 2758 | + ocp_data &= ~IFG_MASK; |
| 2759 | + if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) { |
| 2760 | + ocp_data |= IFG_144NS; |
| 2761 | + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); |
| 2762 | + |
| 2763 | + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); |
| 2764 | + ocp_data &= ~TX10MIDLE_EN; |
| 2765 | + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); |
| 2766 | + } else { |
| 2767 | + ocp_data |= IFG_96NS; |
| 2768 | + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); |
| 2769 | + |
| 2770 | + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); |
| 2771 | + ocp_data |= TX10MIDLE_EN; |
| 2772 | + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); |
| 2773 | + } |
| 2774 | +} |
| 2775 | + |
2750 | 2776 | static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) |
2751 | 2777 | { |
2752 | 2778 | ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, |
@@ -2850,6 +2876,8 @@ static int rtl8153_enable(struct r8152 *tp) |
2850 | 2876 | r8153_set_rx_early_timeout(tp); |
2851 | 2877 | r8153_set_rx_early_size(tp); |
2852 | 2878 |
|
| 2879 | + rtl_set_ifg(tp, rtl8152_get_speed(tp)); |
| 2880 | + |
2853 | 2881 | if (tp->version == RTL_VER_09) { |
2854 | 2882 | u32 ocp_data; |
2855 | 2883 |
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