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evansm7
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powerpc: Free up some CPU feature bits by moving out MMU-related features
Some of the 64bit PPC CPU features are MMU-related, so this patch moves them to MMU_FTR_ bits. All cpu_has_feature()-style tests are moved to mmu_has_feature(), and seven feature bits are freed as a result. Signed-off-by: Matt Evans <[email protected]> Signed-off-by: Benjamin Herrenschmidt <[email protected]>
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-96
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20 files changed

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‎arch/powerpc/include/asm/cputable.h‎

Lines changed: 14 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -178,23 +178,17 @@ extern const char *powerpc_base_platform;
178178
#define LONG_ASM_CONST(x) 0
179179
#endif
180180

181-
#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
182-
#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
183-
#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
181+
184182
#define CPU_FTR_HVMODE_206 LONG_ASM_CONST(0x0000000800000000)
185183
#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
186184
#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
187185
#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
188186
#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
189-
#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
190-
#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
191187
#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
192188
#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
193189
#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
194190
#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
195191
#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
196-
#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
197-
#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
198192
#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
199193
#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
200194
#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
@@ -206,9 +200,10 @@ extern const char *powerpc_base_platform;
206200

207201
#ifndef __ASSEMBLY__
208202

209-
#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
210-
CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
211-
CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
203+
#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
204+
205+
#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_SLB | MMU_FTR_TLBIEL | \
206+
MMU_FTR_16M_PAGE)
212207

213208
/* We only set the altivec features if the kernel was compiled with altivec
214209
* support
@@ -408,38 +403,34 @@ extern const char *powerpc_base_platform;
408403
#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
409404
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
410405
CPU_FTR_MMCRA | CPU_FTR_SMT | \
411-
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
412-
CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS | \
413-
CPU_FTR_POPCNTB)
406+
CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
407+
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
414408
#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
415409
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
416410
CPU_FTR_MMCRA | CPU_FTR_SMT | \
417-
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
411+
CPU_FTR_COHERENT_ICACHE | \
418412
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
419413
CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
420414
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB)
421415
#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
422416
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_HVMODE_206 |\
423417
CPU_FTR_MMCRA | CPU_FTR_SMT | \
424-
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
418+
CPU_FTR_COHERENT_ICACHE | \
425419
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
426420
CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
427421
CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD)
428422
#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
429423
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
430424
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
431-
CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \
432-
CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
425+
CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
433426
CPU_FTR_UNALIGNED_LD_STD)
434427
#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
435-
CPU_FTR_PPCAS_ARCH_V2 | \
436-
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
437-
CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
428+
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
429+
CPU_FTR_PURR | CPU_FTR_REAL_LE)
438430
#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
439431

440432
#define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
441-
CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | \
442-
CPU_FTR_16M_PAGE)
433+
CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
443434

444435
#ifdef __powerpc64__
445436
#ifdef CONFIG_PPC_BOOK3E
@@ -449,7 +440,7 @@ extern const char *powerpc_base_platform;
449440
(CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
450441
CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
451442
CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
452-
CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
443+
CPU_FTR_VSX)
453444
#endif
454445
#else
455446
enum {

‎arch/powerpc/include/asm/mmu.h‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,54 @@
7070
*/
7171
#define MMU_FTR_USE_PAIRED_MAS ASM_CONST(0x01000000)
7272

73+
/* MMU is SLB-based
74+
*/
75+
#define MMU_FTR_SLB ASM_CONST(0x02000000)
76+
77+
/* Support 16M large pages
78+
*/
79+
#define MMU_FTR_16M_PAGE ASM_CONST(0x04000000)
80+
81+
/* Supports TLBIEL variant
82+
*/
83+
#define MMU_FTR_TLBIEL ASM_CONST(0x08000000)
84+
85+
/* Supports tlbies w/o locking
86+
*/
87+
#define MMU_FTR_LOCKLESS_TLBIE ASM_CONST(0x10000000)
88+
89+
/* Large pages can be marked CI
90+
*/
91+
#define MMU_FTR_CI_LARGE_PAGE ASM_CONST(0x20000000)
92+
93+
/* 1T segments available
94+
*/
95+
#define MMU_FTR_1T_SEGMENT ASM_CONST(0x40000000)
96+
97+
/* Doesn't support the B bit (1T segment) in SLBIE
98+
*/
99+
#define MMU_FTR_NO_SLBIE_B ASM_CONST(0x80000000)
100+
101+
/* MMU feature bit sets for various CPUs */
102+
#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2 \
103+
MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
104+
#define MMU_FTRS_POWER4 MMU_FTRS_DEFAULT_HPTE_ARCH_V2
105+
#define MMU_FTRS_PPC970 MMU_FTRS_POWER4
106+
#define MMU_FTRS_POWER5 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
107+
#define MMU_FTRS_POWER6 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE
108+
#define MMU_FTRS_POWER7 MMU_FTRS_POWER4 | MMU_FTR_LOCKLESS_TLBIE | \
109+
MMU_FTR_TLBIE_206
110+
#define MMU_FTRS_CELL MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
111+
MMU_FTR_CI_LARGE_PAGE
112+
#define MMU_FTRS_PA6T MMU_FTRS_DEFAULT_HPTE_ARCH_V2 | \
113+
MMU_FTR_CI_LARGE_PAGE | MMU_FTR_NO_SLBIE_B
114+
#define MMU_FTRS_A2 MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX | \
115+
MMU_FTR_USE_TLBIVAX_BCAST | \
116+
MMU_FTR_LOCK_BCAST_INVAL | \
117+
MMU_FTR_USE_TLBRSRV | \
118+
MMU_FTR_USE_PAIRED_MAS | \
119+
MMU_FTR_TLBIEL | \
120+
MMU_FTR_16M_PAGE
73121
#ifndef __ASSEMBLY__
74122
#include <asm/cputable.h>
75123

‎arch/powerpc/include/asm/mmu_context.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
6767
* sub architectures.
6868
*/
6969
#ifdef CONFIG_PPC_STD_MMU_64
70-
if (cpu_has_feature(CPU_FTR_SLB))
70+
if (mmu_has_feature(MMU_FTR_SLB))
7171
switch_slb(tsk, next);
7272
else
7373
switch_stab(tsk, next);

‎arch/powerpc/kernel/cputable.c‎

Lines changed: 19 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -201,7 +201,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
201201
.cpu_name = "POWER4 (gp)",
202202
.cpu_features = CPU_FTRS_POWER4,
203203
.cpu_user_features = COMMON_USER_POWER4,
204-
.mmu_features = MMU_FTR_HPTE_TABLE,
204+
.mmu_features = MMU_FTRS_POWER4,
205205
.icache_bsize = 128,
206206
.dcache_bsize = 128,
207207
.num_pmcs = 8,
@@ -216,7 +216,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
216216
.cpu_name = "POWER4+ (gq)",
217217
.cpu_features = CPU_FTRS_POWER4,
218218
.cpu_user_features = COMMON_USER_POWER4,
219-
.mmu_features = MMU_FTR_HPTE_TABLE,
219+
.mmu_features = MMU_FTRS_POWER4,
220220
.icache_bsize = 128,
221221
.dcache_bsize = 128,
222222
.num_pmcs = 8,
@@ -232,7 +232,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
232232
.cpu_features = CPU_FTRS_PPC970,
233233
.cpu_user_features = COMMON_USER_POWER4 |
234234
PPC_FEATURE_HAS_ALTIVEC_COMP,
235-
.mmu_features = MMU_FTR_HPTE_TABLE,
235+
.mmu_features = MMU_FTRS_PPC970,
236236
.icache_bsize = 128,
237237
.dcache_bsize = 128,
238238
.num_pmcs = 8,
@@ -250,7 +250,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
250250
.cpu_features = CPU_FTRS_PPC970,
251251
.cpu_user_features = COMMON_USER_POWER4 |
252252
PPC_FEATURE_HAS_ALTIVEC_COMP,
253-
.mmu_features = MMU_FTR_HPTE_TABLE,
253+
.mmu_features = MMU_FTRS_PPC970,
254254
.icache_bsize = 128,
255255
.dcache_bsize = 128,
256256
.num_pmcs = 8,
@@ -286,7 +286,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
286286
.cpu_features = CPU_FTRS_PPC970,
287287
.cpu_user_features = COMMON_USER_POWER4 |
288288
PPC_FEATURE_HAS_ALTIVEC_COMP,
289-
.mmu_features = MMU_FTR_HPTE_TABLE,
289+
.mmu_features = MMU_FTRS_PPC970,
290290
.icache_bsize = 128,
291291
.dcache_bsize = 128,
292292
.num_pmcs = 8,
@@ -304,7 +304,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
304304
.cpu_features = CPU_FTRS_PPC970,
305305
.cpu_user_features = COMMON_USER_POWER4 |
306306
PPC_FEATURE_HAS_ALTIVEC_COMP,
307-
.mmu_features = MMU_FTR_HPTE_TABLE,
307+
.mmu_features = MMU_FTRS_PPC970,
308308
.icache_bsize = 128,
309309
.dcache_bsize = 128,
310310
.num_pmcs = 8,
@@ -320,7 +320,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
320320
.cpu_name = "POWER5 (gr)",
321321
.cpu_features = CPU_FTRS_POWER5,
322322
.cpu_user_features = COMMON_USER_POWER5,
323-
.mmu_features = MMU_FTR_HPTE_TABLE,
323+
.mmu_features = MMU_FTRS_POWER5,
324324
.icache_bsize = 128,
325325
.dcache_bsize = 128,
326326
.num_pmcs = 6,
@@ -340,7 +340,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
340340
.cpu_name = "POWER5+ (gs)",
341341
.cpu_features = CPU_FTRS_POWER5,
342342
.cpu_user_features = COMMON_USER_POWER5_PLUS,
343-
.mmu_features = MMU_FTR_HPTE_TABLE,
343+
.mmu_features = MMU_FTRS_POWER5,
344344
.icache_bsize = 128,
345345
.dcache_bsize = 128,
346346
.num_pmcs = 6,
@@ -356,7 +356,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
356356
.cpu_name = "POWER5+ (gs)",
357357
.cpu_features = CPU_FTRS_POWER5,
358358
.cpu_user_features = COMMON_USER_POWER5_PLUS,
359-
.mmu_features = MMU_FTR_HPTE_TABLE,
359+
.mmu_features = MMU_FTRS_POWER5,
360360
.icache_bsize = 128,
361361
.dcache_bsize = 128,
362362
.num_pmcs = 6,
@@ -373,7 +373,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
373373
.cpu_name = "POWER5+",
374374
.cpu_features = CPU_FTRS_POWER5,
375375
.cpu_user_features = COMMON_USER_POWER5_PLUS,
376-
.mmu_features = MMU_FTR_HPTE_TABLE,
376+
.mmu_features = MMU_FTRS_POWER5,
377377
.icache_bsize = 128,
378378
.dcache_bsize = 128,
379379
.oprofile_cpu_type = "ppc64/ibm-compat-v1",
@@ -387,7 +387,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
387387
.cpu_features = CPU_FTRS_POWER6,
388388
.cpu_user_features = COMMON_USER_POWER6 |
389389
PPC_FEATURE_POWER6_EXT,
390-
.mmu_features = MMU_FTR_HPTE_TABLE,
390+
.mmu_features = MMU_FTRS_POWER6,
391391
.icache_bsize = 128,
392392
.dcache_bsize = 128,
393393
.num_pmcs = 6,
@@ -406,7 +406,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
406406
.cpu_name = "POWER6 (architected)",
407407
.cpu_features = CPU_FTRS_POWER6,
408408
.cpu_user_features = COMMON_USER_POWER6,
409-
.mmu_features = MMU_FTR_HPTE_TABLE,
409+
.mmu_features = MMU_FTRS_POWER6,
410410
.icache_bsize = 128,
411411
.dcache_bsize = 128,
412412
.oprofile_cpu_type = "ppc64/ibm-compat-v1",
@@ -419,8 +419,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
419419
.cpu_name = "POWER7 (architected)",
420420
.cpu_features = CPU_FTRS_POWER7,
421421
.cpu_user_features = COMMON_USER_POWER7,
422-
.mmu_features = MMU_FTR_HPTE_TABLE |
423-
MMU_FTR_TLBIE_206,
422+
.mmu_features = MMU_FTRS_POWER7,
424423
.icache_bsize = 128,
425424
.dcache_bsize = 128,
426425
.oprofile_type = PPC_OPROFILE_POWER4,
@@ -435,8 +434,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
435434
.cpu_name = "POWER7 (raw)",
436435
.cpu_features = CPU_FTRS_POWER7,
437436
.cpu_user_features = COMMON_USER_POWER7,
438-
.mmu_features = MMU_FTR_HPTE_TABLE |
439-
MMU_FTR_TLBIE_206,
437+
.mmu_features = MMU_FTRS_POWER7,
440438
.icache_bsize = 128,
441439
.dcache_bsize = 128,
442440
.num_pmcs = 6,
@@ -453,8 +451,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
453451
.cpu_name = "POWER7+ (raw)",
454452
.cpu_features = CPU_FTRS_POWER7,
455453
.cpu_user_features = COMMON_USER_POWER7,
456-
.mmu_features = MMU_FTR_HPTE_TABLE |
457-
MMU_FTR_TLBIE_206,
454+
.mmu_features = MMU_FTRS_POWER7,
458455
.icache_bsize = 128,
459456
.dcache_bsize = 128,
460457
.num_pmcs = 6,
@@ -473,7 +470,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
473470
.cpu_user_features = COMMON_USER_PPC64 |
474471
PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP |
475472
PPC_FEATURE_SMT,
476-
.mmu_features = MMU_FTR_HPTE_TABLE,
473+
.mmu_features = MMU_FTRS_CELL,
477474
.icache_bsize = 128,
478475
.dcache_bsize = 128,
479476
.num_pmcs = 4,
@@ -488,7 +485,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
488485
.cpu_name = "PA6T",
489486
.cpu_features = CPU_FTRS_PA6T,
490487
.cpu_user_features = COMMON_USER_PA6T,
491-
.mmu_features = MMU_FTR_HPTE_TABLE,
488+
.mmu_features = MMU_FTRS_PA6T,
492489
.icache_bsize = 64,
493490
.dcache_bsize = 64,
494491
.num_pmcs = 6,
@@ -505,7 +502,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
505502
.cpu_name = "POWER4 (compatible)",
506503
.cpu_features = CPU_FTRS_COMPATIBLE,
507504
.cpu_user_features = COMMON_USER_PPC64,
508-
.mmu_features = MMU_FTR_HPTE_TABLE,
505+
.mmu_features = MMU_FTRS_DEFAULT_HPTE_ARCH_V2,
509506
.icache_bsize = 128,
510507
.dcache_bsize = 128,
511508
.num_pmcs = 6,
@@ -2020,11 +2017,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
20202017
.cpu_name = "A2 (>= DD2)",
20212018
.cpu_features = CPU_FTRS_A2,
20222019
.cpu_user_features = COMMON_USER_PPC64,
2023-
.mmu_features = MMU_FTR_TYPE_3E | MMU_FTR_USE_TLBILX |
2024-
MMU_FTR_USE_TLBIVAX_BCAST |
2025-
MMU_FTR_LOCK_BCAST_INVAL |
2026-
MMU_FTR_USE_TLBRSRV |
2027-
MMU_FTR_USE_PAIRED_MAS,
2020+
.mmu_features = MMU_FTRS_A2,
20282021
.icache_bsize = 64,
20292022
.dcache_bsize = 64,
20302023
.num_pmcs = 0,

‎arch/powerpc/kernel/entry_64.S‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -468,10 +468,10 @@ BEGIN_FTR_SECTION
468468
FTR_SECTION_ELSE_NESTED(95)
469469
clrrdi r6,r8,40 /* get its 1T ESID */
470470
clrrdi r9,r1,40 /* get current sp 1T ESID */
471-
ALT_FTR_SECTION_END_NESTED_IFCLR(CPU_FTR_1T_SEGMENT, 95)
471+
ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_1T_SEGMENT, 95)
472472
FTR_SECTION_ELSE
473473
b 2f
474-
ALT_FTR_SECTION_END_IFSET(CPU_FTR_SLB)
474+
ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_SLB)
475475
clrldi. r0,r6,2 /* is new ESID c00000000? */
476476
cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
477477
cror eq,4*cr1+eq,eq
@@ -485,7 +485,7 @@ BEGIN_FTR_SECTION
485485
li r9,MMU_SEGSIZE_1T /* insert B field */
486486
oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
487487
rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
488-
END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
488+
END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
489489

490490
/* Update the last bolted SLB. No write barriers are needed
491491
* here, provided we only update the current CPU's SLB shadow
@@ -497,7 +497,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_1T_SEGMENT)
497497
std r7,SLBSHADOW_STACKVSID(r9) /* Save VSID */
498498
std r0,SLBSHADOW_STACKESID(r9) /* Save ESID */
499499

500-
/* No need to check for CPU_FTR_NO_SLBIE_B here, since when
500+
/* No need to check for MMU_FTR_NO_SLBIE_B here, since when
501501
* we have 1TB segments, the only CPUs known to have the errata
502502
* only support less than 1TB of system memory and we'll never
503503
* actually hit this code path.

‎arch/powerpc/kernel/exceptions-64s.S‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -102,7 +102,7 @@ BEGIN_FTR_SECTION
102102
EXCEPTION_PROLOG_PSERIES_1(data_access_common, EXC_STD)
103103
FTR_SECTION_ELSE
104104
EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, data_access_common, EXC_STD)
105-
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_SLB)
105+
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_SLB)
106106

107107
. = 0x380
108108
.globl data_access_slb_pSeries
@@ -840,7 +840,7 @@ _STATIC(do_hash_page)
840840
BEGIN_FTR_SECTION
841841
andis. r0,r4,0x0020 /* Is it a segment table fault? */
842842
bne- do_ste_alloc /* If so handle it */
843-
END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
843+
END_MMU_FTR_SECTION_IFCLR(MMU_FTR_SLB)
844844

845845
clrrdi r11,r1,THREAD_SHIFT
846846
lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */

‎arch/powerpc/kernel/process.c‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -757,11 +757,11 @@ int copy_thread(unsigned long clone_flags, unsigned long usp,
757757
_ALIGN_UP(sizeof(struct thread_info), 16);
758758

759759
#ifdef CONFIG_PPC_STD_MMU_64
760-
if (cpu_has_feature(CPU_FTR_SLB)) {
760+
if (mmu_has_feature(MMU_FTR_SLB)) {
761761
unsigned long sp_vsid;
762762
unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
763763

764-
if (cpu_has_feature(CPU_FTR_1T_SEGMENT))
764+
if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
765765
sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
766766
<< SLB_VSID_SHIFT_1T;
767767
else

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