@@ -1309,48 +1309,6 @@ void b53_port_event(struct dsa_switch *ds, int port)
13091309}
13101310EXPORT_SYMBOL (b53_port_event );
13111311
1312- void b53_phylink_validate (struct dsa_switch * ds , int port ,
1313- unsigned long * supported ,
1314- struct phylink_link_state * state )
1315- {
1316- struct b53_device * dev = ds -> priv ;
1317- __ETHTOOL_DECLARE_LINK_MODE_MASK (mask ) = { 0 , };
1318-
1319- if (dev -> ops -> serdes_phylink_validate )
1320- dev -> ops -> serdes_phylink_validate (dev , port , mask , state );
1321-
1322- /* Allow all the expected bits */
1323- phylink_set (mask , Autoneg );
1324- phylink_set_port_modes (mask );
1325- phylink_set (mask , Pause );
1326- phylink_set (mask , Asym_Pause );
1327-
1328- /* With the exclusion of 5325/5365, MII, Reverse MII and 802.3z, we
1329- * support Gigabit, including Half duplex.
1330- *
1331- * FIXME: this is weird - 802.3z is always Gigabit, but we exclude
1332- * it here. Why? This makes no sense.
1333- */
1334- if (!(state -> interface == PHY_INTERFACE_MODE_MII ||
1335- state -> interface == PHY_INTERFACE_MODE_REVMII ||
1336- phy_interface_mode_is_8023z (state -> interface ) ||
1337- is5325 (dev ) || is5365 (dev ))) {
1338- phylink_set (mask , 1000b aseT_Full );
1339- phylink_set (mask , 1000b aseT_Half );
1340- }
1341-
1342- if (!phy_interface_mode_is_8023z (state -> interface )) {
1343- phylink_set (mask , 10b aseT_Half );
1344- phylink_set (mask , 10b aseT_Full );
1345- phylink_set (mask , 100b aseT_Half );
1346- phylink_set (mask , 100b aseT_Full );
1347- }
1348-
1349- linkmode_and (supported , supported , mask );
1350- linkmode_and (state -> advertising , state -> advertising , mask );
1351- }
1352- EXPORT_SYMBOL (b53_phylink_validate );
1353-
13541312static void b53_phylink_get_caps (struct dsa_switch * ds , int port ,
13551313 struct phylink_config * config )
13561314{
@@ -1362,14 +1320,26 @@ static void b53_phylink_get_caps(struct dsa_switch *ds, int port,
13621320 /* These switches appear to support MII and RevMII too, but beyond
13631321 * this, the code gives very few clues. FIXME: We probably need more
13641322 * interface modes here.
1323+ *
1324+ * According to b53_srab_mux_init(), ports 3..5 can support:
1325+ * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting.
1326+ * However, the interface mode read from the MUX configuration is
1327+ * not passed back to DSA, so phylink uses NA.
1328+ * DT can specify RGMII for ports 0, 1.
1329+ * For MDIO, port 8 can be RGMII_TXID.
13651330 */
13661331 __set_bit (PHY_INTERFACE_MODE_MII , config -> supported_interfaces );
13671332 __set_bit (PHY_INTERFACE_MODE_REVMII , config -> supported_interfaces );
13681333
13691334 config -> mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
13701335 MAC_10 | MAC_100 ;
13711336
1372- /* 5325/5365 are not capable of gigabit speeds, everything else is */
1337+ /* 5325/5365 are not capable of gigabit speeds, everything else is.
1338+ * Note: the original code also exclulded Gigagbit for MII, RevMII
1339+ * and 802.3z modes. MII and RevMII are not able to work above 100M,
1340+ * so will be excluded by the generic validator implementation.
1341+ * However, the exclusion of Gigabit for 802.3z just seems wrong.
1342+ */
13731343 if (!(is5325 (dev ) || is5365 (dev )))
13741344 config -> mac_capabilities |= MAC_1000 ;
13751345
@@ -2288,7 +2258,6 @@ static const struct dsa_switch_ops b53_switch_ops = {
22882258 .phy_write = b53_phy_write16 ,
22892259 .adjust_link = b53_adjust_link ,
22902260 .phylink_get_caps = b53_phylink_get_caps ,
2291- .phylink_validate = b53_phylink_validate ,
22922261 .phylink_mac_link_state = b53_phylink_mac_link_state ,
22932262 .phylink_mac_config = b53_phylink_mac_config ,
22942263 .phylink_mac_an_restart = b53_phylink_mac_an_restart ,
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