black / pre-commit

Author: mfhepp

adafruit_si5351.py

@@ -330,15 +330,17 @@ def configure_integer(self, pll, divider, inverted=False):
             control |= pll.clock_control_enabled
             control |= 1 << 6  # Enable integer mode.
             if inverted:
-                control |= 0b00010000 # Bit 4 of the control register = CLKx_INV
+                control |= 0b00010000  # Bit 4 of the control register = CLKx_INV
             else:
-                control &= 0b11101111 # Make sure to turn it off if not inverted            
+                control &= 0b11101111  # Make sure to turn it off if not inverted
             self._si5351._write_u8(self._control, control)
             # Store the PLL and divisor value so frequency can be calculated.
             self._pll = pll
             self._divider = divider
 
-        def configure_fractional(self, pll, divider, numerator, denominator, inverted=False):
+        def configure_fractional(
+            self, pll, divider, numerator, denominator, inverted=False
+        ):
             """Configure the clock output with the specified PLL source
             (should be a PLL instance on the SI5351 class) and specifiec
             fractional divider with numerator/denominator.  Again this is less
@@ -372,9 +374,9 @@ def configure_fractional(self, pll, divider, numerator, denominator, inverted=Fa
             # Clock not inverted, powered up
             control |= pll.clock_control_enabled
             if inverted:
-                control |= 0b00010000 # Bit 4 of the control register = CLKx_INV
+                control |= 0b00010000  # Bit 4 of the control register = CLKx_INV
             else:
-                control &= 0b11101111 # Make sure to turn it off if not inverted
+                control &= 0b11101111  # Make sure to turn it off if not inverted
             self._si5351._write_u8(self._control, control)
             # Store the PLL and divisor value so frequency can be calculated.
             self._pll = pll
@@ -454,7 +456,7 @@ def outputs_enabled(self, val):
 
     def reset_plls(self):
         """Reset both PLLs. This is required when the phase between clocks
-        needs to be non-random. 
+        needs to be non-random.
 
         See e.g.