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fix bug for u50 platform (#337)
* Squashed 'hpc/' changes from 1c6ac0e..f28aa9a f28aa9a update release notes e9f956a Merge branch 'dev2021.1' into next 04c17bc update release notes 366f577 update release notes 26599b6 Merge branch 'dev2021.1' into next 4e191d6 updates a40a413 update notes 01d565a Merge branch 'next' of gitenterprise.xilinx.com:FaaSApps/xf_hpc into next fd999c0 Merge branch 'dev2021.1' into next dbe158b fix version error bb0beb4 Merge pull request #77 from liangm/next 95b21eb merge dev2021.1 4ee28f5 Merge branch 'dev2021.1' of gitenterprise.xilinx.com:FaaSApps/xf_hpc into dev2021.1 a188c06 update makefiles 26fd0ea update release notes b7d6078 Update params.mk 550280c Update params.mk git-subtree-dir: hpc git-subtree-split: f28aa9aab61bf0cb761a7844986cad6a2320479f * Squashed 'quantitative_finance/' changes from 5885ea2..21a780a 21a780a Merge pull request #937 from Zhenhong/next f16ec55 fix connection for u50 CR-1103457 b4d28c0 Merge pull request #935 from jingt/next de3387c update benchmark.rst bafca09 Merge pull request #931 from jingt/next d780d09 modify benchmark html path 0483f82 Merge branch 'next' of https://gitenterprise.xilinx.com/jingt/xf_fintech into next 4470704 modify benchmark html path f43157d Merge pull request #1 from FaaSApps/next 495abdc update git-subtree-dir: quantitative_finance git-subtree-split: 21a780aaedb8103d99c572dd0d005de2b03bdb50 Co-authored-by: sdausr <[email protected]>
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‎quantitative_finance/L2/benchmarks/MCAmericanEngineMultiKernel/README.md‎

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* **Work Directory(Step 1)**
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The steps for library download and environment setup can be found in :ref:`l2_vitis_quantitative_finance`. For getting the design,
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For getting the design,
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cd L2/benchmarks/MCEuropeanEngine
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‎quantitative_finance/L2/benchmarks/MCEuropeanEngine/README.md‎

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# Benchmark of MCEuropeanEngine
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*************************************************
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Overview
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* **Work Directory(Step 1)**
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The steps for library download and environment setup can be found in :ref:`l2_vitis_quantitative_finance`. For getting the design,
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For getting the design,
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cd L2/benchmarks/MCEuropeanEngine
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‎quantitative_finance/L2/benchmarks/TreeEngine/README.md‎

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* **Work Directory(Step 1)**
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The steps for library download and environment setup can be found in :ref:`l2_vitis_quantitative_finance`. For getting the design,
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For getting the design,
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cd L2/benchmarks/TreeEngine/TreeSwaptionEngineHWModel
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‎quantitative_finance/L2/tests/CFBlack76/conn_u50.cfg‎

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[connectivity]
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sp=b76_kernel_1.m_axi_in0_port:DDR[1]
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sp=b76_kernel_1.m_axi_in1_port:DDR[1]
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sp=b76_kernel_1.m_axi_in2_port:DDR[1]
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sp=b76_kernel_1.m_axi_in3_port:DDR[1]
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sp=b76_kernel_1.m_axi_in4_port:DDR[1]
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sp=b76_kernel_1.m_axi_out0_port:DDR[0]
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sp=b76_kernel_1.m_axi_out1_port:DDR[0]
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sp=b76_kernel_1.m_axi_out2_port:DDR[0]
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sp=b76_kernel_1.m_axi_out3_port:DDR[0]
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sp=b76_kernel_1.m_axi_out4_port:DDR[0]
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sp=b76_kernel_1.m_axi_out5_port:DDR[0]
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sp=b76_kernel_1.m_axi_in0_port:HBM[1]
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sp=b76_kernel_1.m_axi_in1_port:HBM[1]
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sp=b76_kernel_1.m_axi_in2_port:HBM[1]
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sp=b76_kernel_1.m_axi_in3_port:HBM[1]
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sp=b76_kernel_1.m_axi_in4_port:HBM[1]
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sp=b76_kernel_1.m_axi_out0_port:HBM[0]
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sp=b76_kernel_1.m_axi_out1_port:HBM[0]
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sp=b76_kernel_1.m_axi_out2_port:HBM[0]
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sp=b76_kernel_1.m_axi_out3_port:HBM[0]
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sp=b76_kernel_1.m_axi_out4_port:HBM[0]
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sp=b76_kernel_1.m_axi_out5_port:HBM[0]

‎quantitative_finance/L2/tests/CFBlackScholes/conn_u50.cfg‎

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[connectivity]
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sp=bs_kernel_1.m_axi_in0_port:DDR[1]
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sp=bs_kernel_1.m_axi_in1_port:DDR[1]
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sp=bs_kernel_1.m_axi_in2_port:DDR[1]
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sp=bs_kernel_1.m_axi_in3_port:DDR[1]
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sp=bs_kernel_1.m_axi_in4_port:DDR[1]
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sp=bs_kernel_1.m_axi_out0_port:DDR[0]
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sp=bs_kernel_1.m_axi_out1_port:DDR[0]
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sp=bs_kernel_1.m_axi_out2_port:DDR[0]
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sp=bs_kernel_1.m_axi_out3_port:DDR[0]
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sp=bs_kernel_1.m_axi_out4_port:DDR[0]
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sp=bs_kernel_1.m_axi_out5_port:DDR[0]
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sp=bs_kernel_1.m_axi_in0_port:HBM[1]
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sp=bs_kernel_1.m_axi_in1_port:HBM[1]
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sp=bs_kernel_1.m_axi_in2_port:HBM[1]
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sp=bs_kernel_1.m_axi_in3_port:HBM[1]
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sp=bs_kernel_1.m_axi_in4_port:HBM[1]
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sp=bs_kernel_1.m_axi_out0_port:HBM[0]
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sp=bs_kernel_1.m_axi_out1_port:HBM[0]
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sp=bs_kernel_1.m_axi_out2_port:HBM[0]
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sp=bs_kernel_1.m_axi_out3_port:HBM[0]
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sp=bs_kernel_1.m_axi_out4_port:HBM[0]
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sp=bs_kernel_1.m_axi_out5_port:HBM[0]

‎quantitative_finance/L2/tests/CFBlackScholesMerton/conn_u50.cfg‎

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[connectivity]
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sp=bsm_kernel_1.m_axi_in0_port:DDR[1]
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sp=bsm_kernel_1.m_axi_in1_port:DDR[1]
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sp=bsm_kernel_1.m_axi_in2_port:DDR[1]
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sp=bsm_kernel_1.m_axi_in3_port:DDR[1]
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sp=bsm_kernel_1.m_axi_in4_port:DDR[1]
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sp=bsm_kernel_1.m_axi_in5_port:DDR[1]
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sp=bsm_kernel_1.m_axi_out0_port:DDR[0]
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sp=bsm_kernel_1.m_axi_out1_port:DDR[0]
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sp=bsm_kernel_1.m_axi_out2_port:DDR[0]
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sp=bsm_kernel_1.m_axi_out3_port:DDR[0]
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sp=bsm_kernel_1.m_axi_out4_port:DDR[0]
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sp=bsm_kernel_1.m_axi_out5_port:DDR[0]
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sp=bsm_kernel_1.m_axi_in0_port:HBM[1]
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sp=bsm_kernel_1.m_axi_in1_port:HBM[1]
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sp=bsm_kernel_1.m_axi_in2_port:HBM[1]
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sp=bsm_kernel_1.m_axi_in3_port:HBM[1]
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sp=bsm_kernel_1.m_axi_in4_port:HBM[1]
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sp=bsm_kernel_1.m_axi_in5_port:HBM[1]
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sp=bsm_kernel_1.m_axi_out0_port:HBM[0]
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sp=bsm_kernel_1.m_axi_out1_port:HBM[0]
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sp=bsm_kernel_1.m_axi_out2_port:HBM[0]
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sp=bsm_kernel_1.m_axi_out3_port:HBM[0]
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sp=bsm_kernel_1.m_axi_out4_port:HBM[0]
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sp=bsm_kernel_1.m_axi_out5_port:HBM[0]
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‎quantitative_finance/L2/tests/GarmanKohlhagenEngine/conn_u50.cfg‎

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[connectivity]
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sp=gk_kernel_1.m_axi_in0_port:DDR[0]
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sp=gk_kernel_1.m_axi_in1_port:DDR[0]
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sp=gk_kernel_1.m_axi_in2_port:DDR[0]
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sp=gk_kernel_1.m_axi_in3_port:DDR[0]
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sp=gk_kernel_1.m_axi_in4_port:DDR[0]
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sp=gk_kernel_1.m_axi_in5_port:DDR[0]
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sp=gk_kernel_1.m_axi_out0_port:DDR[1]
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sp=gk_kernel_1.m_axi_out1_port:DDR[1]
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sp=gk_kernel_1.m_axi_out2_port:DDR[1]
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sp=gk_kernel_1.m_axi_out3_port:DDR[1]
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sp=gk_kernel_1.m_axi_out4_port:DDR[1]
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sp=gk_kernel_1.m_axi_out5_port:DDR[1]
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sp=gk_kernel_1.m_axi_in0_port:HBM[0]
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sp=gk_kernel_1.m_axi_in1_port:HBM[0]
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sp=gk_kernel_1.m_axi_in2_port:HBM[0]
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sp=gk_kernel_1.m_axi_in3_port:HBM[0]
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sp=gk_kernel_1.m_axi_in4_port:HBM[0]
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sp=gk_kernel_1.m_axi_in5_port:HBM[0]
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sp=gk_kernel_1.m_axi_out0_port:HBM[1]
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sp=gk_kernel_1.m_axi_out1_port:HBM[1]
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sp=gk_kernel_1.m_axi_out2_port:HBM[1]
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sp=gk_kernel_1.m_axi_out3_port:HBM[1]
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sp=gk_kernel_1.m_axi_out4_port:HBM[1]
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sp=gk_kernel_1.m_axi_out5_port:HBM[1]

‎quantitative_finance/L2/tests/Quanto/conn_u50.cfg‎

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[connectivity]
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sp=quanto_kernel_1.m_axi_in0_port:DDR[0]
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sp=quanto_kernel_1.m_axi_in1_port:DDR[0]
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sp=quanto_kernel_1.m_axi_in2_port:DDR[0]
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sp=quanto_kernel_1.m_axi_in3_port:DDR[0]
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sp=quanto_kernel_1.m_axi_in4_port:DDR[0]
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sp=quanto_kernel_1.m_axi_in5_port:DDR[0]
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sp=quanto_kernel_1.m_axi_in6_port:DDR[0]
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sp=quanto_kernel_1.m_axi_in7_port:DDR[0]
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sp=quanto_kernel_1.m_axi_in8_port:DDR[1]
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sp=quanto_kernel_1.m_axi_in9_port:DDR[1]
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sp=quanto_kernel_1.m_axi_out0_port:DDR[1]
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sp=quanto_kernel_1.m_axi_out1_port:DDR[1]
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sp=quanto_kernel_1.m_axi_out2_port:DDR[1]
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sp=quanto_kernel_1.m_axi_out3_port:DDR[1]
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sp=quanto_kernel_1.m_axi_out4_port:DDR[1]
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sp=quanto_kernel_1.m_axi_out5_port:DDR[1]
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sp=quanto_kernel_1.m_axi_in0_port:HBM[0]
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sp=quanto_kernel_1.m_axi_in1_port:HBM[0]
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sp=quanto_kernel_1.m_axi_in2_port:HBM[0]
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sp=quanto_kernel_1.m_axi_in3_port:HBM[0]
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sp=quanto_kernel_1.m_axi_in4_port:HBM[0]
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sp=quanto_kernel_1.m_axi_in5_port:HBM[0]
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sp=quanto_kernel_1.m_axi_in6_port:HBM[0]
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sp=quanto_kernel_1.m_axi_in7_port:HBM[0]
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sp=quanto_kernel_1.m_axi_in8_port:HBM[1]
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sp=quanto_kernel_1.m_axi_in9_port:HBM[1]
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sp=quanto_kernel_1.m_axi_out0_port:HBM[1]
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sp=quanto_kernel_1.m_axi_out1_port:HBM[1]
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sp=quanto_kernel_1.m_axi_out2_port:HBM[1]
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sp=quanto_kernel_1.m_axi_out3_port:HBM[1]
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sp=quanto_kernel_1.m_axi_out4_port:HBM[1]
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sp=quanto_kernel_1.m_axi_out5_port:HBM[1]

‎quantitative_finance/docs/benchmark/benchmark.rst‎ renamed to ‎quantitative_finance/docs/benchmark.rst‎

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Application Scenario
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---------------------
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The application scenarios are provided for each case. User could find as bellow.
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:ref:`MCEuropeanEngine <MCEE_Profiling>`
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:ref:`MCAmericanEngine <MCAE_Profiling>`
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:ref:`TreeEngine <TreeEngine_Profiling>`
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The application scenarios are provided for each case. User could find details in Profiling section under each case's benchmark description page.
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Performance
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-----------

‎quantitative_finance/docs/guide_L1/benchmarks/SVD.rst‎

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..
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Copyright 2019 Xilinx, Inc.
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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.. meta::
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:keywords: benchmark, European, engine, option
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:description: This is a benchmark of MC (Monte-Carlo) European Engine using the Xilinx Vitis environment to compare with QuantLib.
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:xlnxdocumentclass: Document
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:xlnxdocumenttype: Tutorials
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.. _guide_l1_benchmark_SVD_
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*************************************************
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Benchmark of Singular Value Decomposition (SVD)
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*************************************************
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Overview
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========
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This is a benchmark of Singular Value Decomposition. It supports software and hardware emulation as well as running the hardware accelerator on the Alveo U250.
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This example resides in ``L1/benchmarks/SVD`` directory. The tutorial provides a step-by-step guide that covers commands for build and runging kernel.
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Executable Usage
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================
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* **Work Directory(Step 1)**
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The steps for library download and environment setup can be found in :ref:`l2_vitis_quantitative_finance`. For getting the design,
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.. code-block:: bash
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cd L1/benchmarks/SVD
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* **Build kernel(Step 2)**
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Run the following make command to build your XCLBIN and host binary targeting a specific device. Please be noticed that this process will take a long time, maybe couple of hours.
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.. code-block:: bash
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source /opt/xilinx/Vitis/2021.1/settings64.sh
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source /opt/xilinx/xrt/setenv.sh
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export DEVICE=/opt/xilinx/platforms/xilinx_u250_xdma_201830_2/xilinx_u250_xdma_201830_2.xpfm
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export TARGET=hw
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make run
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* **Run kernel(Step 3)**
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To get the benchmark results, please run the following command.
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.. code-block:: bash
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./build_dir.hw.xilinx_u250_xdma_201830_2/host.exe -xclbin build_dir.hw.xilinx_u250_xdma_201830_2/kernel_svd_0.xclbin
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Input Arguments:
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.. code-block:: bash
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Usage: test.exe -[-xclbin -rep]
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-xclbin MCEuropeanEngine binary;
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* **Example output(Step 4)**
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.. code-block:: bash
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Found Platform
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Platform Name: Xilinx
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Found Device=xilinx_u250_xdma_201830_2
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INFO: Importing ./build_dir.hw.xilinx_u250_xdma_201830_2/kernel_svd_0.xclbin
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Loading: './build_dir.hw.xilinx_u250_xdma_201830_2.xclbin'
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kernel has been created
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finished data transfer from h2d
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Kernel 0 done!
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kernel execution time : 22 us
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result correct
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.. _SVD_Profiling:
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Profiling
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==========
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The timing performance of the 4x4 SVD is shown in the table below, where matrix size is 4 x 4, and FPGA frequency is 300MHz.
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.. _tab_SVD_Execution_Time:
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.. table:: Timing_Performance
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+-----------------------------------+----------------------------------+
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| Platform | Execution time |
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| +-----------------+----------------+
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| | cold run | warm run |
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+-----------------------------------+-----------------+----------------+
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| MKL Intel(R) Xeon(R) E5-2690 v3 | N/A | 8 us |
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+-----------------------------------+-----------------+----------------+
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| FinTech on U250 | 196 us | 22 us |
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+-----------------------------------+-----------------+----------------+
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| Accelaration Ratio | N/A | 0.36X |
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+-----------------------------------+-----------------+----------------+
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The hardware resources are listed in the following table (vivado 18.3 report without platform).
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.. _tab_SVD_resource:
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.. table:: Resource utilization report of SVD on U250
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:align: center
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+---------------+------+------+------+--------+--------+
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| Inmlemetation | BRAM | URAM | DSP | FF | LUT |
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+---------------+------+------+------+--------+--------+
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| SVD | 9 | 0 | 126 | 46360 | 40313 |
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+---------------+------+------+------+--------+--------+
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.. toctree::
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:maxdepth: 1

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