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Remove Dup function HAL_ETH_SetMDIOClockRange. #711

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Merged
merged 1 commit into from
Feb 16, 2023
Merged

Remove Dup function HAL_ETH_SetMDIOClockRange. #711

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3 changes: 0 additions & 3 deletions source/portable/NetworkInterface/STM32Hxx/NetworkInterface.c
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Original file line number Diff line number Diff line change
Expand Up @@ -278,9 +278,6 @@ BaseType_t xNetworkInterfaceInitialise( void )
HAL_ETH_DescAssignMemory( &( xEthHandle ), uxIndex, pucBuffer, NULL );
}

/* Configure the MDIO Clock */
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@moninom1 moninom1 Feb 14, 2023

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Do we need to add ETH_MAC_MDIO_ClkConfig here?

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@ActoryOu ActoryOu Feb 14, 2023

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No, it calls HAL_ETH_Init in NetworkInterface.c:234, and HAL_ETH_Init calls ETH_MAC_MDIO_ClkConfig in stm32hxx_hal_eth.c:309.

HAL_ETH_SetMDIOClockRange( &( xEthHandle ) );

/* Initialize the MACB and set all PHY properties */
prvMACBProbePhy();

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50 changes: 0 additions & 50 deletions source/portable/NetworkInterface/STM32Hxx/stm32hxx_hal_eth.c
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Expand Up @@ -2171,56 +2171,6 @@ extern SemaphoreHandle_t xTXDescriptorSemaphore;
}
}

/**
* @brief Configures the Clock range of ETH MDIO interface.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
void HAL_ETH_SetMDIOClockRange( ETH_HandleTypeDef * heth )
{
uint32_t tmpreg, hclk;

/* Get the ETHERNET MACMDIOAR value */
tmpreg = ( heth->Instance )->MACMDIOAR;

/* Clear CSR Clock Range bits */
tmpreg &= ~ETH_MACMDIOAR_CR;

/* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();

/* Set CR bits depending on hclk value */
if( ( hclk >= 20000000U ) && ( hclk < 35000000U ) )
{
/* CSR Clock Range between 20-35 MHz */
tmpreg |= ( uint32_t ) ETH_MACMDIOAR_CR_DIV16;
}
else if( ( hclk >= 35000000U ) && ( hclk < 60000000U ) )
{
/* CSR Clock Range between 35-60 MHz */
tmpreg |= ( uint32_t ) ETH_MACMDIOAR_CR_DIV26;
}
else if( ( hclk >= 60000000U ) && ( hclk < 100000000U ) )
{
/* CSR Clock Range between 60-100 MHz */
tmpreg |= ( uint32_t ) ETH_MACMDIOAR_CR_DIV42;
}
else if( ( hclk >= 100000000U ) && ( hclk < 150000000U ) )
{
/* CSR Clock Range between 100-150 MHz */
tmpreg |= ( uint32_t ) ETH_MACMDIOAR_CR_DIV62;
}
else /* (hclk >= 150000000)&&(hclk <= 200000000) */
{
/* CSR Clock Range between 150-200 MHz */
tmpreg |= ( uint32_t ) ETH_MACMDIOAR_CR_DIV102;
}

/* Configure the CSR Clock Range */
( heth->Instance )->MACMDIOAR = ( uint32_t ) tmpreg;
}

/**
* @brief Set the ETH MAC (L2) Filters configuration.
* @param heth: pointer to a ETH_HandleTypeDef structure that contains
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1 change: 0 additions & 1 deletion source/portable/NetworkInterface/STM32Hxx/stm32hxx_hal_eth.h
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Expand Up @@ -1808,7 +1808,6 @@
ETH_MACConfigTypeDef * macconf );
HAL_StatusTypeDef HAL_ETH_SetDMAConfig( ETH_HandleTypeDef * heth,
ETH_DMAConfigTypeDef * dmaconf );
void HAL_ETH_SetMDIOClockRange( ETH_HandleTypeDef * heth );

/* MAC VLAN Processing APIs ************************************************/
void HAL_ETH_SetRxVLANIdentifier( ETH_HandleTypeDef * heth,
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