Skip to content

Commit db8f233

Browse files
committed
Remove the check for clear tick interrupt. Format comments a little. Set copyright year for 2024
1 parent 797f2f2 commit db8f233

File tree

6 files changed

+25
-30
lines changed

6 files changed

+25
-30
lines changed

portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.S

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
3-
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
3+
* Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
44
*
55
* SPDX-License-Identifier: MIT
66
*

portable/GCC/ARM_CRx_MPU/mpu_wrappers_v2_asm.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
3-
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
3+
* Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
44
*
55
* SPDX-License-Identifier: MIT
66
*

portable/GCC/ARM_CRx_MPU/port.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
3-
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
3+
* Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
44
*
55
* SPDX-License-Identifier: MIT
66
*

portable/GCC/ARM_CRx_MPU/portASM.S

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
3-
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
3+
* Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
44
*
55
* SPDX-License-Identifier: MIT
66
*

portable/GCC/ARM_CRx_MPU/portmacro.h

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
3-
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
3+
* Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
44
*
55
* SPDX-License-Identifier: MIT
66
*
@@ -132,11 +132,6 @@ extern "C" {
132132
"to call the function that sets up the tick interrupt."
133133
#endif /* configSETUP_TICK_INTERRUPT */
134134

135-
#ifndef configCLEAR_TICK_INTERRUPT
136-
#error "configCLEAR_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h " \
137-
"to clear which ever interrupt was used to generate the tick interrupt."
138-
#endif /* configCLEAR_TICK_INTERRUPT */
139-
140135
#if( configUSE_TICKLESS_IDLE != 0 )
141136
#error This port does not support tickless idle
142137
#endif /* ( configUSE_TICKLESS_IDLE != 0 ) */

portable/GCC/ARM_CRx_MPU/portmacro_asm.h

Lines changed: 20 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
/*
22
* FreeRTOS Kernel <DEVELOPMENT BRANCH>
3-
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
3+
* Copyright (C) 2024 Amazon.com, Inc. or its affiliates. All Rights Reserved.
44
*
55
* SPDX-License-Identifier: MIT
66
*
@@ -47,9 +47,9 @@ extern "C" {
4747
#error "Set configTOTAL_MPU_REGIONS to the number of MPU regions in FreeRTOSConfig.h"
4848
#endif /* configTOTAL_MPU_REGIONS */
4949

50-
/** On the ArmV7-R Architecture the Operating mode of the Processor is set using
51-
* the Current Program Status and Control Register (CPSR) Mode bits, [4:0]
52-
* the only registers banked between modes are the CPSR, Stack Pointer (R13),
50+
/** On the ArmV7-R Architecture the Operating mode of the Processor is set
51+
* using the Current Program Status Register (CPSR) Mode bits, [4:0].
52+
* The only registers banked between modes are the CPSR, Stack Pointer (R13),
5353
* and the Link Register (R14). FIQ mode also banks the GPRs R8-R12
5454
* Of note, the only mode not "Privileged" is User Mode
5555
*
@@ -125,7 +125,7 @@ extern "C" {
125125
#define portPRIVILEGE_BIT ( 0x80000000UL )
126126

127127
/**
128-
* @brief Flag uses to mark that a FreeRTOS Task is privileged.
128+
* @brief Flag used to mark that a FreeRTOS Task is privileged.
129129
* @ingroup Port Privilege
130130
*/
131131
#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
@@ -135,14 +135,14 @@ extern "C" {
135135
* @ingroup Scheduler
136136
* @note This value must not be in use in mpu_syscall_numbers.h
137137
*/
138-
#define portSVC_YIELD 0x0100
138+
#define portSVC_YIELD 0x0100U
139139

140140
/**
141141
* @brief SVC Number to use when exiting a FreeRTOS System Call.
142142
* @ingroup MPU Control
143143
* @note This value must not be in use in mpu_syscall_numbers.h
144144
*/
145-
#define portSVC_SYSTEM_CALL_EXIT 0x0104
145+
#define portSVC_SYSTEM_CALL_EXIT 0x0104U
146146

147147
/**
148148
* @addtogroup MPU Control
@@ -381,30 +381,30 @@ extern "C" {
381381

382382
/**
383383
* @brief The length in ulContext for the General Purpose Registers in bytes.
384-
* @note There are 13 GPRs, R0-R12, the SP, and the LR. Each are 32 bits,
385-
* which leads to the 15 registers * 4 in length.
384+
* @note There are 13 GPRs, R0-R12, the SP, and the LR. Each register is 32
385+
* bits, so the register context length is 15 registers * 4 bytes = 60 bytes.
386386
*/
387387
#define portREGISTER_LENGTH ( 15U * 4U )
388388

389389
/**
390390
* If you KNOW that your system will not utilize the FPU in any capacity
391-
* you can set portENABLE_FPU to 0, which will reduce the per-task RAM usage
392-
* by ( 32 FPRs + 32 bit FPSCR ) * 4 bytes per register = 132, or 0x84, Bytes Per Task
391+
* you can set portENABLE_FPU to 0. This will reduce the per-task RAM usage
392+
* by ( 32 FPRs + 32 bit FPSCR ) * 4 bytes per register = 132 Bytes Per Task.
393+
* It will also increase context swap speed, as these can then be ignored.
393394
* BE CAREFUL DISABLING THIS: Certain APIs will try and optimize themselves
394-
* by using the FPRs. If the FPU context is not saved and this happens it could be
395-
* exceedingly difficult to debug why a strcpy() or other similar function
395+
* by using the FPRs. If the FPU context is not saved and this happens it could
396+
* be exceedingly difficult to debug why a strcpy() or other similar function
396397
* seems to randomly fail.
397398
*/
398399
#ifndef configENABLE_FPU
399400
#define configENABLE_FPU 1
400401
#endif /* configENABLE_FPU */
401402

402403
/**
403-
* @brief Mark if the Floating Point Registers will be saved.
404+
* @brief Mark if the Floating Point Registers (FPRs) will be saved.
404405
* @ingroup Task Context
405-
* @note When using the FPU, we must save additional registers into the task's context
406-
* These consist of the Floating Point Status and Control Register (FPSCR),
407-
* As well as the Floating Point Registers (FPRs)
406+
* @note Using the FPU requires save FPRs into the task's context. As well as
407+
* the Floating Point Status and Control Register (FPSCR).
408408
*/
409409
#define portENABLE_FPU configENABLE_FPU
410410

@@ -440,13 +440,13 @@ extern "C" {
440440

441441
/**
442442
* @brief Numerical offset from the start of a TCB to xSystemCallStackInfo.
443-
* @note In the exception handlers it is necessary to load this variable from the TCB.
443+
* @note This is used in portASM.S to load xSystemCallStackInfo from the TCB.
444444
* This provides an easy way for the exception handlers to get this structure.
445445
* The numerical value here should be equal to:
446-
* sizeof( xRegion ) + sizeof( ulContext ) + sizeof( ulTaskFlags)
446+
* sizeof( xRegion ) + sizeof( ulContext ) + sizeof( ulTaskFlags )
447447
*/
448448
#define portSYSTEM_CALL_INFO_OFFSET \
449-
( ( ( portTOTAL_NUM_REGIONS_IN_TCB * 3U ) + ( MAX_CONTEXT_SIZE ) + 1 ) * 4U )
449+
( ( ( portTOTAL_NUM_REGIONS_IN_TCB * 3U ) + ( MAX_CONTEXT_SIZE ) + 1U ) * 4U )
450450

451451
#ifdef __cplusplus
452452
} /* extern C */

0 commit comments

Comments
 (0)