@@ -48,17 +48,12 @@ volatile uint16_t _write_index; /* fifo position when receiving */
4848/*  var of different device steps during init and receiving  */ 
4949volatile  bool  phase_bd_addr;
5050volatile  bool  phase_tx_power;
51- volatile  bool  phase_gatt_init;
52- volatile  bool  phase_gap_init;
53- volatile  bool  phase_random_addr;
54- volatile  bool  phase_get_random_addr;
5551volatile  bool  phase_reset;
5652volatile  bool  phase_running;
57- volatile   bool  is_random_addr_msg;  
53+ 
5854
5955/* * Bluetooth Device Address */ 
6056static  uint8_t  bd_addr_udn[CONFIG_DATA_PUBADDR_LEN];
61- static  uint8_t  helper_random_addr[6 ];
6257
6358/*  Private functions ---------------------------------------------------------*/ 
6459/* *
@@ -186,16 +181,10 @@ void evt_received(TL_EvtPacket_t *hcievt)
186181              (hcievt->evtserial .evt .payload [0 ] == 0x01 ) &&
187182              (hcievt->evtserial .evt .payload [1 ] == 0x0C ) &&
188183              (hcievt->evtserial .evt .payload [2 ] == 0xFC )) {
189-             /*  First setting must be global address and is_random_addr_msg should be false
190-              * Second setting must be static random address and is_random_addr_msg should be true 
184+             /*  First setting must be global address
191185             */  
192-             if (!is_random_addr_msg) {
193-               phase_bd_addr = true ;
194-               is_random_addr_msg = true ;
195-             } else  {
196-               phase_random_addr = true ;
197-               is_random_addr_msg = false ;
198-             }
186+             phase_bd_addr = true ;
187+ 
199188            if  (hcievt->evtserial .evt .payload [3 ] != 0 ) {
200189#if  defined(PRINT_IPCC_INFO)
201190              printf (" Error: wrong BD Addr\r\n "  );
@@ -218,50 +207,7 @@ void evt_received(TL_EvtPacket_t *hcievt)
218207            /*  rx data is no more useful : not stored in the _rxbuff */ 
219208            break ;
220209          }
221-           /*  check the Rx event of complete the previous gatt init 0xFD01 */ 
222-           if  ((hcievt->evtserial .evt .evtcode  == TL_BLEEVT_CC_OPCODE) &&
223-               (hcievt->evtserial .evt .payload [0 ] == 0x01 ) &&
224-               (hcievt->evtserial .evt .payload [1 ] == 0x01 ) &&
225-               (hcievt->evtserial .evt .payload [2 ] == 0xFD )) {
226-             phase_gatt_init = true ;
227-             if  (hcievt->evtserial .evt .payload [3 ] != 0 ) {
228- #if  defined(PRINT_IPCC_INFO)
229-               printf (" Error: wrong Random Addr\r\n "  );
230- #endif  /* (PRINT_IPCC_INFO)*/ 
231-             }
232-             /*  rx data is no more useful : not stored in the _rxbuff */ 
233-             break ;
234-           }
235-           /*  check the Rx event of complete the previous gap init 0xFC8A */ 
236-           if  ((hcievt->evtserial .evt .evtcode  == TL_BLEEVT_CC_OPCODE) &&
237-               (hcievt->evtserial .evt .payload [0 ] == 0x01 ) &&
238-               (hcievt->evtserial .evt .payload [1 ] == 0x8A ) &&
239-               (hcievt->evtserial .evt .payload [2 ] == 0xFC )) {
240-             phase_gap_init = true ;
241-             if  (hcievt->evtserial .evt .payload [3 ] != 0 ) {
242- #if  defined(PRINT_IPCC_INFO)
243-               printf (" Error: wrong Random Addr\r\n "  );
244- #endif  /* (PRINT_IPCC_INFO)*/ 
245-             }
246-             /*  rx data is no more useful : not stored in the _rxbuff */ 
247-             break ;
248-           }
249-           /*  check the Rx event of complete the previous get random addr opcode 0xFC0D */ 
250-           if  ((hcievt->evtserial .evt .evtcode  == TL_BLEEVT_CC_OPCODE) &&
251-               (hcievt->evtserial .evt .payload [0 ] == 0x01 ) &&
252-               (hcievt->evtserial .evt .payload [1 ] == 0x0D ) &&
253-               (hcievt->evtserial .evt .payload [2 ] == 0xFC )) {
254-             if  (hcievt->evtserial .evt .payload [3 ] != 0 ) {
255- #if  defined(PRINT_IPCC_INFO)
256-               printf (" Error: wrong Random Addr\r\n "  );
257- #endif  /* (PRINT_IPCC_INFO)*/ 
258-             }
259210
260-             memcpy (helper_random_addr, &hcievt->evtserial .evt .payload [5 ], 6 );
261-             phase_get_random_addr = true ;
262-             /*  rx data is no more useful : not stored in the _rxbuff */ 
263-             break ;
264-           }
265211          /*  check if the reset phase is in progress (opcode is 0x0C03) */ 
266212          if  ((hcievt->evtserial .evt .evtcode  == TL_BLEEVT_CC_OPCODE) &&
267213              (hcievt->evtserial .evt .payload [0 ] == 0x01 ) &&
@@ -391,10 +337,10 @@ static bool get_bd_address(uint8_t *bd_addr)
391337
392338    bd_addr[0 ] = (uint8_t )(udn & 0x000000FF );
393339    bd_addr[1 ] = (uint8_t )((udn & 0x0000FF00 ) >> 8 );
394-     bd_addr[2 ] = (uint8_t )((udn &  0x00FF0000 ) >>  16 ) ;
395-     bd_addr[3 ] = (uint8_t )device_id ;
396-     bd_addr[4 ] = (uint8_t )(company_id & 0x000000FF );
397-     bd_addr[5 ] = (uint8_t )((company_id & 0x0000FF00 ) >> 8 );
340+     bd_addr[2 ] = (uint8_t )device_id ;
341+     bd_addr[3 ] = (uint8_t )(company_id &  0x000000FF ) ;
342+     bd_addr[4 ] = (uint8_t )(( company_id & 0x0000FF00 ) >>  8 );
343+     bd_addr[5 ] = (uint8_t )((company_id & 0x00FF0000 ) >> 16 );
398344
399345    bd_found = true ;
400346  } else  {
@@ -448,13 +394,8 @@ HCISharedMemTransportClass::HCISharedMemTransportClass()
448394
449395  phase_bd_addr = false ;
450396  phase_tx_power = false ;
451-   phase_gatt_init = false ;
452-   phase_gap_init = false ;
453-   phase_random_addr = false ;
454-   phase_get_random_addr = false ;
455397  phase_reset = false ;
456398  phase_running = false ;
457-   is_random_addr_msg = false ;
458399}
459400
460401HCISharedMemTransportClass::~HCISharedMemTransportClass ()
@@ -517,13 +458,8 @@ void HCISharedMemTransportClass::end()
517458  /*  the HCI RESET command ready to be processed again */ 
518459  phase_bd_addr = false ;
519460  phase_tx_power = false ;
520-   phase_gatt_init = false ;
521-   phase_gap_init = false ;
522-   phase_random_addr = false ;
523-   phase_get_random_addr = false ;
524461  phase_reset = false ;
525462  phase_running = false ;
526-   is_random_addr_msg = false ;
527463}
528464
529465void  HCISharedMemTransportClass::wait (unsigned  long  timeout)
@@ -614,34 +550,11 @@ size_t HCISharedMemTransportClass::write(const uint8_t *data, size_t length)
614550    while  (!phase_bd_addr);
615551    /*  this sequence is now complete */ 
616552
617-     /*  set the random address */ 
618-     bt_ipm_set_random_addr ();
619-     /*  wait for the Rx complete */ 
620-     while  (!phase_random_addr);
621- 
622553    /*  set the Tx power */ 
623554    bt_ipm_set_power ();
624555    /*  wait for the Rx complete */ 
625556    while  (!phase_tx_power);
626557
627-     /*  gatt init */ 
628-     bt_ipm_gatt_init ();
629-     /*  wait for the Rx complete */ 
630-     while  (!phase_gatt_init);
631- 
632-     /*  gap init */ 
633-     bt_ipm_gap_init ();
634-     /*  wait for the Rx complete */ 
635-     while  (!phase_gap_init);
636- 
637-     /*  get the random address */ 
638-     bt_ipm_get_random_addr ();
639-     /*  wait for the Rx complete */ 
640-     while  (!phase_get_random_addr);
641- 
642-     /*  Now we can copy the random address and save it in the transport class */ 
643-     memcpy (_random_addr, helper_random_addr, 6 );
644- 
645558    /*  this sequence is now complete */ 
646559    phase_running = true ;
647560
@@ -831,43 +744,6 @@ int HCISharedMemTransportClass::bt_ipm_set_addr(void)
831744  return  0 ; /*  Error */ 
832745}
833746
834- int  HCISharedMemTransportClass::bt_ipm_set_random_addr (void )
835- {
836-   /*  the specific table for set addr is 8 bytes:
837-    * one byte for config_offset 
838-    * one byte for length 
839-    * 6 bytes for payload */  
840-   uint8_t  data[4  + 8 ];
841- 
842-   /* 
843-    * Static random Address 
844-    * The two upper bits shall be set to 1 
845-    * The lowest 32bits is read from the UDN to differentiate between devices 
846-    * The RNG may be used to provide a random number on each power on 
847-    */  
848-   uint32_t  srd_bd_addr[2 ];
849- 
850-   phase_random_addr = false ;
851- 
852-   srd_bd_addr[1 ] =  0x0000ED6E ;
853-   srd_bd_addr[0 ] =  LL_FLASH_GetUDN ( );
854- 
855-   data[0 ] = BT_BUF_CMD;
856-   data[1 ] = uint8_t (ACI_WRITE_CONFIG_DATA_OPCODE & 0x000000FF ); /*  OCF */ 
857-   data[2 ] = uint8_t ((ACI_WRITE_CONFIG_DATA_OPCODE & 0x0000FF00 ) >> 8 ); /*  OGF */ 
858-   data[3 ] = 8 ; /*  length of parameters */ 
859-   /*  fill the ACI_HAL_WRITE_CONFIG_DATA with the addr*/ 
860-   data[4 ] = 0x2E ; /*  the offset */ 
861-   data[5 ] = 6 ; /*  is the length of the random address */ 
862-   memcpy (data + 6 , srd_bd_addr, 6 );
863-   /*  send the ACI_HAL_WRITE_CONFIG_DATA */ 
864-   if  (mbox_write (data[0 ], 11 , &data[1 ]) != 11 ) {
865-     /*  Error: no data are written */ 
866-     return  0 ;
867-   }
868-   /*  now wait for the corresponding Rx event */ 
869-   return  1 ; /*  success */ 
870- }
871747
872748int  HCISharedMemTransportClass::bt_ipm_set_power (void )
873749{
@@ -894,78 +770,4 @@ int HCISharedMemTransportClass::bt_ipm_set_power(void)
894770  return  1 ; /*  success */ 
895771}
896772
897- int  HCISharedMemTransportClass::bt_ipm_gatt_init (void )
898- {
899-   /*  the specific table for gatt init */ 
900-   uint8_t  data[4 ];
901- 
902-   phase_gatt_init = false ;
903- 
904-   data[0 ] = BT_BUF_CMD; /*  the type */ 
905-   data[1 ] = 0x01 ; /*  the OPCODE */ 
906-   data[2 ] = 0xFD ;
907-   data[3 ] = 0 ; /*  the length */ 
908- 
909-   /*  send the GATT_INIT */ 
910-   if  (mbox_write (data[0 ], 3 , &data[1 ]) != 3 ) {
911-     /*  Error: no data are written */ 
912-     return  0 ;
913-   }
914-   /*  now wait for the corresponding Rx event */ 
915-   return  1 ; /*  success */ 
916- }
917- 
918- int  HCISharedMemTransportClass::bt_ipm_gap_init (void )
919- {
920-   /*  the specific table for gap init is 3 bytes:
921-    * Role byte, enable_privacy byte, device_name_char_len byte */  
922-   uint8_t  data[4  + 3 ];
923- 
924-   phase_gap_init = false ;
925- 
926-   data[0 ] = BT_BUF_CMD; /*  the type */ 
927-   data[1 ] = 0x8A ; /*  the OPCODE */ 
928-   data[2 ] = 0xFC ;
929-   data[3 ] = 3 ; /*  the length */ 
930-   /*  fill the GAP_INIT */ 
931-   data[4 ] = 0x0F ; /*  role */ 
932-   data[5 ] = 0x00 ; /*  enable_privacy */ 
933-   data[6 ] = 0x00 ; /*  device_name_char_len */ 
934- 
935-   /*  send the GAP_INIT */ 
936-   if  (mbox_write (data[0 ], 6 , &data[1 ]) != 6 ) {
937-     /*  Error: no data are written */ 
938-     return  0 ;
939-   }
940-   /*  now wait for the corresponding Rx event */ 
941-   return  1 ; /*  success */ 
942- }
943- 
944- int  HCISharedMemTransportClass::bt_ipm_get_random_addr (void )
945- {
946-   /*  the specific table for set addr is 8 bytes:
947-    * one byte for config_offset 
948-    * one byte for length 
949-    * 6 bytes for payload */  
950-   uint8_t  data[4  + 1 ];
951- 
952-   phase_get_random_addr = false ;
953- 
954-   /*  create ACI_READ_CONFIG_DATA_OPCODE */ 
955-   data[0 ] = BT_BUF_CMD;
956-   data[1 ] = uint8_t (ACI_READ_CONFIG_DATA_OPCODE & 0x000000FF ); /*  OCF */ 
957-   data[2 ] = uint8_t ((ACI_READ_CONFIG_DATA_OPCODE & 0x0000FF00 ) >> 8 ); /*  OGF */ 
958-   data[3 ] = 1 ; /*  length of parameters */ 
959-   /*  fill the ACI_READ_CONFIG_DATA_OPCODE with the offset*/ 
960-   data[4 ] = 0x2E ; /*  the offset */ 
961- 
962-   /*  send the ACI_READ_CONFIG_DATA_OPCODE */ 
963-   if  (mbox_write (data[0 ], 4 , &data[1 ]) != 4 ) {
964-     /*  Error: no data are written */ 
965-     return  0 ;
966-   }
967-   /*  now wait for the corresponding Rx event */ 
968-   return  1 ; /*  success */ 
969- }
970- 
971773#endif  /*  STM32WBxx */ 
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