diff --git a/arm/cortexm.py b/arm/cortexm.py
index a07003d2..5094698b 100644
--- a/arm/cortexm.py
+++ b/arm/cortexm.py
@@ -437,6 +437,123 @@ def __init__(self):
'src/s-textio__microbit.adb'])
+class NRF52(ArmV7MTarget):
+ @property
+ def name(self):
+ return 'nRF52'
+
+ @property
+ def parent(self):
+ return CortexMArch
+
+ @property
+ def loaders(self):
+ return ('ROM', )
+
+ @property
+ def has_fpu(self):
+ return True
+
+ @property
+ def system_ads(self):
+ # Use custom System package since system-xi-cortexm4 assumes
+ # 4-bit interrupt priorities, but the nRF52 only supports
+ # 3-bit interrupt priorities. This requires different
+ # definitions for Priority and Interrupt_Priority in System.
+ return {'zfp': 'system-xi-arm.ads',
+ 'ravenscar-sfp': 'arm/nordic/nrf52/system-xi-nrf52-sfp.ads',
+ 'ravenscar-full': 'arm/nordic/nrf52/system-xi-nrf52-full.ads'}
+
+ @property
+ def compiler_switches(self):
+ # The required compiler switches
+ return ('-mlittle-endian', '-mthumb', '-mhard-float',
+ '-mfpu=fpv4-sp-d16', '-mcpu=cortex-m4')
+
+ def __init__(self):
+ super(NRF52, self).__init__()
+
+ self.add_linker_script('arm/nordic/nrf52/common-ROM.ld', loader='ROM')
+
+ self.add_sources('crt0', [
+ 'arm/nordic/nrf52/s-bbmcpa.ads',
+ 'arm/nordic/nrf52/start-common.S',
+ 'arm/nordic/nrf52/start-rom.S',
+ 'arm/nordic/nrf52/setup_board.ads'])
+
+ self.add_sources('gnarl', [
+ 'src/s-bbpara__nrf52.ads',
+ 'src/s-bbbosu__nrf52.adb',
+ 'src/s-bcpcst__pendsv.adb'])
+
+
+class NRF52840(NRF52):
+ @property
+ def name(self):
+ return 'nrf52840'
+
+ @property
+ def use_semihosting_io(self):
+ return True
+
+ def __init__(self):
+ super(NRF52840, self).__init__()
+
+ self.add_linker_script('arm/nordic/nrf52/memory-map_nRF52840.ld',
+ loader='ROM')
+
+ self.add_sources('crt0', [
+ 'arm/nordic/nrf52/nrf52840/s-bbbopa.ads',
+ 'arm/nordic/nrf52/nrf52840/setup_board.adb',
+ 'arm/nordic/nrf52/nrf52840/svd/i-nrf52.ads',
+ 'arm/nordic/nrf52/nrf52840/svd/i-nrf52-ccm.ads',
+ 'arm/nordic/nrf52/nrf52840/svd/i-nrf52-clock.ads',
+ 'arm/nordic/nrf52/nrf52840/svd/i-nrf52-ficr.ads',
+ 'arm/nordic/nrf52/nrf52840/svd/i-nrf52-gpio.ads',
+ 'arm/nordic/nrf52/nrf52840/svd/i-nrf52-uicr.ads',
+ 'arm/nordic/nrf52/nrf52840/svd/i-nrf52-nvmc.ads',
+ 'arm/nordic/nrf52/nrf52840/svd/i-nrf52-rtc.ads',
+ 'arm/nordic/nrf52/nrf52840/svd/i-nrf52-temp.ads',
+ 'src/s-textio__null.adb'])
+
+ self.add_sources('gnarl', [
+ 'arm/nordic/nrf52/nrf52840/svd/handler.S',
+ 'arm/nordic/nrf52/nrf52840/svd/a-intnam.ads'])
+
+
+class NRF52832(NRF52):
+ @property
+ def name(self):
+ return 'nrf52832'
+
+ @property
+ def use_semihosting_io(self):
+ return True
+
+ def __init__(self):
+ super(NRF52832, self).__init__()
+
+ self.add_linker_script('arm/nordic/nrf52/memory-map_nRF52832.ld',
+ loader='ROM')
+
+ self.add_sources('crt0', [
+ 'arm/nordic/nrf52/nrf52832/s-bbbopa.ads',
+ 'arm/nordic/nrf52/nrf52832/setup_board.adb',
+ 'arm/nordic/nrf52/nrf52832/svd/i-nrf52.ads',
+ 'arm/nordic/nrf52/nrf52832/svd/i-nrf52-clock.ads',
+ 'arm/nordic/nrf52/nrf52832/svd/i-nrf52-ficr.ads',
+ 'arm/nordic/nrf52/nrf52832/svd/i-nrf52-gpio.ads',
+ 'arm/nordic/nrf52/nrf52832/svd/i-nrf52-uicr.ads',
+ 'arm/nordic/nrf52/nrf52832/svd/i-nrf52-nvmc.ads',
+ 'arm/nordic/nrf52/nrf52832/svd/i-nrf52-rtc.ads',
+ 'arm/nordic/nrf52/nrf52832/svd/i-nrf52-temp.ads',
+ 'src/s-textio__null.adb'])
+
+ self.add_sources('gnarl', [
+ 'arm/nordic/nrf52/nrf52832/svd/handler.S',
+ 'arm/nordic/nrf52/nrf52832/svd/a-intnam.ads'])
+
+
class Stm32CommonArchSupport(ArchSupport):
"""Holds sources common to all stm32 boards"""
@property
diff --git a/arm/nordic/nrf52/README b/arm/nordic/nrf52/README
new file mode 100644
index 00000000..8da144e5
--- /dev/null
+++ b/arm/nordic/nrf52/README
@@ -0,0 +1,138 @@
+Nordic nRF52 Runtimes
+=====================
+
+Runtimes Supported
+------------------
+
+* ZFP
+* Ravenscar-SFP
+* Ravenscar-Full
+
+Targets Supported
+-----------------
+
+Cortex-M4F CPUs:
+* nRF52832
+* nRF52840
+
+Interrupts
+----------
+
+The package Ada.Interrupts.Names (a-intnam.ads) is located in the gnat
+directory. This package spec was automatically generated from an SVD file so
+you will not need to change it unless an SVD file was unavailable for your
+target.
+
+See package System.BB.MCU_Parameters (s-bbmcpa.ads) for the number of
+interrupts defined. That number must reflect the contents of the
+SVD-generated package Ada.Interrupts.Names.
+
+Resources Used
+--------------
+
+The Ravenscar runtime uses the RTC0 peripheral to implement Ada semantics for
+time, i.e., delay statements and the package Ada.Real_Time. The RTC0 interrupt
+runs at the highest priority. RTC0 runs from the low frequency clock (LFCLK)
+which runs at 32.768 kHz. The LFCLK source is configured in the Setup_Board
+procedure (setup_board.adb), and may be either the external 32 kHz crystal
+oscillator (LFXO), the internal 32 kHz oscillator (LFRC), or synthesized from
+the 16 MHz high-speed clock (HFCLK).
+
+The other RTC peripherals (RTC1 and RTC2) are available for user applications.
+
+Tick-less Scheduler
+-------------------
+
+The RTC0 peripheral is used to implement a "tick-less" version of Ada.Real_Time
+which does not rely on periodic interrupts at a constant rate (e.g. 1 kHz).
+Instead, the "compare" feature of the RTC peripheral is used to generate an
+interrupt at the precise point in time when the scheduler needs to wake up at
+the end of a delay.
+
+Rationale
+,,,,,,,,,
+
+The primary rationale for this tick-less approach is to support ultra-low power
+applications that can operate for years on batteries. To do this, the CPU must
+be allowed to remain in a low-power sleep as much as possible, avoiding
+excessive wake-ups due to unnecessary interrupts. The target baseline average
+MCU current consumption for this runtime is 10 µA (assuming only the RTC0
+peripheral is active and the HFCLK is disabled). This would allow the MCU to
+theoretically run for over a year on a single CR2032 coin cell battery.
+
+This low-power requirement eliminated the possibility of using the SysTick
+timer for the following reasons:
+1. The SysTick timer ticks at (usually) 1 kHz, which results in a lot of
+ unnecessary CPU wake-ups during long task delays.
+2. It was discovered on a nRF52840 PDK board that the power management on the
+ nRF52 powers down the entire CPU - including the SysTick - when the CPU
+ enters WFI sleep. This results in the SysTick pausing when the CPU sleeps,
+ making it useless as a time source while the CPU is sleeping.
+3. The SysTick (and any other high-resolution timer peripherals) requires the
+ high-frequency clock (HFCLK) to be active, which has a relatively high
+ current draw of approximately 200 µA, which exceeds my target current draw
+ by an order of magnitude.
+
+The solution is therefore to use the RTC0 timer, using the 32.768 kHz
+LFCLK, which allows the CPU and HFCLK domain to be powered off during WFI sleep
+while keeping task delays alive.
+
+Implementation
+,,,,,,,,,,,,,,
+The existing Ravenscar scheduler is very well designed and can already support
+a tick-less implementation without changes. The only work needed to implement a
+tick-less scheduler was to implement the alarm handler System.BB.Board_Support
+package in a way that avoids a periodic interrupt.
+
+The RTC is a 24-bit counter, which overflows every 512 seconds when operating
+at 32.768 kHz. The RTC also has a "compare" feature which allows an interrupt
+to be generated then the RTC counter reaches a configurable 24-bit value. This
+compare feature is what is used to implement the tick-less alarm.
+
+Read_Clock just needs to read and return the current value of the RTC's 24-bit
+counter. This provides a high-resolution time base that ticks every 30.518 µs.
+
+When Set_Alarm is called, it sets the RTC compare value to the specified alarm
+time. The alarm time is guaranteed to be a 24-bit value since the existing
+runtime ensures the provided alarm time does not exceed the value returned by
+the Max_Timer_Interval function, which in this runtime for the nRF52 returns
+2**24 - 1.
+
+Once the alarm time is set, a single interrupt will be generated at the
+specified alarm time, which wakes up the scheduler and unblocks the delayed
+task. This results in task delays that are much more accurate than
+SysTick-based runtimes, since the alarm interrupt is triggered at the exact
+alarm time. The resolution of the alarm is 1 timer tick, which is 30.518 µs.
+
+The runtime already guarantees that an alarm will be set at least once every
+Max_Timer_Interval to keep the scheduler alive during long periods of sleep.
+This will result in unnecessary alarm interrupts during very long periods of
+sleep, but since the RTC overflows very slowly - every 512 seconds
+(8.5 minutes) - these will occur very infrequently. The RTC uses a
+"safety factor" of 7/8 of the Max_Timer_Interval, resulting in one unnecessary
+interrupt every 448 seconds (7.5 minutes) which is perfectly acceptable since
+the CPU is only awake for a very short time before sleeping again.
+
+Considerations for Ada RM 3.8 (30)
+,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,
+
+The runtime in this repository derives the resolution of
+Ada.Real_Time.Time_Unit directly from the clock source (specified in
+System.BB.Board_Parameters). The other runtimes in this repository specify
+their main clock speed (e.g. 64 MHz), so Time_Unit is very fine. This runtime,
+however, uses a 32.768 kHz clock source which would result in a much more
+coarse Time_Unit.
+
+Ada RM Annex D.8 "Monotonic Time" item 30 states: "Time_Unit shall be less than
+or equal to 20 microseconds". A Time_Unit derived from a 32.768 kHz clock
+source would violate this requirement, as it would have Time_Unit of 30.518 µs.
+
+To ensure that the requirement in ARM D.8 (30 is met, the package spec for
+System.BB.Board_Support deals in units that are scaled up in multiples of
+32.768 kHz, and is the unit exposed to the rest of the runtime (including
+Ada.Real_Time). The Board_Support package body divides these scaled-up units
+back down to 32.768 kHz when interacting with the RTC. This scaling factor is
+configured in the constant: System.BB.Board_Parameters.RTC_Tick_Scaling_Factor.
+This value is currently set to 32, so that Time_Unit has a resolution of
+1 / (32.768 kHz * 32) = 0.954 µs, which satisfies ARM D.8 (30).
+
diff --git a/arm/nordic/nrf52/common-ROM.ld b/arm/nordic/nrf52/common-ROM.ld
new file mode 100644
index 00000000..b9af7a77
--- /dev/null
+++ b/arm/nordic/nrf52/common-ROM.ld
@@ -0,0 +1,139 @@
+/****************************************************************************
+ * *
+ * GNAT COMPILER COMPONENTS *
+ * *
+ * A R M *
+ * *
+ * Linker Script File *
+ * *
+ * Copyright (C) 1999-2002 Universidad Politecnica de Madrid *
+ * Copyright (C) 2003-2006 The European Space Agency *
+ * Copyright (C) 2003-2019 AdaCore *
+ * *
+ * GNAT is free software; you can redistribute it and/or modify it under *
+ * terms of the GNU General Public License as published by the Free Soft- *
+ * ware Foundation; either version 2, or (at your option) any later ver- *
+ * sion. GNAT is distributed in the hope that it will be useful, but WITH- *
+ * OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY *
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License *
+ * for more details. You should have received a copy of the GNU General *
+ * Public License distributed with GNAT; see file COPYING. If not, write *
+ * to the Free Software Foundation, 51 Franklin Street, Fifth Floor, *
+ * Boston, MA 02110-1301, USA. *
+ * *
+ * As a special exception, if you link this file with other files to *
+ * produce an executable, this file does not by itself cause the resulting *
+ * executable to be covered by the GNU General Public License. This except- *
+ * ion does not however invalidate any other reasons why the executable *
+ * file might be covered by the GNU Public License. *
+ * *
+ * GNARL was developed by the GNARL team at Florida State University. *
+ * Extensive contributions were provided by Ada Core Technologies, Inc. *
+ * The executive was developed by the Real-Time Systems Group at the *
+ * Technical University of Madrid. *
+ * *
+ ****************************************************************************/
+
+/* This is a ARM specific version of this file */
+
+/* This script replaces ld's default linker script, providing the
+ appropriate memory map and output format. */
+
+SEARCH_DIR(.)
+__DYNAMIC = 0;
+
+_DEFAULT_STACK_SIZE = 4*1024;
+
+ENTRY(_start_rom);
+
+SECTIONS
+{
+ .text :
+ {
+ KEEP (*(.vectors))
+ *(.text .text.* .gnu.linkonce.t*)
+ *(.gnu.warning)
+ } > flash
+
+ .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > flash
+ PROVIDE_HIDDEN (__exidx_start = .);
+ .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > flash
+ PROVIDE_HIDDEN (__exidx_end = .);
+
+ .rodata :
+ {
+ *(.lit)
+ *(.rodata .rodata.* .gnu.linkonce.r*)
+ . = ALIGN(0x4);
+ __rom_end = .;
+ } > flash
+
+ __data_load = __rom_end;
+ .data : AT (__data_load)
+ {
+ __data_start = .;
+ *(.data .data.* .gnu.linkonce.d*)
+
+ /* Ensure that the end of the data section is always word aligned.
+ Initial values are stored in 4-bytes blocks so we must guarantee
+ that these blocks do not fall out the section (otherwise they are
+ truncated and the initial data for the last block are lost). */
+
+ . = ALIGN(0x4);
+ __data_end = .;
+ } > sram_da
+ __data_words = (__data_end - __data_start) >> 2;
+
+ .bss (NOLOAD): {
+ . = ALIGN(0x8);
+ __bss_start = .;
+
+ *(.bss .bss.*)
+ *(COMMON)
+
+ . = ALIGN(0x8); /* Align the stack to 64 bits */
+ __bss_end = .;
+
+ __interrupt_stack_start = .;
+ *(.interrupt_stacks)
+ . = ALIGN(0x8);
+ __interrupt_stack_end = .;
+
+ __stack_start = .;
+ . += DEFINED (__stack_size) ? __stack_size : _DEFAULT_STACK_SIZE;
+ . = ALIGN(0x8);
+ __stack_end = .;
+
+ _end = .;
+ __heap_start = .;
+ __heap_end = ORIGIN(sram_bs) + LENGTH(sram_bs);
+ } > sram_bs
+
+ __bss_words = (__bss_end - __bss_start) >> 2;
+
+ /* DWARF debug sections.
+ Symbols in the DWARF debugging sections are relative to the beginning
+ of the section so we begin them at 0. */
+ /* DWARF 1 */
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+ /* GNU DWARF 1 extensions */
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+ /* DWARF 1.1 and DWARF 2 */
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ /* DWARF 2 */
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+ /* DWARF 3 */
+ .debug_pubtypes 0 : { *(.debug_pubtypes) }
+ .debug_ranges 0 : { *(.debug_ranges) }
+ .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) }
+ /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) }
+}
diff --git a/arm/nordic/nrf52/memory-map_nRF52832.ld b/arm/nordic/nrf52/memory-map_nRF52832.ld
new file mode 100644
index 00000000..df128174
--- /dev/null
+++ b/arm/nordic/nrf52/memory-map_nRF52832.ld
@@ -0,0 +1,47 @@
+/****************************************************************************
+ * *
+ * GNAT COMPILER COMPONENTS *
+ * *
+ * A R M *
+ * *
+ * Linker Script File *
+ * *
+ * Copyright (C) 1999-2002 Universidad Politecnica de Madrid *
+ * Copyright (C) 2003-2006 The European Space Agency *
+ * Copyright (C) 2003-2019 AdaCore *
+ * *
+ * GNAT is free software; you can redistribute it and/or modify it under *
+ * terms of the GNU General Public License as published by the Free Soft- *
+ * ware Foundation; either version 2, or (at your option) any later ver- *
+ * sion. GNAT is distributed in the hope that it will be useful, but WITH- *
+ * OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY *
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License *
+ * for more details. You should have received a copy of the GNU General *
+ * Public License distributed with GNAT; see file COPYING. If not, write *
+ * to the Free Software Foundation, 51 Franklin Street, Fifth Floor, *
+ * Boston, MA 02110-1301, USA. *
+ * *
+ * As a special exception, if you link this file with other files to *
+ * produce an executable, this file does not by itself cause the resulting *
+ * executable to be covered by the GNU General Public License. This except- *
+ * ion does not however invalidate any other reasons why the executable *
+ * file might be covered by the GNU Public License. *
+ * *
+ * GNARL was developed by the GNARL team at Florida State University. *
+ * Extensive contributions were provided by Ada Core Technologies, Inc. *
+ * The executive was developed by the Real-Time Systems Group at the *
+ * Technical University of Madrid. *
+ * *
+ ****************************************************************************/
+
+MEMORY
+{
+ flash (rx) : ORIGIN = 0x00000000, LENGTH = 512K
+ sram12 (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+}
+
+/* Do not place anything into the dtcm as it is used as Data cache by the CPU*/
+REGION_ALIAS("sram_tx", sram12)
+REGION_ALIAS("sram_ro", sram12)
+REGION_ALIAS("sram_bs", sram12)
+REGION_ALIAS("sram_da", sram12)
diff --git a/arm/nordic/nrf52/memory-map_nRF52840.ld b/arm/nordic/nrf52/memory-map_nRF52840.ld
new file mode 100644
index 00000000..3e1234db
--- /dev/null
+++ b/arm/nordic/nrf52/memory-map_nRF52840.ld
@@ -0,0 +1,47 @@
+/****************************************************************************
+ * *
+ * GNAT COMPILER COMPONENTS *
+ * *
+ * A R M *
+ * *
+ * Linker Script File *
+ * *
+ * Copyright (C) 1999-2002 Universidad Politecnica de Madrid *
+ * Copyright (C) 2003-2006 The European Space Agency *
+ * Copyright (C) 2003-2019 AdaCore *
+ * *
+ * GNAT is free software; you can redistribute it and/or modify it under *
+ * terms of the GNU General Public License as published by the Free Soft- *
+ * ware Foundation; either version 2, or (at your option) any later ver- *
+ * sion. GNAT is distributed in the hope that it will be useful, but WITH- *
+ * OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY *
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License *
+ * for more details. You should have received a copy of the GNU General *
+ * Public License distributed with GNAT; see file COPYING. If not, write *
+ * to the Free Software Foundation, 51 Franklin Street, Fifth Floor, *
+ * Boston, MA 02110-1301, USA. *
+ * *
+ * As a special exception, if you link this file with other files to *
+ * produce an executable, this file does not by itself cause the resulting *
+ * executable to be covered by the GNU General Public License. This except- *
+ * ion does not however invalidate any other reasons why the executable *
+ * file might be covered by the GNU Public License. *
+ * *
+ * GNARL was developed by the GNARL team at Florida State University. *
+ * Extensive contributions were provided by Ada Core Technologies, Inc. *
+ * The executive was developed by the Real-Time Systems Group at the *
+ * Technical University of Madrid. *
+ * *
+ ****************************************************************************/
+
+MEMORY
+{
+ flash (rx) : ORIGIN = 0x00000000, LENGTH = 1024K
+ sram12 (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+/* Do not place anything into the dtcm as it is used as Data cache by the CPU*/
+REGION_ALIAS("sram_tx", sram12)
+REGION_ALIAS("sram_ro", sram12)
+REGION_ALIAS("sram_bs", sram12)
+REGION_ALIAS("sram_da", sram12)
diff --git a/arm/nordic/nrf52/nrf52832/s-bbbopa.ads b/arm/nordic/nrf52/nrf52832/s-bbbopa.ads
new file mode 100644
index 00000000..12552d09
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52832/s-bbbopa.ads
@@ -0,0 +1,67 @@
+------------------------------------------------------------------------------
+-- --
+-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS --
+-- --
+-- S Y S T E M . B B . B O A R D _ P A R A M E T E R S --
+-- --
+-- S p e c --
+-- --
+-- Copyright (C) 2016-2019, AdaCore --
+-- --
+-- GNAT is free software; you can redistribute it and/or modify it under --
+-- terms of the GNU General Public License as published by the Free Soft- --
+-- ware Foundation; either version 3, or (at your option) any later ver- --
+-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
+-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
+-- or FITNESS FOR A PARTICULAR PURPOSE. --
+-- --
+-- As a special exception under Section 7 of GPL version 3, you are granted --
+-- additional permissions described in the GCC Runtime Library Exception, --
+-- version 3.1, as published by the Free Software Foundation. --
+-- --
+-- You should have received a copy of the GNU General Public License and --
+-- a copy of the GCC Runtime Library Exception along with this program; --
+-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
+-- . --
+-- --
+-- GNAT was originally developed by the GNAT team at New York University. --
+-- Extensive contributions were provided by Ada Core Technologies Inc. --
+-- --
+-- The port of GNARL to bare board targets was initially developed by the --
+-- Real-Time Systems Group at the Technical University of Madrid. --
+-- --
+------------------------------------------------------------------------------
+
+-- This package defines board parameters for the nRF52840-DK board
+
+package System.BB.Board_Parameters is
+ pragma No_Elaboration_Code_All;
+ pragma Pure;
+
+ --------------------
+ -- Hardware clock --
+ --------------------
+
+ RTC_Tick_Scaling_Factor : constant := 32; -- 32.768 kHz * 32 = 1.048576 MHz
+ -- Use a fairly high scaling factor so that Ada.Real_Time.Time_Unit is
+ -- at least 1 microsecond. This improves the long-running accuracy of
+ -- periodic tasks where the period is not integer divisible by 32.768 kHz.
+ --
+ -- The maximum permitted scaling factor is 255, otherwise the 24-bit RTC
+ -- period (@ 32 kHz) cannot be scaled to the 32-bit range of
+ -- Timer_Interval.
+
+ Main_Clock_Frequency : constant := 32_768 * RTC_Tick_Scaling_Factor;
+ -- On the nRF52 we use the RTC peripheral as the system tick, instead of
+ -- the Cortex-M4 SysTick because the SysTick is powered down when the CPU
+ -- enters sleep mode (via the "wfi" instruction). Since we still want to
+ -- be able to put the CPU to sleep (to save power) we instead use the
+ -- low-power RTC peripheral, which runs at 32.768 kHz.
+ --
+ -- In this runtime, the minimum allowed frequency is 50_000 Hz so that
+ -- Ada.Real_Time.Time_Unit does not exceed 20 µs as required by
+ -- Ada RM D.8 (30). Since the RTC's actual period is 30.518 µs we multiply
+ -- the RTC frequency by RTC_Tick_Scaling_Factor so that Time_Unit meets the
+ -- requirement in Ada RM D.8 (30).
+
+end System.BB.Board_Parameters;
diff --git a/arm/nordic/nrf52/nrf52832/setup_board.adb b/arm/nordic/nrf52/nrf52832/setup_board.adb
new file mode 100644
index 00000000..6b177067
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52832/setup_board.adb
@@ -0,0 +1,396 @@
+------------------------------------------------------------------------------
+-- --
+-- GNAT RUN-TIME COMPONENTS --
+-- --
+-- Copyright (C) 2012-2019, Free Software Foundation, Inc. --
+-- --
+-- GNAT is free software; you can redistribute it and/or modify it under --
+-- terms of the GNU General Public License as published by the Free Soft- --
+-- ware Foundation; either version 3, or (at your option) any later ver- --
+-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
+-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
+-- or FITNESS FOR A PARTICULAR PURPOSE. --
+-- --
+-- As a special exception under Section 7 of GPL version 3, you are granted --
+-- additional permissions described in the GCC Runtime Library Exception, --
+-- version 3.1, as published by the Free Software Foundation. --
+-- --
+-- You should have received a copy of the GNU General Public License and --
+-- a copy of the GCC Runtime Library Exception along with this program; --
+-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
+-- . --
+-- --
+-- GNAT was originally developed by the GNAT team at New York University. --
+-- Extensive contributions were provided by Ada Core Technologies Inc. --
+-- --
+------------------------------------------------------------------------------
+
+-- This file is based on the startup code from the following file in Nordic's
+-- nRF5 SDK (version 15.1.0): modules/nrfx/mdk/system_nrf52.c for errata
+-- workarounds and configuration of the SWD pins and reset pin.
+--
+-- This Errata_X functions detect if certain errata are applicable for the
+-- MCU. If they are applicable, then a workaround is applied for the errata.
+-- Some of these errata workarounds rely on reading and/or writing registers
+-- that are not documented in the datasheet. As mentioned above, these
+-- register addresses and values are copied from Nordic's nRF5 SDK.
+
+pragma Ada_2012; -- To work around pre-commit check?
+pragma Suppress (All_Checks);
+
+with System;
+with System.Machine_Code; use System.Machine_Code;
+
+with Interfaces; use Interfaces;
+with Interfaces.NRF52; use Interfaces.NRF52;
+with Interfaces.NRF52.CLOCK; use Interfaces.NRF52.CLOCK;
+with Interfaces.NRF52.FICR; use Interfaces.NRF52.FICR;
+with Interfaces.NRF52.GPIO; use Interfaces.NRF52.GPIO;
+with Interfaces.NRF52.NVMC; use Interfaces.NRF52.NVMC;
+with Interfaces.NRF52.UICR; use Interfaces.NRF52.UICR;
+with Interfaces.NRF52.TEMP; use Interfaces.NRF52.TEMP;
+
+procedure Setup_Board is
+
+ ---------------------------
+ -- Board Configuration --
+ ---------------------------
+
+ Use_HFXO : constant Boolean := False;
+ -- Set to True to use the high-frequency external oscillator (HFXO).
+ -- When False, the on-chip oscillator is used.
+ -- The HFXO can also be turned on and off later by the main program.
+
+ LFCLK_Source : constant LFCLKSRC_SRC_Field := Xtal;
+ -- Selects the source for the LFCLK.
+ -- Xtal selects the external 32.768 kHz crystal (LFXO).
+ -- Rc selects the internal 32.768 kHz RC oscillator.
+ -- Synth selects the LFCLK synthesized from the 16 MHz HFCLK.
+
+ Use_SWO_Trace : constant Boolean := True;
+ -- Set to True to enable the SWO trace pins.
+
+ Use_Reset_Pin : constant Boolean := True;
+ -- When True, P0.18 will be configured as the reset pin.
+
+ --------------------------
+ -- Errata Workarounds --
+ --------------------------
+
+ -- Some of these registers are not documented in the Objective Product Spec
+ -- but they are used in the nRF5 SDK startup code to detect when
+ -- certain errata are applicable.
+
+ Undocumented_Reg_1 : UInt32
+ with Address => System'To_Address (16#F000_0FE0#);
+
+ Undocumented_Reg_2 : UInt32
+ with Address => System'To_Address (16#F000_0FE4#);
+
+ Undocumented_Reg_3 : UInt32
+ with Address => System'To_Address (16#F000_0FE8#);
+
+ Undocumented_Reg_4 : UInt32
+ with Address => System'To_Address (16#1000_0130#);
+
+ Undocumented_Reg_5 : UInt32
+ with Address => System'To_Address (16#1000_0134#);
+
+ -- Undocumented registers used for the workaround of erratas 12, 16
+ Errata_12_Reg_1 : UInt32
+ with Volatile, Address => System'To_Address (16#4001_3540#);
+ Errata_12_Reg_2 : UInt32
+ with Volatile, Address => System'To_Address (16#1000_0324#);
+ Errata_16_Reg : UInt32
+ with Volatile, Address => System'To_Address (16#4007_C074#);
+ Errata_31_Reg_1 : UInt32
+ with Volatile, Address => System'To_Address (16#4000_053C#);
+ Errata_31_Reg_2 : UInt32
+ with Volatile, Address => System'To_Address (16#1000_0244#);
+ Errata_37_Reg : UInt32
+ with Volatile, Address => System'To_Address (16#4000_05A0#);
+ Errata_57_Reg_1 : UInt32
+ with Volatile, Address => System'To_Address (16#4000_5610#);
+ Errata_57_Reg_2 : UInt32
+ with Volatile, Address => System'To_Address (16#4000_5688#);
+ Errata_57_Reg_3 : UInt32
+ with Volatile, Address => System'To_Address (16#4000_5618#);
+ Errata_57_Reg_4 : UInt32
+ with Volatile, Address => System'To_Address (16#4000_5614#);
+ Errata_108_Reg_1 : UInt32
+ with Volatile, Address => System'To_Address (16#4000_0EE4#);
+ Errata_108_Reg_2 : UInt32
+ with Volatile, Address => System'To_Address (16#1000_0258#);
+ Errata_182_Reg : UInt32
+ with Volatile, Address => System'To_Address (16#4000_173C#);
+
+ CoreDebug_DEMCR : UInt32
+ with Volatile, Address => System'To_Address (16#E000_EDFC#);
+
+ DEMCR_TRCENA_Mask : constant UInt32 := 16#0100_0000#;
+
+ -- The POWER.RESETREAS register.
+ -- We define this here instead of including Interfaces.POWER as a
+ -- workaround for a warning about unused bits in the definition
+ -- of RAM_Cluster in the auto-generated code.
+ POWER_RESETREAS : UInt32
+ with Volatile, Address => System'To_Address (16#4000_0400#);
+
+ -- The following functions detect if different errata are applicable on
+ -- the specific MCU revision. For example, Errata_12 checks if a errata #12
+ -- is applicable ("COMP: Reference ladder not correctly calibrated").
+
+ function Errata_12 return Boolean is
+ (((Undocumented_Reg_1 and 16#FF#) = 6)
+ and ((Undocumented_Reg_2 and 16#F#) = 0)
+ and ((Undocumented_Reg_3 and 16#F0#) in 16#30# | 16#40# | 16#50#))
+ with Inline_Always;
+
+ function Errata_16 return Boolean is
+ (((Undocumented_Reg_1 and 16#FF#) = 6)
+ and ((Undocumented_Reg_2 and 16#F#) = 0)
+ and ((Undocumented_Reg_3 and 16#F0#) = 16#30#))
+ with Inline_Always;
+
+ function Errata_31 return Boolean is
+ (((Undocumented_Reg_1 and 16#FF#) = 6)
+ and ((Undocumented_Reg_2 and 16#F#) = 0)
+ and ((Undocumented_Reg_3 and 16#F0#) in 16#30# | 16#40# | 16#50#))
+ with Inline_Always;
+
+ function Errata_32 return Boolean is
+ (((Undocumented_Reg_1 and 16#FF#) = 6)
+ and ((Undocumented_Reg_2 and 16#F#) = 0)
+ and ((Undocumented_Reg_3 and 16#F0#) = 16#30#))
+ with Inline_Always;
+
+ function Errata_36 return Boolean is
+ (((Undocumented_Reg_1 and 16#FF#) = 6)
+ and ((Undocumented_Reg_2 and 16#F#) = 0)
+ and ((Undocumented_Reg_3 and 16#F0#) in 16#30# | 16#40# | 16#50#))
+ with Inline_Always;
+
+ function Errata_37 return Boolean is
+ (((Undocumented_Reg_1 and 16#FF#) = 6)
+ and ((Undocumented_Reg_2 and 16#F#) = 0)
+ and ((Undocumented_Reg_3 and 16#F0#) = 16#30#))
+ with Inline_Always;
+
+ function Errata_57 return Boolean is
+ (((Undocumented_Reg_1 and 16#FF#) = 6)
+ and ((Undocumented_Reg_2 and 16#F#) = 0)
+ and ((Undocumented_Reg_3 and 16#F0#) = 16#30#))
+ with Inline_Always;
+
+ function Errata_66 return Boolean is
+ (((Undocumented_Reg_1 and 16#FF#) = 6)
+ and ((Undocumented_Reg_2 and 16#F#) = 0)
+ and ((Undocumented_Reg_3 and 16#F0#) = 16#50#))
+ with Inline_Always;
+
+ function Errata_108 return Boolean is
+ (((Undocumented_Reg_1 and 16#FF#) = 6)
+ and ((Undocumented_Reg_2 and 16#F#) = 0)
+ and ((Undocumented_Reg_3 and 16#F0#) in 16#30# | 16#40# | 16#50#))
+ with Inline_Always;
+
+ function Errata_136 return Boolean is
+ (((Undocumented_Reg_1 and 16#FF#) = 6)
+ and ((Undocumented_Reg_2 and 16#F#) = 0)
+ and ((Undocumented_Reg_3 and 16#F0#) in 16#30# | 16#40# | 16#50#))
+ with Inline_Always;
+
+ function Errata_182 return Boolean is
+ (Undocumented_Reg_4 = 6 and Undocumented_Reg_5 = 6)
+ with Inline_Always;
+
+ procedure NVIC_SystemReset;
+
+ procedure NVIC_SystemReset is
+ SCB_AIRCR : UInt32
+ with Volatile, Address => System'To_Address (16#E000_ED0C#);
+
+ VECTKEY : constant UInt32 := 16#05FA_0000#;
+
+ PRIGROUP_Mask : constant UInt32 := 16#0000_0700#;
+
+ SYSRESETREQ : constant UInt32 := 16#0000_0004#;
+
+ begin
+ -- Ensure all outstanding memory accesses including buffered write
+ -- are completed before reset
+ Asm ("dsb", Volatile => True);
+
+ SCB_AIRCR := VECTKEY or (SCB_AIRCR and PRIGROUP_Mask) or SYSRESETREQ;
+
+ Asm ("dsb", Volatile => True);
+
+ loop
+ null;
+ end loop;
+ end NVIC_SystemReset;
+
+begin
+
+ -- Enable SWO trace pins
+ if Use_SWO_Trace then
+ CoreDebug_DEMCR := CoreDebug_DEMCR or DEMCR_TRCENA_Mask;
+ CLOCK_Periph.TRACECONFIG.TRACEMUX := Serial;
+ P0_Periph.PIN_CNF (18) := PIN_CNF_Register'
+ (DIR => Output,
+ INPUT => Connect,
+ PULL => Disabled,
+ Reserved_4_7 => 0,
+ DRIVE => H0H1,
+ Reserved_11_15 => 0,
+ SENSE => Disabled,
+ Reserved_18_31 => 0);
+ end if;
+
+ -- Workaround for Errata 12 "COMP: Reference ladder not correctly
+ -- calibrated"
+ if Errata_12 then
+ Errata_12_Reg_1 := Shift_Right (Errata_12_Reg_2 and 16#1F00#, 8);
+ end if;
+
+ -- Workaround for Errata 16 "System: RAM may be corrupt on wakeup from
+ -- CPU IDLE"
+ if Errata_16 then
+ Errata_16_Reg := 3131961357;
+ end if;
+
+ -- Workaround for Errata 31 "CLOCK: Calibration values are not correctly
+ -- loaded from FICR at reset"
+ if Errata_31 then
+ Errata_31_Reg_1 := Shift_Right (Errata_31_Reg_2 and 16#E000#, 13);
+ end if;
+
+ -- Workaround for Errata 32 "DIF: Debug session automatically enables
+ -- TracePort pins"
+ if Errata_32 then
+ CoreDebug_DEMCR := CoreDebug_DEMCR and (not DEMCR_TRCENA_Mask);
+ end if;
+
+ -- Workaround for Errata 36 "CLOCK: Some registers are not reset when
+ -- expected"
+ if Errata_36 then
+ CLOCK_Periph.EVENTS_DONE := (EVENTS_DONE => 0, others => <>);
+ CLOCK_Periph.EVENTS_CTTO := (EVENTS_CTTO => 0, others => <>);
+ CLOCK_Periph.CTIV := (CTIV => 0, Reserved_7_31 => 0);
+ end if;
+
+ -- Workaround for Errata 37 "RADIO: Encryption engine is slow by default"
+ if Errata_37 then
+ Errata_37_Reg := 3;
+ end if;
+
+ -- Workaround for Errata 57 "NFCT: NFC Modulation amplitude"
+ if Errata_57 then
+ Errata_57_Reg_1 := 16#0000_0005#;
+ Errata_57_Reg_2 := 16#0000_0001#;
+ Errata_57_Reg_3 := 16#0000_0000#;
+ Errata_57_Reg_4 := 16#0000_003F#;
+ end if;
+
+ -- Workaround for Errata 66 "TEMP: Linearity specification not met with
+ -- default settings"
+ if Errata_66 then
+ TEMP_Periph.A0.A0 := FICR_Periph.TEMP.A0.A;
+ TEMP_Periph.A1.A1 := FICR_Periph.TEMP.A1.A;
+ TEMP_Periph.A2.A2 := FICR_Periph.TEMP.A2.A;
+ TEMP_Periph.A3.A3 := FICR_Periph.TEMP.A3.A;
+ TEMP_Periph.A4.A4 := FICR_Periph.TEMP.A4.A;
+ TEMP_Periph.A5.A5 := FICR_Periph.TEMP.A5.A;
+ TEMP_Periph.B0.B0 := FICR_Periph.TEMP.B0.B;
+ TEMP_Periph.B1.B1 := FICR_Periph.TEMP.B1.B;
+ TEMP_Periph.B2.B2 := FICR_Periph.TEMP.B2.B;
+ TEMP_Periph.B3.B3 := FICR_Periph.TEMP.B3.B;
+ TEMP_Periph.B4.B4 := FICR_Periph.TEMP.B4.B;
+ TEMP_Periph.B5.B5 := FICR_Periph.TEMP.B5.B;
+ TEMP_Periph.T0.T0 := FICR_Periph.TEMP.T0.T;
+ TEMP_Periph.T1.T1 := FICR_Periph.TEMP.T1.T;
+ TEMP_Periph.T2.T2 := FICR_Periph.TEMP.T2.T;
+ TEMP_Periph.T3.T3 := FICR_Periph.TEMP.T3.T;
+ TEMP_Periph.T4.T4 := FICR_Periph.TEMP.T4.T;
+ end if;
+
+ -- Workaround for Errata 108 "RAM: RAM content cannot be trusted upon
+ -- waking up from System ON Idle or System OFF mode"
+ if Errata_108 then
+ Errata_108_Reg_1 := Errata_108_Reg_2 and 16#0000_004F#;
+ end if;
+
+ -- Workaround for Errata 136 "System: Bits in RESETREAS are set when they
+ -- should not be"
+ if Errata_136 then
+ -- Clear all flags except RESETPIN if RESETPIN is the reset reason
+ if (POWER_RESETREAS and 16#0000_0001#) /= 0 then
+ POWER_RESETREAS := 16#FFFF_FFFE#;
+ end if;
+ end if;
+
+ -- Workaround for Errata 182 "RADIO: Fixes for anomalies #102, #106, and
+ -- #107 do not take effect"
+ if Errata_182 then
+ Errata_182_Reg := Errata_182_Reg or 16#200#;
+ end if;
+
+ if Use_Reset_Pin then
+ -- Enable nRESET pin on P0.18
+ if UICR_Periph.PSELRESET (0).CONNECT = Disconnected or
+ UICR_Periph.PSELRESET (1).CONNECT = Disconnected
+ then
+ NVMC_Periph.CONFIG := CONFIG_Register'
+ (WEN => Wen,
+ Reserved_2_31 => 0);
+ loop
+ exit when NVMC_Periph.READY.READY = Ready;
+ end loop;
+
+ UICR_Periph.PSELRESET (0) := PSELRESET_Register'
+ (PIN => 21,
+ Reserved_6_30 => 0,
+ CONNECT => Connected);
+ loop
+ exit when NVMC_Periph.READY.READY = Ready;
+ end loop;
+
+ UICR_Periph.PSELRESET (1) := PSELRESET_Register'
+ (PIN => 21,
+ Reserved_6_30 => 0,
+ CONNECT => Connected);
+ loop
+ exit when NVMC_Periph.READY.READY = Ready;
+ end loop;
+
+ NVMC_Periph.CONFIG := CONFIG_Register'
+ (WEN => Ren,
+ Reserved_2_31 => 0);
+ loop
+ exit when NVMC_Periph.READY.READY = Ready;
+ end loop;
+
+ NVIC_SystemReset;
+ end if;
+ end if;
+
+ -- Configure the 32.768 kHz external crystal.
+ -- The LFCLK will be started later, if required by the runtime.
+ --
+ -- The Ravenscar runtime uses LFCLK as its timing source for task delays,
+ -- so LFCLK will be started by System.BB.Board_Support.Initialize_Board.
+ --
+ -- The ZFP runtime does not use LFCLK, so it is not started in ZFP.
+ CLOCK_Periph.LFCLKSRC := LFCLKSRC_Register'
+ (SRC => LFCLK_Source,
+ Reserved_2_15 => 0,
+ BYPASS => Disabled,
+ EXTERNAL => Disabled,
+ Reserved_18_31 => 0);
+
+ -- Optionally enable the external HFXO.
+ -- If HFXO is disabled, then the HFCLK will use the internal HF oscillator
+ if Use_HFXO then
+ CLOCK_Periph.TASKS_HFCLKSTART := (TASKS_HFCLKSTART => 1, others => <>);
+ end if;
+end Setup_Board;
diff --git a/arm/nordic/nrf52/nrf52832/svd/a-intnam.ads b/arm/nordic/nrf52/nrf52832/svd/a-intnam.ads
new file mode 100644
index 00000000..4c7edb89
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52832/svd/a-intnam.ads
@@ -0,0 +1,98 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update for
+-- such product, must reproduce the above copyright notice, this list of
+-- conditions and the following disclaimer in the documentation and/or other
+-- materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from this
+-- software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52.svd
+
+-- This is a version for the nRF52832 reference description for radio MCU with
+-- ARM 32-bit Cortex-M4 Microcontroller MCU
+package Ada.Interrupts.Names is
+
+ -- All identifiers in this unit are implementation defined
+
+ pragma Implementation_Defined;
+
+ ----------------
+ -- Interrupts --
+ ----------------
+
+ -- System tick
+ Sys_Tick_Interrupt : constant Interrupt_ID := -1;
+ POWER_CLOCK_Interrupt : constant Interrupt_ID := 0;
+ RADIO_Interrupt : constant Interrupt_ID := 1;
+ UARTE0_UART0_Interrupt : constant Interrupt_ID := 2;
+ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_Interrupt : constant Interrupt_ID := 3;
+ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_Interrupt : constant Interrupt_ID := 4;
+ NFCT_Interrupt : constant Interrupt_ID := 5;
+ GPIOTE_Interrupt : constant Interrupt_ID := 6;
+ SAADC_Interrupt : constant Interrupt_ID := 7;
+ TIMER0_Interrupt : constant Interrupt_ID := 8;
+ TIMER1_Interrupt : constant Interrupt_ID := 9;
+ TIMER2_Interrupt : constant Interrupt_ID := 10;
+ RTC0_Interrupt : constant Interrupt_ID := 11;
+ TEMP_Interrupt : constant Interrupt_ID := 12;
+ RNG_Interrupt : constant Interrupt_ID := 13;
+ ECB_Interrupt : constant Interrupt_ID := 14;
+ CCM_AAR_Interrupt : constant Interrupt_ID := 15;
+ WDT_Interrupt : constant Interrupt_ID := 16;
+ RTC1_Interrupt : constant Interrupt_ID := 17;
+ QDEC_Interrupt : constant Interrupt_ID := 18;
+ COMP_LPCOMP_Interrupt : constant Interrupt_ID := 19;
+ SWI0_EGU0_Interrupt : constant Interrupt_ID := 20;
+ SWI1_EGU1_Interrupt : constant Interrupt_ID := 21;
+ SWI2_EGU2_Interrupt : constant Interrupt_ID := 22;
+ SWI3_EGU3_Interrupt : constant Interrupt_ID := 23;
+ SWI4_EGU4_Interrupt : constant Interrupt_ID := 24;
+ SWI5_EGU5_Interrupt : constant Interrupt_ID := 25;
+ TIMER3_Interrupt : constant Interrupt_ID := 26;
+ TIMER4_Interrupt : constant Interrupt_ID := 27;
+ PWM0_Interrupt : constant Interrupt_ID := 28;
+ PDM_Interrupt : constant Interrupt_ID := 29;
+ MWU_Interrupt : constant Interrupt_ID := 32;
+ PWM1_Interrupt : constant Interrupt_ID := 33;
+ PWM2_Interrupt : constant Interrupt_ID := 34;
+ SPIM2_SPIS2_SPI2_Interrupt : constant Interrupt_ID := 35;
+ RTC2_Interrupt : constant Interrupt_ID := 36;
+ I2S_Interrupt : constant Interrupt_ID := 37;
+ FPU_Interrupt : constant Interrupt_ID := 38;
+
+end Ada.Interrupts.Names;
diff --git a/arm/nordic/nrf52/nrf52832/svd/handler.S b/arm/nordic/nrf52/nrf52832/svd/handler.S
new file mode 100644
index 00000000..e8837a58
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52832/svd/handler.S
@@ -0,0 +1,103 @@
+## -*- asm -*- #############################
+# Automatically generated by SVD2Ada
+# For the nRF52832 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller target
+############################################
+
+ .syntax unified
+ .cpu cortex-m4
+ .thumb
+
+ .text
+ .globl __vectors
+ .p2align 8
+__vectors:
+ /* Cortex-M core interrupts */
+ .word 0 /* stack top address */
+ .word fault /* 1 Reset. */
+ .word fault /* 2 NMI. */
+ .word fault /* 3 Hard fault. */
+ .word fault /* 4 Mem manage. */
+ .word fault /* 5 Bus fault. */
+ .word fault /* 6 Usage fault. */
+ .word fault /* 7 reserved. */
+ .word fault /* 8 reserved. */
+ .word fault /* 9 reserved. */
+ .word fault /* 10 reserved. */
+ .word __gnat_sv_call_trap /* 11 SVCall. */
+ .word __gnat_bkpt_trap /* 12 Breakpoint. */
+ .word fault /* 13 reserved. */
+ .word __gnat_pend_sv_trap /* 14 PendSV. */
+ .word __gnat_sys_tick_trap /* 15 Systick. */
+ /* MCU interrupts */
+ .word __gnat_irq_trap /* 16 POWER_CLOCK */
+ .word __gnat_irq_trap /* 17 RADIO */
+ .word __gnat_irq_trap /* 18 UARTE0_UART0 */
+ .word __gnat_irq_trap /* 19 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */
+ .word __gnat_irq_trap /* 20 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */
+ .word __gnat_irq_trap /* 21 NFCT */
+ .word __gnat_irq_trap /* 22 GPIOTE */
+ .word __gnat_irq_trap /* 23 SAADC */
+ .word __gnat_irq_trap /* 24 TIMER0 */
+ .word __gnat_irq_trap /* 25 TIMER1 */
+ .word __gnat_irq_trap /* 26 TIMER2 */
+ .word __gnat_irq_trap /* 27 RTC0 */
+ .word __gnat_irq_trap /* 28 TEMP */
+ .word __gnat_irq_trap /* 29 RNG */
+ .word __gnat_irq_trap /* 30 ECB */
+ .word __gnat_irq_trap /* 31 CCM_AAR */
+ .word __gnat_irq_trap /* 32 WDT */
+ .word __gnat_irq_trap /* 33 RTC1 */
+ .word __gnat_irq_trap /* 34 QDEC */
+ .word __gnat_irq_trap /* 35 COMP_LPCOMP */
+ .word __gnat_irq_trap /* 36 SWI0_EGU0 */
+ .word __gnat_irq_trap /* 37 SWI1_EGU1 */
+ .word __gnat_irq_trap /* 38 SWI2_EGU2 */
+ .word __gnat_irq_trap /* 39 SWI3_EGU3 */
+ .word __gnat_irq_trap /* 40 SWI4_EGU4 */
+ .word __gnat_irq_trap /* 41 SWI5_EGU5 */
+ .word __gnat_irq_trap /* 42 TIMER3 */
+ .word __gnat_irq_trap /* 43 TIMER4 */
+ .word __gnat_irq_trap /* 44 PWM0 */
+ .word __gnat_irq_trap /* 45 PDM */
+ .word __gnat_irq_trap /* 46 IRQ 30. */
+ .word __gnat_irq_trap /* 47 IRQ 31. */
+ .word __gnat_irq_trap /* 48 MWU */
+ .word __gnat_irq_trap /* 49 PWM1 */
+ .word __gnat_irq_trap /* 50 PWM2 */
+ .word __gnat_irq_trap /* 51 SPIM2_SPIS2_SPI2 */
+ .word __gnat_irq_trap /* 52 RTC2 */
+ .word __gnat_irq_trap /* 53 I2S */
+ .word __gnat_irq_trap /* 54 FPU */
+
+ .text
+
+ .thumb_func
+.weak __gnat_irq_trap
+.type __gnat_irq_trap, %function
+__gnat_irq_trap:
+0: b 0b
+ .size __gnat_irq_trap, . - __gnat_irq_trap
+
+ .thumb_func
+.weak __gnat_sv_call_trap
+.type __gnat_sv_call_trap, %function
+__gnat_sv_call_trap:
+0: b 0b
+ .size __gnat_sv_call_trap, . - __gnat_sv_call_trap
+
+ .thumb_func
+.weak __gnat_pend_sv_trap
+.type __gnat_pend_sv_trap, %function
+__gnat_pend_sv_trap:
+0: b 0b
+ .size __gnat_pend_sv_trap, . - __gnat_pend_sv_trap
+
+ .thumb_func
+.weak __gnat_sys_tick_trap
+.type __gnat_sys_tick_trap, %function
+__gnat_sys_tick_trap:
+0: b 0b
+ .size __gnat_sys_tick_trap, . - __gnat_sys_tick_trap
+
+ .thumb_func
+fault: b fault
diff --git a/arm/nordic/nrf52/nrf52832/svd/i-nrf52-clock.ads b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-clock.ads
new file mode 100644
index 00000000..90d15ebf
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-clock.ads
@@ -0,0 +1,868 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update for
+-- such product, must reproduce the above copyright notice, this list of
+-- conditions and the following disclaimer in the documentation and/or other
+-- materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from this
+-- software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.CLOCK is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ subtype TASKS_HFCLKSTART_TASKS_HFCLKSTART_Field is Interfaces.NRF52.Bit;
+
+ -- Start HFCLK crystal oscillator
+ type TASKS_HFCLKSTART_Register is record
+ -- Write-only.
+ TASKS_HFCLKSTART : TASKS_HFCLKSTART_TASKS_HFCLKSTART_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_HFCLKSTART_Register use record
+ TASKS_HFCLKSTART at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Field is Interfaces.NRF52.Bit;
+
+ -- Stop HFCLK crystal oscillator
+ type TASKS_HFCLKSTOP_Register is record
+ -- Write-only.
+ TASKS_HFCLKSTOP : TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_HFCLKSTOP_Register use record
+ TASKS_HFCLKSTOP at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_LFCLKSTART_TASKS_LFCLKSTART_Field is Interfaces.NRF52.Bit;
+
+ -- Start LFCLK source
+ type TASKS_LFCLKSTART_Register is record
+ -- Write-only.
+ TASKS_LFCLKSTART : TASKS_LFCLKSTART_TASKS_LFCLKSTART_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_LFCLKSTART_Register use record
+ TASKS_LFCLKSTART at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Field is Interfaces.NRF52.Bit;
+
+ -- Stop LFCLK source
+ type TASKS_LFCLKSTOP_Register is record
+ -- Write-only.
+ TASKS_LFCLKSTOP : TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_LFCLKSTOP_Register use record
+ TASKS_LFCLKSTOP at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_CAL_TASKS_CAL_Field is Interfaces.NRF52.Bit;
+
+ -- Start calibration of LFRC oscillator
+ type TASKS_CAL_Register is record
+ -- Write-only.
+ TASKS_CAL : TASKS_CAL_TASKS_CAL_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_CAL_Register use record
+ TASKS_CAL at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_CTSTART_TASKS_CTSTART_Field is Interfaces.NRF52.Bit;
+
+ -- Start calibration timer
+ type TASKS_CTSTART_Register is record
+ -- Write-only.
+ TASKS_CTSTART : TASKS_CTSTART_TASKS_CTSTART_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_CTSTART_Register use record
+ TASKS_CTSTART at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_CTSTOP_TASKS_CTSTOP_Field is Interfaces.NRF52.Bit;
+
+ -- Stop calibration timer
+ type TASKS_CTSTOP_Register is record
+ -- Write-only.
+ TASKS_CTSTOP : TASKS_CTSTOP_TASKS_CTSTOP_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_CTSTOP_Register use record
+ TASKS_CTSTOP at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Field is
+ Interfaces.NRF52.Bit;
+
+ -- HFCLK oscillator started
+ type EVENTS_HFCLKSTARTED_Register is record
+ EVENTS_HFCLKSTARTED : EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Field :=
+ 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_HFCLKSTARTED_Register use record
+ EVENTS_HFCLKSTARTED at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Field is
+ Interfaces.NRF52.Bit;
+
+ -- LFCLK started
+ type EVENTS_LFCLKSTARTED_Register is record
+ EVENTS_LFCLKSTARTED : EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Field :=
+ 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_LFCLKSTARTED_Register use record
+ EVENTS_LFCLKSTARTED at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_DONE_EVENTS_DONE_Field is Interfaces.NRF52.Bit;
+
+ -- Calibration of LFCLK RC oscillator complete event
+ type EVENTS_DONE_Register is record
+ EVENTS_DONE : EVENTS_DONE_EVENTS_DONE_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_DONE_Register use record
+ EVENTS_DONE at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_CTTO_EVENTS_CTTO_Field is Interfaces.NRF52.Bit;
+
+ -- Calibration timer timeout
+ type EVENTS_CTTO_Register is record
+ EVENTS_CTTO : EVENTS_CTTO_EVENTS_CTTO_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_CTTO_Register use record
+ EVENTS_CTTO at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Write '1' to Enable interrupt for HFCLKSTARTED event
+ type INTENSET_HFCLKSTARTED_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_HFCLKSTARTED_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable interrupt for HFCLKSTARTED event
+ type INTENSET_HFCLKSTARTED_Field_1 is
+ (-- Reset value for the field
+ Intenset_Hfclkstarted_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_HFCLKSTARTED_Field_1 use
+ (Intenset_Hfclkstarted_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to Enable interrupt for LFCLKSTARTED event
+ type INTENSET_LFCLKSTARTED_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_LFCLKSTARTED_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable interrupt for LFCLKSTARTED event
+ type INTENSET_LFCLKSTARTED_Field_1 is
+ (-- Reset value for the field
+ Intenset_Lfclkstarted_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_LFCLKSTARTED_Field_1 use
+ (Intenset_Lfclkstarted_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to Enable interrupt for DONE event
+ type INTENSET_DONE_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_DONE_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable interrupt for DONE event
+ type INTENSET_DONE_Field_1 is
+ (-- Reset value for the field
+ Intenset_Done_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_DONE_Field_1 use
+ (Intenset_Done_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to Enable interrupt for CTTO event
+ type INTENSET_CTTO_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_CTTO_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable interrupt for CTTO event
+ type INTENSET_CTTO_Field_1 is
+ (-- Reset value for the field
+ Intenset_Ctto_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_CTTO_Field_1 use
+ (Intenset_Ctto_Field_Reset => 0,
+ Set => 1);
+
+ -- Enable interrupt
+ type INTENSET_Register is record
+ -- Write '1' to Enable interrupt for HFCLKSTARTED event
+ HFCLKSTARTED : INTENSET_HFCLKSTARTED_Field_1 :=
+ Intenset_Hfclkstarted_Field_Reset;
+ -- Write '1' to Enable interrupt for LFCLKSTARTED event
+ LFCLKSTARTED : INTENSET_LFCLKSTARTED_Field_1 :=
+ Intenset_Lfclkstarted_Field_Reset;
+ -- unspecified
+ Reserved_2_2 : Interfaces.NRF52.Bit := 16#0#;
+ -- Write '1' to Enable interrupt for DONE event
+ DONE : INTENSET_DONE_Field_1 := Intenset_Done_Field_Reset;
+ -- Write '1' to Enable interrupt for CTTO event
+ CTTO : INTENSET_CTTO_Field_1 := Intenset_Ctto_Field_Reset;
+ -- unspecified
+ Reserved_5_31 : Interfaces.NRF52.UInt27 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENSET_Register use record
+ HFCLKSTARTED at 0 range 0 .. 0;
+ LFCLKSTARTED at 0 range 1 .. 1;
+ Reserved_2_2 at 0 range 2 .. 2;
+ DONE at 0 range 3 .. 3;
+ CTTO at 0 range 4 .. 4;
+ Reserved_5_31 at 0 range 5 .. 31;
+ end record;
+
+ -- Write '1' to Disable interrupt for HFCLKSTARTED event
+ type INTENCLR_HFCLKSTARTED_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_HFCLKSTARTED_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable interrupt for HFCLKSTARTED event
+ type INTENCLR_HFCLKSTARTED_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Hfclkstarted_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_HFCLKSTARTED_Field_1 use
+ (Intenclr_Hfclkstarted_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to Disable interrupt for LFCLKSTARTED event
+ type INTENCLR_LFCLKSTARTED_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_LFCLKSTARTED_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable interrupt for LFCLKSTARTED event
+ type INTENCLR_LFCLKSTARTED_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Lfclkstarted_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_LFCLKSTARTED_Field_1 use
+ (Intenclr_Lfclkstarted_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to Disable interrupt for DONE event
+ type INTENCLR_DONE_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_DONE_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable interrupt for DONE event
+ type INTENCLR_DONE_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Done_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_DONE_Field_1 use
+ (Intenclr_Done_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to Disable interrupt for CTTO event
+ type INTENCLR_CTTO_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_CTTO_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable interrupt for CTTO event
+ type INTENCLR_CTTO_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Ctto_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_CTTO_Field_1 use
+ (Intenclr_Ctto_Field_Reset => 0,
+ Clear => 1);
+
+ -- Disable interrupt
+ type INTENCLR_Register is record
+ -- Write '1' to Disable interrupt for HFCLKSTARTED event
+ HFCLKSTARTED : INTENCLR_HFCLKSTARTED_Field_1 :=
+ Intenclr_Hfclkstarted_Field_Reset;
+ -- Write '1' to Disable interrupt for LFCLKSTARTED event
+ LFCLKSTARTED : INTENCLR_LFCLKSTARTED_Field_1 :=
+ Intenclr_Lfclkstarted_Field_Reset;
+ -- unspecified
+ Reserved_2_2 : Interfaces.NRF52.Bit := 16#0#;
+ -- Write '1' to Disable interrupt for DONE event
+ DONE : INTENCLR_DONE_Field_1 := Intenclr_Done_Field_Reset;
+ -- Write '1' to Disable interrupt for CTTO event
+ CTTO : INTENCLR_CTTO_Field_1 := Intenclr_Ctto_Field_Reset;
+ -- unspecified
+ Reserved_5_31 : Interfaces.NRF52.UInt27 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENCLR_Register use record
+ HFCLKSTARTED at 0 range 0 .. 0;
+ LFCLKSTARTED at 0 range 1 .. 1;
+ Reserved_2_2 at 0 range 2 .. 2;
+ DONE at 0 range 3 .. 3;
+ CTTO at 0 range 4 .. 4;
+ Reserved_5_31 at 0 range 5 .. 31;
+ end record;
+
+ -- HFCLKSTART task triggered or not
+ type HFCLKRUN_STATUS_Field is
+ (-- Task not triggered
+ Nottriggered,
+ -- Task triggered
+ Triggered)
+ with Size => 1;
+ for HFCLKRUN_STATUS_Field use
+ (Nottriggered => 0,
+ Triggered => 1);
+
+ -- Status indicating that HFCLKSTART task has been triggered
+ type HFCLKRUN_Register is record
+ -- Read-only. HFCLKSTART task triggered or not
+ STATUS : HFCLKRUN_STATUS_Field;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for HFCLKRUN_Register use record
+ STATUS at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Source of HFCLK
+ type HFCLKSTAT_SRC_Field is
+ (-- 64 MHz internal oscillator (HFINT)
+ Rc,
+ -- 64 MHz crystal oscillator (HFXO)
+ Xtal)
+ with Size => 1;
+ for HFCLKSTAT_SRC_Field use
+ (Rc => 0,
+ Xtal => 1);
+
+ -- HFCLK state
+ type HFCLKSTAT_STATE_Field is
+ (-- HFCLK not running
+ Notrunning,
+ -- HFCLK running
+ Running)
+ with Size => 1;
+ for HFCLKSTAT_STATE_Field use
+ (Notrunning => 0,
+ Running => 1);
+
+ -- HFCLK status
+ type HFCLKSTAT_Register is record
+ -- Read-only. Source of HFCLK
+ SRC : HFCLKSTAT_SRC_Field;
+ -- unspecified
+ Reserved_1_15 : Interfaces.NRF52.UInt15;
+ -- Read-only. HFCLK state
+ STATE : HFCLKSTAT_STATE_Field;
+ -- unspecified
+ Reserved_17_31 : Interfaces.NRF52.UInt15;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for HFCLKSTAT_Register use record
+ SRC at 0 range 0 .. 0;
+ Reserved_1_15 at 0 range 1 .. 15;
+ STATE at 0 range 16 .. 16;
+ Reserved_17_31 at 0 range 17 .. 31;
+ end record;
+
+ -- LFCLKSTART task triggered or not
+ type LFCLKRUN_STATUS_Field is
+ (-- Task not triggered
+ Nottriggered,
+ -- Task triggered
+ Triggered)
+ with Size => 1;
+ for LFCLKRUN_STATUS_Field use
+ (Nottriggered => 0,
+ Triggered => 1);
+
+ -- Status indicating that LFCLKSTART task has been triggered
+ type LFCLKRUN_Register is record
+ -- Read-only. LFCLKSTART task triggered or not
+ STATUS : LFCLKRUN_STATUS_Field;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for LFCLKRUN_Register use record
+ STATUS at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Source of LFCLK
+ type LFCLKSTAT_SRC_Field is
+ (-- 32.768 kHz RC oscillator
+ Rc,
+ -- 32.768 kHz crystal oscillator
+ Xtal,
+ -- 32.768 kHz synthesized from HFCLK
+ Synth)
+ with Size => 2;
+ for LFCLKSTAT_SRC_Field use
+ (Rc => 0,
+ Xtal => 1,
+ Synth => 2);
+
+ -- LFCLK state
+ type LFCLKSTAT_STATE_Field is
+ (-- LFCLK not running
+ Notrunning,
+ -- LFCLK running
+ Running)
+ with Size => 1;
+ for LFCLKSTAT_STATE_Field use
+ (Notrunning => 0,
+ Running => 1);
+
+ -- LFCLK status
+ type LFCLKSTAT_Register is record
+ -- Read-only. Source of LFCLK
+ SRC : LFCLKSTAT_SRC_Field;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14;
+ -- Read-only. LFCLK state
+ STATE : LFCLKSTAT_STATE_Field;
+ -- unspecified
+ Reserved_17_31 : Interfaces.NRF52.UInt15;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for LFCLKSTAT_Register use record
+ SRC at 0 range 0 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ STATE at 0 range 16 .. 16;
+ Reserved_17_31 at 0 range 17 .. 31;
+ end record;
+
+ -- Clock source
+ type LFCLKSRCCOPY_SRC_Field is
+ (-- 32.768 kHz RC oscillator
+ Rc,
+ -- 32.768 kHz crystal oscillator
+ Xtal,
+ -- 32.768 kHz synthesized from HFCLK
+ Synth)
+ with Size => 2;
+ for LFCLKSRCCOPY_SRC_Field use
+ (Rc => 0,
+ Xtal => 1,
+ Synth => 2);
+
+ -- Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
+ type LFCLKSRCCOPY_Register is record
+ -- Read-only. Clock source
+ SRC : LFCLKSRCCOPY_SRC_Field;
+ -- unspecified
+ Reserved_2_31 : Interfaces.NRF52.UInt30;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for LFCLKSRCCOPY_Register use record
+ SRC at 0 range 0 .. 1;
+ Reserved_2_31 at 0 range 2 .. 31;
+ end record;
+
+ -- Clock source
+ type LFCLKSRC_SRC_Field is
+ (-- 32.768 kHz RC oscillator
+ Rc,
+ -- 32.768 kHz crystal oscillator
+ Xtal,
+ -- 32.768 kHz synthesized from HFCLK
+ Synth)
+ with Size => 2;
+ for LFCLKSRC_SRC_Field use
+ (Rc => 0,
+ Xtal => 1,
+ Synth => 2);
+
+ -- Enable or disable bypass of LFCLK crystal oscillator with external clock
+ -- source
+ type LFCLKSRC_BYPASS_Field is
+ (-- Disable (use with Xtal or low-swing external source)
+ Disabled,
+ -- Enable (use with rail-to-rail external source)
+ Enabled)
+ with Size => 1;
+ for LFCLKSRC_BYPASS_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Enable or disable external source for LFCLK
+ type LFCLKSRC_EXTERNAL_Field is
+ (-- Disable external source (use with Xtal)
+ Disabled,
+ -- Enable use of external source instead of Xtal (SRC needs to be set to Xtal)
+ Enabled)
+ with Size => 1;
+ for LFCLKSRC_EXTERNAL_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Clock source for the LFCLK
+ type LFCLKSRC_Register is record
+ -- Clock source
+ SRC : LFCLKSRC_SRC_Field := Interfaces.NRF52.CLOCK.Rc;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14 := 16#0#;
+ -- Enable or disable bypass of LFCLK crystal oscillator with external
+ -- clock source
+ BYPASS : LFCLKSRC_BYPASS_Field :=
+ Interfaces.NRF52.CLOCK.Disabled;
+ -- Enable or disable external source for LFCLK
+ EXTERNAL : LFCLKSRC_EXTERNAL_Field :=
+ Interfaces.NRF52.CLOCK.Disabled;
+ -- unspecified
+ Reserved_18_31 : Interfaces.NRF52.UInt14 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for LFCLKSRC_Register use record
+ SRC at 0 range 0 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ BYPASS at 0 range 16 .. 16;
+ EXTERNAL at 0 range 17 .. 17;
+ Reserved_18_31 at 0 range 18 .. 31;
+ end record;
+
+ subtype CTIV_CTIV_Field is Interfaces.NRF52.UInt7;
+
+ -- Calibration timer interval
+ type CTIV_Register is record
+ -- Calibration timer interval in multiple of 0.25 seconds. Range: 0.25
+ -- seconds to 31.75 seconds.
+ CTIV : CTIV_CTIV_Field := 16#0#;
+ -- unspecified
+ Reserved_7_31 : Interfaces.NRF52.UInt25 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for CTIV_Register use record
+ CTIV at 0 range 0 .. 6;
+ Reserved_7_31 at 0 range 7 .. 31;
+ end record;
+
+ -- Speed of Trace Port clock. Note that the TRACECLK pin will output this
+ -- clock divided by two.
+ type TRACECONFIG_TRACEPORTSPEED_Field is
+ (-- 32 MHz Trace Port clock (TRACECLK = 16 MHz)
+ Val_32Mhz,
+ -- 16 MHz Trace Port clock (TRACECLK = 8 MHz)
+ Val_16Mhz,
+ -- 8 MHz Trace Port clock (TRACECLK = 4 MHz)
+ Val_8Mhz,
+ -- 4 MHz Trace Port clock (TRACECLK = 2 MHz)
+ Val_4Mhz)
+ with Size => 2;
+ for TRACECONFIG_TRACEPORTSPEED_Field use
+ (Val_32Mhz => 0,
+ Val_16Mhz => 1,
+ Val_8Mhz => 2,
+ Val_4Mhz => 3);
+
+ -- Pin multiplexing of trace signals.
+ type TRACECONFIG_TRACEMUX_Field is
+ (-- GPIOs multiplexed onto all trace-pins
+ Gpio,
+ -- SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins
+ Serial,
+ -- TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and
+-- P0.14.
+ Parallel)
+ with Size => 2;
+ for TRACECONFIG_TRACEMUX_Field use
+ (Gpio => 0,
+ Serial => 1,
+ Parallel => 2);
+
+ -- Clocking options for the Trace Port debug interface
+ type TRACECONFIG_Register is record
+ -- Speed of Trace Port clock. Note that the TRACECLK pin will output
+ -- this clock divided by two.
+ TRACEPORTSPEED : TRACECONFIG_TRACEPORTSPEED_Field :=
+ Interfaces.NRF52.CLOCK.Val_32Mhz;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14 := 16#0#;
+ -- Pin multiplexing of trace signals.
+ TRACEMUX : TRACECONFIG_TRACEMUX_Field :=
+ Interfaces.NRF52.CLOCK.Gpio;
+ -- unspecified
+ Reserved_18_31 : Interfaces.NRF52.UInt14 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TRACECONFIG_Register use record
+ TRACEPORTSPEED at 0 range 0 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ TRACEMUX at 0 range 16 .. 17;
+ Reserved_18_31 at 0 range 18 .. 31;
+ end record;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ -- Clock control
+ type CLOCK_Peripheral is record
+ -- Start HFCLK crystal oscillator
+ TASKS_HFCLKSTART : aliased TASKS_HFCLKSTART_Register;
+ -- Stop HFCLK crystal oscillator
+ TASKS_HFCLKSTOP : aliased TASKS_HFCLKSTOP_Register;
+ -- Start LFCLK source
+ TASKS_LFCLKSTART : aliased TASKS_LFCLKSTART_Register;
+ -- Stop LFCLK source
+ TASKS_LFCLKSTOP : aliased TASKS_LFCLKSTOP_Register;
+ -- Start calibration of LFRC oscillator
+ TASKS_CAL : aliased TASKS_CAL_Register;
+ -- Start calibration timer
+ TASKS_CTSTART : aliased TASKS_CTSTART_Register;
+ -- Stop calibration timer
+ TASKS_CTSTOP : aliased TASKS_CTSTOP_Register;
+ -- HFCLK oscillator started
+ EVENTS_HFCLKSTARTED : aliased EVENTS_HFCLKSTARTED_Register;
+ -- LFCLK started
+ EVENTS_LFCLKSTARTED : aliased EVENTS_LFCLKSTARTED_Register;
+ -- Calibration of LFCLK RC oscillator complete event
+ EVENTS_DONE : aliased EVENTS_DONE_Register;
+ -- Calibration timer timeout
+ EVENTS_CTTO : aliased EVENTS_CTTO_Register;
+ -- Enable interrupt
+ INTENSET : aliased INTENSET_Register;
+ -- Disable interrupt
+ INTENCLR : aliased INTENCLR_Register;
+ -- Status indicating that HFCLKSTART task has been triggered
+ HFCLKRUN : aliased HFCLKRUN_Register;
+ -- HFCLK status
+ HFCLKSTAT : aliased HFCLKSTAT_Register;
+ -- Status indicating that LFCLKSTART task has been triggered
+ LFCLKRUN : aliased LFCLKRUN_Register;
+ -- LFCLK status
+ LFCLKSTAT : aliased LFCLKSTAT_Register;
+ -- Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
+ LFCLKSRCCOPY : aliased LFCLKSRCCOPY_Register;
+ -- Clock source for the LFCLK
+ LFCLKSRC : aliased LFCLKSRC_Register;
+ -- Calibration timer interval
+ CTIV : aliased CTIV_Register;
+ -- Clocking options for the Trace Port debug interface
+ TRACECONFIG : aliased TRACECONFIG_Register;
+ end record
+ with Volatile;
+
+ for CLOCK_Peripheral use record
+ TASKS_HFCLKSTART at 16#0# range 0 .. 31;
+ TASKS_HFCLKSTOP at 16#4# range 0 .. 31;
+ TASKS_LFCLKSTART at 16#8# range 0 .. 31;
+ TASKS_LFCLKSTOP at 16#C# range 0 .. 31;
+ TASKS_CAL at 16#10# range 0 .. 31;
+ TASKS_CTSTART at 16#14# range 0 .. 31;
+ TASKS_CTSTOP at 16#18# range 0 .. 31;
+ EVENTS_HFCLKSTARTED at 16#100# range 0 .. 31;
+ EVENTS_LFCLKSTARTED at 16#104# range 0 .. 31;
+ EVENTS_DONE at 16#10C# range 0 .. 31;
+ EVENTS_CTTO at 16#110# range 0 .. 31;
+ INTENSET at 16#304# range 0 .. 31;
+ INTENCLR at 16#308# range 0 .. 31;
+ HFCLKRUN at 16#408# range 0 .. 31;
+ HFCLKSTAT at 16#40C# range 0 .. 31;
+ LFCLKRUN at 16#414# range 0 .. 31;
+ LFCLKSTAT at 16#418# range 0 .. 31;
+ LFCLKSRCCOPY at 16#41C# range 0 .. 31;
+ LFCLKSRC at 16#518# range 0 .. 31;
+ CTIV at 16#538# range 0 .. 31;
+ TRACECONFIG at 16#55C# range 0 .. 31;
+ end record;
+
+ -- Clock control
+ CLOCK_Periph : aliased CLOCK_Peripheral
+ with Import, Address => CLOCK_Base;
+
+end Interfaces.NRF52.CLOCK;
diff --git a/arm/nordic/nrf52/nrf52832/svd/i-nrf52-ficr.ads b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-ficr.ads
new file mode 100644
index 00000000..711fe2f9
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-ficr.ads
@@ -0,0 +1,464 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update for
+-- such product, must reproduce the above copyright notice, this list of
+-- conditions and the following disclaimer in the documentation and/or other
+-- materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from this
+-- software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.FICR is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ -- Description collection[0]: Device identifier
+
+ -- Description collection[0]: Device identifier
+ type DEVICEID_Registers is array (0 .. 1) of Interfaces.NRF52.UInt32;
+
+ -- Description collection[0]: Encryption Root, word 0
+
+ -- Description collection[0]: Encryption Root, word 0
+ type ER_Registers is array (0 .. 3) of Interfaces.NRF52.UInt32;
+
+ -- Description collection[0]: Identity Root, word 0
+
+ -- Description collection[0]: Identity Root, word 0
+ type IR_Registers is array (0 .. 3) of Interfaces.NRF52.UInt32;
+
+ -- Device address type
+ type DEVICEADDRTYPE_DEVICEADDRTYPE_Field is
+ (-- Public address
+ Public,
+ -- Random address
+ Random)
+ with Size => 1;
+ for DEVICEADDRTYPE_DEVICEADDRTYPE_Field use
+ (Public => 0,
+ Random => 1);
+
+ -- Device address type
+ type DEVICEADDRTYPE_Register is record
+ -- Read-only. Device address type
+ DEVICEADDRTYPE : DEVICEADDRTYPE_DEVICEADDRTYPE_Field;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for DEVICEADDRTYPE_Register use record
+ DEVICEADDRTYPE at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Description collection[0]: Device address 0
+
+ -- Description collection[0]: Device address 0
+ type DEVICEADDR_Registers is array (0 .. 1) of Interfaces.NRF52.UInt32;
+
+ ------------------------------
+ -- INFO cluster's Registers --
+ ------------------------------
+
+ -- Description collection[0]: Unspecified
+
+ -- Description collection[0]: Unspecified
+ type UNUSED0_INFO_Registers is array (0 .. 2) of Interfaces.NRF52.UInt32;
+
+ -- Device info
+ type INFO_Cluster is record
+ -- Part code
+ PART : aliased Interfaces.NRF52.UInt32;
+ -- Part Variant, Hardware version and Production configuration
+ VARIANT : aliased Interfaces.NRF52.UInt32;
+ -- Package option
+ PACKAGE_k : aliased Interfaces.NRF52.UInt32;
+ -- RAM variant
+ RAM : aliased Interfaces.NRF52.UInt32;
+ -- Flash variant
+ FLASH : aliased Interfaces.NRF52.UInt32;
+ -- Description collection[0]: Unspecified
+ UNUSED0 : aliased UNUSED0_INFO_Registers;
+ end record
+ with Size => 256;
+
+ for INFO_Cluster use record
+ PART at 16#0# range 0 .. 31;
+ VARIANT at 16#4# range 0 .. 31;
+ PACKAGE_k at 16#8# range 0 .. 31;
+ RAM at 16#C# range 0 .. 31;
+ FLASH at 16#10# range 0 .. 31;
+ UNUSED0 at 16#14# range 0 .. 95;
+ end record;
+
+ ------------------------------
+ -- TEMP cluster's Registers --
+ ------------------------------
+
+ subtype A_A_Field is Interfaces.NRF52.UInt12;
+
+ -- Slope definition A0.
+ type A_Register is record
+ -- Read-only. A (slope definition) register.
+ A : A_A_Field;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for A_Register use record
+ A at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype B_B_Field is Interfaces.NRF52.UInt14;
+
+ -- y-intercept B0.
+ type B_Register is record
+ -- Read-only. B (y-intercept)
+ B : B_B_Field;
+ -- unspecified
+ Reserved_14_31 : Interfaces.NRF52.UInt18;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for B_Register use record
+ B at 0 range 0 .. 13;
+ Reserved_14_31 at 0 range 14 .. 31;
+ end record;
+
+ subtype T_T_Field is Interfaces.NRF52.Byte;
+
+ -- Segment end T0.
+ type T_Register is record
+ -- Read-only. T (segment end)register.
+ T : T_T_Field;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for T_Register use record
+ T at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ -- Registers storing factory TEMP module linearization coefficients
+ type TEMP_Cluster is record
+ -- Slope definition A0.
+ A0 : aliased A_Register;
+ -- Slope definition A1.
+ A1 : aliased A_Register;
+ -- Slope definition A2.
+ A2 : aliased A_Register;
+ -- Slope definition A3.
+ A3 : aliased A_Register;
+ -- Slope definition A4.
+ A4 : aliased A_Register;
+ -- Slope definition A5.
+ A5 : aliased A_Register;
+ -- y-intercept B0.
+ B0 : aliased B_Register;
+ -- y-intercept B1.
+ B1 : aliased B_Register;
+ -- y-intercept B2.
+ B2 : aliased B_Register;
+ -- y-intercept B3.
+ B3 : aliased B_Register;
+ -- y-intercept B4.
+ B4 : aliased B_Register;
+ -- y-intercept B5.
+ B5 : aliased B_Register;
+ -- Segment end T0.
+ T0 : aliased T_Register;
+ -- Segment end T1.
+ T1 : aliased T_Register;
+ -- Segment end T2.
+ T2 : aliased T_Register;
+ -- Segment end T3.
+ T3 : aliased T_Register;
+ -- Segment end T4.
+ T4 : aliased T_Register;
+ end record
+ with Size => 544;
+
+ for TEMP_Cluster use record
+ A0 at 16#0# range 0 .. 31;
+ A1 at 16#4# range 0 .. 31;
+ A2 at 16#8# range 0 .. 31;
+ A3 at 16#C# range 0 .. 31;
+ A4 at 16#10# range 0 .. 31;
+ A5 at 16#14# range 0 .. 31;
+ B0 at 16#18# range 0 .. 31;
+ B1 at 16#1C# range 0 .. 31;
+ B2 at 16#20# range 0 .. 31;
+ B3 at 16#24# range 0 .. 31;
+ B4 at 16#28# range 0 .. 31;
+ B5 at 16#2C# range 0 .. 31;
+ T0 at 16#30# range 0 .. 31;
+ T1 at 16#34# range 0 .. 31;
+ T2 at 16#38# range 0 .. 31;
+ T3 at 16#3C# range 0 .. 31;
+ T4 at 16#40# range 0 .. 31;
+ end record;
+
+ -----------------------------
+ -- NFC cluster's Registers --
+ -----------------------------
+
+ subtype TAGHEADER0_NFC_MFGID_Field is Interfaces.NRF52.Byte;
+ -- TAGHEADER0_NFC_UD array element
+ subtype TAGHEADER0_NFC_UD_Element is Interfaces.NRF52.Byte;
+
+ -- TAGHEADER0_NFC_UD array
+ type TAGHEADER0_NFC_UD_Field_Array is array (1 .. 3)
+ of TAGHEADER0_NFC_UD_Element
+ with Component_Size => 8, Size => 24;
+
+ -- Type definition for TAGHEADER0_NFC_UD
+ type TAGHEADER0_NFC_UD_Field
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- UD as a value
+ Val : Interfaces.NRF52.UInt24;
+ when True =>
+ -- UD as an array
+ Arr : TAGHEADER0_NFC_UD_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 24;
+
+ for TAGHEADER0_NFC_UD_Field use record
+ Val at 0 range 0 .. 23;
+ Arr at 0 range 0 .. 23;
+ end record;
+
+ -- Default header for NFC Tag. Software can read these values to populate
+ -- NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ type TAGHEADER0_NFC_Register is record
+ -- Read-only. Default Manufacturer ID: Nordic Semiconductor ASA has ICM
+ -- 0x5F
+ MFGID : TAGHEADER0_NFC_MFGID_Field;
+ -- Read-only. Unique identifier byte 1
+ UD : TAGHEADER0_NFC_UD_Field;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TAGHEADER0_NFC_Register use record
+ MFGID at 0 range 0 .. 7;
+ UD at 0 range 8 .. 31;
+ end record;
+
+ -- TAGHEADER1_NFC_UD array element
+ subtype TAGHEADER1_NFC_UD_Element is Interfaces.NRF52.Byte;
+
+ -- TAGHEADER1_NFC_UD array
+ type TAGHEADER1_NFC_UD_Field_Array is array (4 .. 7)
+ of TAGHEADER1_NFC_UD_Element
+ with Component_Size => 8, Size => 32;
+
+ -- Default header for NFC Tag. Software can read these values to populate
+ -- NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ type TAGHEADER1_NFC_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- UD as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- UD as an array
+ Arr : TAGHEADER1_NFC_UD_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for TAGHEADER1_NFC_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- TAGHEADER2_NFC_UD array element
+ subtype TAGHEADER2_NFC_UD_Element is Interfaces.NRF52.Byte;
+
+ -- TAGHEADER2_NFC_UD array
+ type TAGHEADER2_NFC_UD_Field_Array is array (8 .. 11)
+ of TAGHEADER2_NFC_UD_Element
+ with Component_Size => 8, Size => 32;
+
+ -- Default header for NFC Tag. Software can read these values to populate
+ -- NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ type TAGHEADER2_NFC_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- UD as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- UD as an array
+ Arr : TAGHEADER2_NFC_UD_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for TAGHEADER2_NFC_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- TAGHEADER3_NFC_UD array element
+ subtype TAGHEADER3_NFC_UD_Element is Interfaces.NRF52.Byte;
+
+ -- TAGHEADER3_NFC_UD array
+ type TAGHEADER3_NFC_UD_Field_Array is array (12 .. 15)
+ of TAGHEADER3_NFC_UD_Element
+ with Component_Size => 8, Size => 32;
+
+ -- Default header for NFC Tag. Software can read these values to populate
+ -- NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ type TAGHEADER3_NFC_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- UD as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- UD as an array
+ Arr : TAGHEADER3_NFC_UD_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for TAGHEADER3_NFC_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Unspecified
+ type NFC_Cluster is record
+ -- Default header for NFC Tag. Software can read these values to
+ -- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ TAGHEADER0 : aliased TAGHEADER0_NFC_Register;
+ -- Default header for NFC Tag. Software can read these values to
+ -- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ TAGHEADER1 : aliased TAGHEADER1_NFC_Register;
+ -- Default header for NFC Tag. Software can read these values to
+ -- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ TAGHEADER2 : aliased TAGHEADER2_NFC_Register;
+ -- Default header for NFC Tag. Software can read these values to
+ -- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ TAGHEADER3 : aliased TAGHEADER3_NFC_Register;
+ end record
+ with Size => 128;
+
+ for NFC_Cluster use record
+ TAGHEADER0 at 16#0# range 0 .. 31;
+ TAGHEADER1 at 16#4# range 0 .. 31;
+ TAGHEADER2 at 16#8# range 0 .. 31;
+ TAGHEADER3 at 16#C# range 0 .. 31;
+ end record;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ -- Factory Information Configuration Registers
+ type FICR_Peripheral is record
+ -- Code memory page size
+ CODEPAGESIZE : aliased Interfaces.NRF52.UInt32;
+ -- Code memory size
+ CODESIZE : aliased Interfaces.NRF52.UInt32;
+ -- Description collection[0]: Device identifier
+ DEVICEID : aliased DEVICEID_Registers;
+ -- Description collection[0]: Encryption Root, word 0
+ ER : aliased ER_Registers;
+ -- Description collection[0]: Identity Root, word 0
+ IR : aliased IR_Registers;
+ -- Device address type
+ DEVICEADDRTYPE : aliased DEVICEADDRTYPE_Register;
+ -- Description collection[0]: Device address 0
+ DEVICEADDR : aliased DEVICEADDR_Registers;
+ -- Device info
+ INFO : aliased INFO_Cluster;
+ -- Registers storing factory TEMP module linearization coefficients
+ TEMP : aliased TEMP_Cluster;
+ -- Unspecified
+ NFC : aliased NFC_Cluster;
+ end record
+ with Volatile;
+
+ for FICR_Peripheral use record
+ CODEPAGESIZE at 16#10# range 0 .. 31;
+ CODESIZE at 16#14# range 0 .. 31;
+ DEVICEID at 16#60# range 0 .. 63;
+ ER at 16#80# range 0 .. 127;
+ IR at 16#90# range 0 .. 127;
+ DEVICEADDRTYPE at 16#A0# range 0 .. 31;
+ DEVICEADDR at 16#A4# range 0 .. 63;
+ INFO at 16#100# range 0 .. 255;
+ TEMP at 16#404# range 0 .. 543;
+ NFC at 16#450# range 0 .. 127;
+ end record;
+
+ -- Factory Information Configuration Registers
+ FICR_Periph : aliased FICR_Peripheral
+ with Import, Address => FICR_Base;
+
+end Interfaces.NRF52.FICR;
diff --git a/arm/nordic/nrf52/nrf52832/svd/i-nrf52-gpio.ads b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-gpio.ads
new file mode 100644
index 00000000..73acd521
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-gpio.ads
@@ -0,0 +1,583 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update for
+-- such product, must reproduce the above copyright notice, this list of
+-- conditions and the following disclaimer in the documentation and/or other
+-- materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from this
+-- software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.GPIO is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ -- Pin 0
+ type OUT_PIN0_Field is
+ (-- Pin driver is low
+ Low,
+ -- Pin driver is high
+ High)
+ with Size => 1;
+ for OUT_PIN0_Field use
+ (Low => 0,
+ High => 1);
+
+ -- OUT_PIN array
+ type OUT_PIN_Field_Array is array (0 .. 31) of OUT_PIN0_Field
+ with Component_Size => 1, Size => 32;
+
+ -- Write GPIO port
+ type OUT_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : OUT_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for OUT_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Pin 0
+ type OUTSET_PIN0_Field is
+ (-- Read: pin driver is low
+ Low,
+ -- Read: pin driver is high
+ High)
+ with Size => 1;
+ for OUTSET_PIN0_Field use
+ (Low => 0,
+ High => 1);
+
+ -- Pin 0
+ type OUTSET_PIN0_Field_1 is
+ (-- Reset value for the field
+ Outset_Pin0_Field_Reset,
+ -- Write: writing a '1' sets the pin high; writing a '0' has no effect
+ Set)
+ with Size => 1;
+ for OUTSET_PIN0_Field_1 use
+ (Outset_Pin0_Field_Reset => 0,
+ Set => 1);
+
+ -- OUTSET_PIN array
+ type OUTSET_PIN_Field_Array is array (0 .. 31) of OUTSET_PIN0_Field_1
+ with Component_Size => 1, Size => 32;
+
+ -- Set individual bits in GPIO port
+ type OUTSET_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : OUTSET_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for OUTSET_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Pin 0
+ type OUTCLR_PIN0_Field is
+ (-- Read: pin driver is low
+ Low,
+ -- Read: pin driver is high
+ High)
+ with Size => 1;
+ for OUTCLR_PIN0_Field use
+ (Low => 0,
+ High => 1);
+
+ -- Pin 0
+ type OUTCLR_PIN0_Field_1 is
+ (-- Reset value for the field
+ Outclr_Pin0_Field_Reset,
+ -- Write: writing a '1' sets the pin low; writing a '0' has no effect
+ Clear)
+ with Size => 1;
+ for OUTCLR_PIN0_Field_1 use
+ (Outclr_Pin0_Field_Reset => 0,
+ Clear => 1);
+
+ -- OUTCLR_PIN array
+ type OUTCLR_PIN_Field_Array is array (0 .. 31) of OUTCLR_PIN0_Field_1
+ with Component_Size => 1, Size => 32;
+
+ -- Clear individual bits in GPIO port
+ type OUTCLR_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : OUTCLR_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for OUTCLR_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Pin 0
+ type IN_PIN0_Field is
+ (-- Pin input is low
+ Low,
+ -- Pin input is high
+ High)
+ with Size => 1;
+ for IN_PIN0_Field use
+ (Low => 0,
+ High => 1);
+
+ -- IN_PIN array
+ type IN_PIN_Field_Array is array (0 .. 31) of IN_PIN0_Field
+ with Component_Size => 1, Size => 32;
+
+ -- Read GPIO port
+ type IN_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : IN_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for IN_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Pin 0
+ type DIR_PIN0_Field is
+ (-- Pin set as input
+ Input,
+ -- Pin set as output
+ Output)
+ with Size => 1;
+ for DIR_PIN0_Field use
+ (Input => 0,
+ Output => 1);
+
+ -- DIR_PIN array
+ type DIR_PIN_Field_Array is array (0 .. 31) of DIR_PIN0_Field
+ with Component_Size => 1, Size => 32;
+
+ -- Direction of GPIO pins
+ type DIR_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : DIR_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for DIR_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Set as output pin 0
+ type DIRSET_PIN0_Field is
+ (-- Read: pin set as input
+ Input,
+ -- Read: pin set as output
+ Output)
+ with Size => 1;
+ for DIRSET_PIN0_Field use
+ (Input => 0,
+ Output => 1);
+
+ -- Set as output pin 0
+ type DIRSET_PIN0_Field_1 is
+ (-- Reset value for the field
+ Dirset_Pin0_Field_Reset,
+ -- Write: writing a '1' sets pin to output; writing a '0' has no effect
+ Set)
+ with Size => 1;
+ for DIRSET_PIN0_Field_1 use
+ (Dirset_Pin0_Field_Reset => 0,
+ Set => 1);
+
+ -- DIRSET_PIN array
+ type DIRSET_PIN_Field_Array is array (0 .. 31) of DIRSET_PIN0_Field_1
+ with Component_Size => 1, Size => 32;
+
+ -- DIR set register
+ type DIRSET_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : DIRSET_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for DIRSET_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Set as input pin 0
+ type DIRCLR_PIN0_Field is
+ (-- Read: pin set as input
+ Input,
+ -- Read: pin set as output
+ Output)
+ with Size => 1;
+ for DIRCLR_PIN0_Field use
+ (Input => 0,
+ Output => 1);
+
+ -- Set as input pin 0
+ type DIRCLR_PIN0_Field_1 is
+ (-- Reset value for the field
+ Dirclr_Pin0_Field_Reset,
+ -- Write: writing a '1' sets pin to input; writing a '0' has no effect
+ Clear)
+ with Size => 1;
+ for DIRCLR_PIN0_Field_1 use
+ (Dirclr_Pin0_Field_Reset => 0,
+ Clear => 1);
+
+ -- DIRCLR_PIN array
+ type DIRCLR_PIN_Field_Array is array (0 .. 31) of DIRCLR_PIN0_Field_1
+ with Component_Size => 1, Size => 32;
+
+ -- DIR clear register
+ type DIRCLR_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : DIRCLR_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for DIRCLR_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register.
+ -- Write '1' to clear.
+ type LATCH_PIN0_Field is
+ (-- Criteria has not been met
+ Notlatched,
+ -- Criteria has been met
+ Latched)
+ with Size => 1;
+ for LATCH_PIN0_Field use
+ (Notlatched => 0,
+ Latched => 1);
+
+ -- LATCH_PIN array
+ type LATCH_PIN_Field_Array is array (0 .. 31) of LATCH_PIN0_Field
+ with Component_Size => 1, Size => 32;
+
+ -- Latch register indicating what GPIO pins that have met the criteria set
+ -- in the PIN_CNF[n].SENSE registers
+ type LATCH_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : LATCH_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for LATCH_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Select between default DETECT signal behaviour and LDETECT mode
+ type DETECTMODE_DETECTMODE_Field is
+ (-- DETECT directly connected to PIN DETECT signals
+ Default,
+ -- Use the latched LDETECT behaviour
+ Ldetect)
+ with Size => 1;
+ for DETECTMODE_DETECTMODE_Field use
+ (Default => 0,
+ Ldetect => 1);
+
+ -- Select between default DETECT signal behaviour and LDETECT mode
+ type DETECTMODE_Register is record
+ -- Select between default DETECT signal behaviour and LDETECT mode
+ DETECTMODE : DETECTMODE_DETECTMODE_Field :=
+ Interfaces.NRF52.GPIO.Default;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for DETECTMODE_Register use record
+ DETECTMODE at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Pin direction. Same physical register as DIR register
+ type PIN_CNF_DIR_Field is
+ (-- Configure pin as an input pin
+ Input,
+ -- Configure pin as an output pin
+ Output)
+ with Size => 1;
+ for PIN_CNF_DIR_Field use
+ (Input => 0,
+ Output => 1);
+
+ -- Connect or disconnect input buffer
+ type PIN_CNF_INPUT_Field is
+ (-- Connect input buffer
+ Connect,
+ -- Disconnect input buffer
+ Disconnect)
+ with Size => 1;
+ for PIN_CNF_INPUT_Field use
+ (Connect => 0,
+ Disconnect => 1);
+
+ -- Pull configuration
+ type PIN_CNF_PULL_Field is
+ (-- No pull
+ Disabled,
+ -- Pull down on pin
+ Pulldown,
+ -- Pull up on pin
+ Pullup)
+ with Size => 2;
+ for PIN_CNF_PULL_Field use
+ (Disabled => 0,
+ Pulldown => 1,
+ Pullup => 3);
+
+ -- Drive configuration
+ type PIN_CNF_DRIVE_Field is
+ (-- Standard '0', standard '1'
+ S0S1,
+ -- High drive '0', standard '1'
+ H0S1,
+ -- Standard '0', high drive '1'
+ S0H1,
+ -- High drive '0', high 'drive '1''
+ H0H1,
+ -- Disconnect '0' standard '1' (normally used for wired-or connections)
+ D0S1,
+ -- Disconnect '0', high drive '1' (normally used for wired-or connections)
+ D0H1,
+ -- Standard '0'. disconnect '1' (normally used for wired-and connections)
+ S0D1,
+ -- High drive '0', disconnect '1' (normally used for wired-and connections)
+ H0D1)
+ with Size => 3;
+ for PIN_CNF_DRIVE_Field use
+ (S0S1 => 0,
+ H0S1 => 1,
+ S0H1 => 2,
+ H0H1 => 3,
+ D0S1 => 4,
+ D0H1 => 5,
+ S0D1 => 6,
+ H0D1 => 7);
+
+ -- Pin sensing mechanism
+ type PIN_CNF_SENSE_Field is
+ (-- Disabled
+ Disabled,
+ -- Sense for high level
+ High,
+ -- Sense for low level
+ Low)
+ with Size => 2;
+ for PIN_CNF_SENSE_Field use
+ (Disabled => 0,
+ High => 2,
+ Low => 3);
+
+ -- Description collection[0]: Configuration of GPIO pins
+ type PIN_CNF_Register is record
+ -- Pin direction. Same physical register as DIR register
+ DIR : PIN_CNF_DIR_Field := Interfaces.NRF52.GPIO.Input;
+ -- Connect or disconnect input buffer
+ INPUT : PIN_CNF_INPUT_Field :=
+ Interfaces.NRF52.GPIO.Disconnect;
+ -- Pull configuration
+ PULL : PIN_CNF_PULL_Field := Interfaces.NRF52.GPIO.Disabled;
+ -- unspecified
+ Reserved_4_7 : Interfaces.NRF52.UInt4 := 16#0#;
+ -- Drive configuration
+ DRIVE : PIN_CNF_DRIVE_Field := Interfaces.NRF52.GPIO.S0S1;
+ -- unspecified
+ Reserved_11_15 : Interfaces.NRF52.UInt5 := 16#0#;
+ -- Pin sensing mechanism
+ SENSE : PIN_CNF_SENSE_Field := Interfaces.NRF52.GPIO.Disabled;
+ -- unspecified
+ Reserved_18_31 : Interfaces.NRF52.UInt14 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for PIN_CNF_Register use record
+ DIR at 0 range 0 .. 0;
+ INPUT at 0 range 1 .. 1;
+ PULL at 0 range 2 .. 3;
+ Reserved_4_7 at 0 range 4 .. 7;
+ DRIVE at 0 range 8 .. 10;
+ Reserved_11_15 at 0 range 11 .. 15;
+ SENSE at 0 range 16 .. 17;
+ Reserved_18_31 at 0 range 18 .. 31;
+ end record;
+
+ -- Description collection[0]: Configuration of GPIO pins
+ type PIN_CNF_Registers is array (0 .. 31) of PIN_CNF_Register;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ -- GPIO Port 1
+ type GPIO_Peripheral is record
+ -- Write GPIO port
+ OUT_k : aliased OUT_Register;
+ -- Set individual bits in GPIO port
+ OUTSET : aliased OUTSET_Register;
+ -- Clear individual bits in GPIO port
+ OUTCLR : aliased OUTCLR_Register;
+ -- Read GPIO port
+ IN_k : aliased IN_Register;
+ -- Direction of GPIO pins
+ DIR : aliased DIR_Register;
+ -- DIR set register
+ DIRSET : aliased DIRSET_Register;
+ -- DIR clear register
+ DIRCLR : aliased DIRCLR_Register;
+ -- Latch register indicating what GPIO pins that have met the criteria
+ -- set in the PIN_CNF[n].SENSE registers
+ LATCH : aliased LATCH_Register;
+ -- Select between default DETECT signal behaviour and LDETECT mode
+ DETECTMODE : aliased DETECTMODE_Register;
+ -- Description collection[0]: Configuration of GPIO pins
+ PIN_CNF : aliased PIN_CNF_Registers;
+ end record
+ with Volatile;
+
+ for GPIO_Peripheral use record
+ OUT_k at 16#504# range 0 .. 31;
+ OUTSET at 16#508# range 0 .. 31;
+ OUTCLR at 16#50C# range 0 .. 31;
+ IN_k at 16#510# range 0 .. 31;
+ DIR at 16#514# range 0 .. 31;
+ DIRSET at 16#518# range 0 .. 31;
+ DIRCLR at 16#51C# range 0 .. 31;
+ LATCH at 16#520# range 0 .. 31;
+ DETECTMODE at 16#524# range 0 .. 31;
+ PIN_CNF at 16#700# range 0 .. 1023;
+ end record;
+
+ -- GPIO Port 1
+ P0_Periph : aliased GPIO_Peripheral
+ with Import, Address => P0_Base;
+
+end Interfaces.NRF52.GPIO;
diff --git a/arm/nordic/nrf52/nrf52832/svd/i-nrf52-nvmc.ads b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-nvmc.ads
new file mode 100644
index 00000000..5de60eb6
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-nvmc.ads
@@ -0,0 +1,282 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update for
+-- such product, must reproduce the above copyright notice, this list of
+-- conditions and the following disclaimer in the documentation and/or other
+-- materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from this
+-- software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.NVMC is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ -- NVMC is ready or busy
+ type READY_READY_Field is
+ (-- NVMC is busy (on-going write or erase operation)
+ Busy,
+ -- NVMC is ready
+ Ready)
+ with Size => 1;
+ for READY_READY_Field use
+ (Busy => 0,
+ Ready => 1);
+
+ -- Ready flag
+ type READY_Register is record
+ -- Read-only. NVMC is ready or busy
+ READY : READY_READY_Field;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for READY_Register use record
+ READY at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Program memory access mode. It is strongly recommended to only activate
+ -- erase and write modes when they are actively used. Enabling write or
+ -- erase will invalidate the cache and keep it invalidated.
+ type CONFIG_WEN_Field is
+ (-- Read only access
+ Ren,
+ -- Write Enabled
+ Wen,
+ -- Erase enabled
+ Een)
+ with Size => 2;
+ for CONFIG_WEN_Field use
+ (Ren => 0,
+ Wen => 1,
+ Een => 2);
+
+ -- Configuration register
+ type CONFIG_Register is record
+ -- Program memory access mode. It is strongly recommended to only
+ -- activate erase and write modes when they are actively used. Enabling
+ -- write or erase will invalidate the cache and keep it invalidated.
+ WEN : CONFIG_WEN_Field := Interfaces.NRF52.NVMC.Ren;
+ -- unspecified
+ Reserved_2_31 : Interfaces.NRF52.UInt30 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for CONFIG_Register use record
+ WEN at 0 range 0 .. 1;
+ Reserved_2_31 at 0 range 2 .. 31;
+ end record;
+
+ -- Erase all non-volatile memory including UICR registers. Note that code
+ -- erase has to be enabled by CONFIG.EEN before the UICR can be erased.
+ type ERASEALL_ERASEALL_Field is
+ (-- No operation
+ Nooperation,
+ -- Start chip erase
+ Erase)
+ with Size => 1;
+ for ERASEALL_ERASEALL_Field use
+ (Nooperation => 0,
+ Erase => 1);
+
+ -- Register for erasing all non-volatile user memory
+ type ERASEALL_Register is record
+ -- Erase all non-volatile memory including UICR registers. Note that
+ -- code erase has to be enabled by CONFIG.EEN before the UICR can be
+ -- erased.
+ ERASEALL : ERASEALL_ERASEALL_Field :=
+ Interfaces.NRF52.NVMC.Nooperation;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for ERASEALL_Register use record
+ ERASEALL at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Register starting erase of all User Information Configuration Registers.
+ -- Note that code erase has to be enabled by CONFIG.EEN before the UICR can
+ -- be erased.
+ type ERASEUICR_ERASEUICR_Field is
+ (-- No operation
+ Nooperation,
+ -- Start erase of UICR
+ Erase)
+ with Size => 1;
+ for ERASEUICR_ERASEUICR_Field use
+ (Nooperation => 0,
+ Erase => 1);
+
+ -- Register for erasing User Information Configuration Registers
+ type ERASEUICR_Register is record
+ -- Register starting erase of all User Information Configuration
+ -- Registers. Note that code erase has to be enabled by CONFIG.EEN
+ -- before the UICR can be erased.
+ ERASEUICR : ERASEUICR_ERASEUICR_Field :=
+ Interfaces.NRF52.NVMC.Nooperation;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for ERASEUICR_Register use record
+ ERASEUICR at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Cache enable
+ type ICACHECNF_CACHEEN_Field is
+ (-- Disable cache. Invalidates all cache entries.
+ Disabled,
+ -- Enable cache
+ Enabled)
+ with Size => 1;
+ for ICACHECNF_CACHEEN_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Cache profiling enable
+ type ICACHECNF_CACHEPROFEN_Field is
+ (-- Disable cache profiling
+ Disabled,
+ -- Enable cache profiling
+ Enabled)
+ with Size => 1;
+ for ICACHECNF_CACHEPROFEN_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- I-Code cache configuration register.
+ type ICACHECNF_Register is record
+ -- Cache enable
+ CACHEEN : ICACHECNF_CACHEEN_Field :=
+ Interfaces.NRF52.NVMC.Disabled;
+ -- unspecified
+ Reserved_1_7 : Interfaces.NRF52.UInt7 := 16#0#;
+ -- Cache profiling enable
+ CACHEPROFEN : ICACHECNF_CACHEPROFEN_Field :=
+ Interfaces.NRF52.NVMC.Disabled;
+ -- unspecified
+ Reserved_9_31 : Interfaces.NRF52.UInt23 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for ICACHECNF_Register use record
+ CACHEEN at 0 range 0 .. 0;
+ Reserved_1_7 at 0 range 1 .. 7;
+ CACHEPROFEN at 0 range 8 .. 8;
+ Reserved_9_31 at 0 range 9 .. 31;
+ end record;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ type NVMC_Disc is
+ (Age,
+ Cr1);
+
+ -- Non Volatile Memory Controller
+ type NVMC_Peripheral
+ (Discriminent : NVMC_Disc := Age)
+ is record
+ -- Ready flag
+ READY : aliased READY_Register;
+ -- Configuration register
+ CONFIG : aliased CONFIG_Register;
+ -- Register for erasing all non-volatile user memory
+ ERASEALL : aliased ERASEALL_Register;
+ -- Deprecated register - Register for erasing a page in Code area.
+ -- Equivalent to ERASEPAGE.
+ ERASEPCR0 : aliased Interfaces.NRF52.UInt32;
+ -- Register for erasing User Information Configuration Registers
+ ERASEUICR : aliased ERASEUICR_Register;
+ -- I-Code cache configuration register.
+ ICACHECNF : aliased ICACHECNF_Register;
+ -- I-Code cache hit counter.
+ IHIT : aliased Interfaces.NRF52.UInt32;
+ -- I-Code cache miss counter.
+ IMISS : aliased Interfaces.NRF52.UInt32;
+ case Discriminent is
+ when Age =>
+ -- Register for erasing a page in Code area
+ ERASEPAGE : aliased Interfaces.NRF52.UInt32;
+ when Cr1 =>
+ -- Deprecated register - Register for erasing a page in Code area.
+ -- Equivalent to ERASEPAGE.
+ ERASEPCR1 : aliased Interfaces.NRF52.UInt32;
+ end case;
+ end record
+ with Unchecked_Union, Volatile;
+
+ for NVMC_Peripheral use record
+ READY at 16#400# range 0 .. 31;
+ CONFIG at 16#504# range 0 .. 31;
+ ERASEALL at 16#50C# range 0 .. 31;
+ ERASEPCR0 at 16#510# range 0 .. 31;
+ ERASEUICR at 16#514# range 0 .. 31;
+ ICACHECNF at 16#540# range 0 .. 31;
+ IHIT at 16#548# range 0 .. 31;
+ IMISS at 16#54C# range 0 .. 31;
+ ERASEPAGE at 16#508# range 0 .. 31;
+ ERASEPCR1 at 16#508# range 0 .. 31;
+ end record;
+
+ -- Non Volatile Memory Controller
+ NVMC_Periph : aliased NVMC_Peripheral
+ with Import, Address => NVMC_Base;
+
+end Interfaces.NRF52.NVMC;
diff --git a/arm/nordic/nrf52/nrf52832/svd/i-nrf52-rtc.ads b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-rtc.ads
new file mode 100644
index 00000000..a71d1556
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-rtc.ads
@@ -0,0 +1,849 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update for
+-- such product, must reproduce the above copyright notice, this list of
+-- conditions and the following disclaimer in the documentation and/or other
+-- materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from this
+-- software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.RTC is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ subtype TASKS_START_TASKS_START_Field is Interfaces.NRF52.Bit;
+
+ -- Start RTC COUNTER
+ type TASKS_START_Register is record
+ -- Write-only.
+ TASKS_START : TASKS_START_TASKS_START_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_START_Register use record
+ TASKS_START at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_STOP_TASKS_STOP_Field is Interfaces.NRF52.Bit;
+
+ -- Stop RTC COUNTER
+ type TASKS_STOP_Register is record
+ -- Write-only.
+ TASKS_STOP : TASKS_STOP_TASKS_STOP_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_STOP_Register use record
+ TASKS_STOP at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_CLEAR_TASKS_CLEAR_Field is Interfaces.NRF52.Bit;
+
+ -- Clear RTC COUNTER
+ type TASKS_CLEAR_Register is record
+ -- Write-only.
+ TASKS_CLEAR : TASKS_CLEAR_TASKS_CLEAR_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_CLEAR_Register use record
+ TASKS_CLEAR at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Field is Interfaces.NRF52.Bit;
+
+ -- Set COUNTER to 0xFFFFF0
+ type TASKS_TRIGOVRFLW_Register is record
+ -- Write-only.
+ TASKS_TRIGOVRFLW : TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_TRIGOVRFLW_Register use record
+ TASKS_TRIGOVRFLW at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_TICK_EVENTS_TICK_Field is Interfaces.NRF52.Bit;
+
+ -- Event on COUNTER increment
+ type EVENTS_TICK_Register is record
+ EVENTS_TICK : EVENTS_TICK_EVENTS_TICK_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_TICK_Register use record
+ EVENTS_TICK at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_OVRFLW_EVENTS_OVRFLW_Field is Interfaces.NRF52.Bit;
+
+ -- Event on COUNTER overflow
+ type EVENTS_OVRFLW_Register is record
+ EVENTS_OVRFLW : EVENTS_OVRFLW_EVENTS_OVRFLW_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_OVRFLW_Register use record
+ EVENTS_OVRFLW at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_COMPARE_EVENTS_COMPARE_Field is Interfaces.NRF52.Bit;
+
+ -- Description collection[0]: Compare event on CC[0] match
+ type EVENTS_COMPARE_Register is record
+ EVENTS_COMPARE : EVENTS_COMPARE_EVENTS_COMPARE_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_COMPARE_Register use record
+ EVENTS_COMPARE at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Description collection[0]: Compare event on CC[0] match
+ type EVENTS_COMPARE_Registers is array (0 .. 3) of EVENTS_COMPARE_Register;
+
+ -- Write '1' to Enable interrupt for TICK event
+ type INTENSET_TICK_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_TICK_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable interrupt for TICK event
+ type INTENSET_TICK_Field_1 is
+ (-- Reset value for the field
+ Intenset_Tick_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_TICK_Field_1 use
+ (Intenset_Tick_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to Enable interrupt for OVRFLW event
+ type INTENSET_OVRFLW_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_OVRFLW_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable interrupt for OVRFLW event
+ type INTENSET_OVRFLW_Field_1 is
+ (-- Reset value for the field
+ Intenset_Ovrflw_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_OVRFLW_Field_1 use
+ (Intenset_Ovrflw_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to Enable interrupt for COMPARE[0] event
+ type INTENSET_COMPARE0_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_COMPARE0_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable interrupt for COMPARE[0] event
+ type INTENSET_COMPARE0_Field_1 is
+ (-- Reset value for the field
+ Intenset_Compare0_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_COMPARE0_Field_1 use
+ (Intenset_Compare0_Field_Reset => 0,
+ Set => 1);
+
+ -- INTENSET_COMPARE array
+ type INTENSET_COMPARE_Field_Array is array (0 .. 3)
+ of INTENSET_COMPARE0_Field_1
+ with Component_Size => 1, Size => 4;
+
+ -- Type definition for INTENSET_COMPARE
+ type INTENSET_COMPARE_Field
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- COMPARE as a value
+ Val : Interfaces.NRF52.UInt4;
+ when True =>
+ -- COMPARE as an array
+ Arr : INTENSET_COMPARE_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 4;
+
+ for INTENSET_COMPARE_Field use record
+ Val at 0 range 0 .. 3;
+ Arr at 0 range 0 .. 3;
+ end record;
+
+ -- Enable interrupt
+ type INTENSET_Register is record
+ -- Write '1' to Enable interrupt for TICK event
+ TICK : INTENSET_TICK_Field_1 := Intenset_Tick_Field_Reset;
+ -- Write '1' to Enable interrupt for OVRFLW event
+ OVRFLW : INTENSET_OVRFLW_Field_1 := Intenset_Ovrflw_Field_Reset;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14 := 16#0#;
+ -- Write '1' to Enable interrupt for COMPARE[0] event
+ COMPARE : INTENSET_COMPARE_Field :=
+ (As_Array => False, Val => 16#0#);
+ -- unspecified
+ Reserved_20_31 : Interfaces.NRF52.UInt12 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENSET_Register use record
+ TICK at 0 range 0 .. 0;
+ OVRFLW at 0 range 1 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ COMPARE at 0 range 16 .. 19;
+ Reserved_20_31 at 0 range 20 .. 31;
+ end record;
+
+ -- Write '1' to Disable interrupt for TICK event
+ type INTENCLR_TICK_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_TICK_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable interrupt for TICK event
+ type INTENCLR_TICK_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Tick_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_TICK_Field_1 use
+ (Intenclr_Tick_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to Disable interrupt for OVRFLW event
+ type INTENCLR_OVRFLW_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_OVRFLW_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable interrupt for OVRFLW event
+ type INTENCLR_OVRFLW_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Ovrflw_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_OVRFLW_Field_1 use
+ (Intenclr_Ovrflw_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to Disable interrupt for COMPARE[0] event
+ type INTENCLR_COMPARE0_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_COMPARE0_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable interrupt for COMPARE[0] event
+ type INTENCLR_COMPARE0_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Compare0_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_COMPARE0_Field_1 use
+ (Intenclr_Compare0_Field_Reset => 0,
+ Clear => 1);
+
+ -- INTENCLR_COMPARE array
+ type INTENCLR_COMPARE_Field_Array is array (0 .. 3)
+ of INTENCLR_COMPARE0_Field_1
+ with Component_Size => 1, Size => 4;
+
+ -- Type definition for INTENCLR_COMPARE
+ type INTENCLR_COMPARE_Field
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- COMPARE as a value
+ Val : Interfaces.NRF52.UInt4;
+ when True =>
+ -- COMPARE as an array
+ Arr : INTENCLR_COMPARE_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 4;
+
+ for INTENCLR_COMPARE_Field use record
+ Val at 0 range 0 .. 3;
+ Arr at 0 range 0 .. 3;
+ end record;
+
+ -- Disable interrupt
+ type INTENCLR_Register is record
+ -- Write '1' to Disable interrupt for TICK event
+ TICK : INTENCLR_TICK_Field_1 := Intenclr_Tick_Field_Reset;
+ -- Write '1' to Disable interrupt for OVRFLW event
+ OVRFLW : INTENCLR_OVRFLW_Field_1 := Intenclr_Ovrflw_Field_Reset;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14 := 16#0#;
+ -- Write '1' to Disable interrupt for COMPARE[0] event
+ COMPARE : INTENCLR_COMPARE_Field :=
+ (As_Array => False, Val => 16#0#);
+ -- unspecified
+ Reserved_20_31 : Interfaces.NRF52.UInt12 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENCLR_Register use record
+ TICK at 0 range 0 .. 0;
+ OVRFLW at 0 range 1 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ COMPARE at 0 range 16 .. 19;
+ Reserved_20_31 at 0 range 20 .. 31;
+ end record;
+
+ -- Enable or disable event routing for TICK event
+ type EVTEN_TICK_Field is
+ (-- Disable
+ Disabled,
+ -- Enable
+ Enabled)
+ with Size => 1;
+ for EVTEN_TICK_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Enable or disable event routing for OVRFLW event
+ type EVTEN_OVRFLW_Field is
+ (-- Disable
+ Disabled,
+ -- Enable
+ Enabled)
+ with Size => 1;
+ for EVTEN_OVRFLW_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Enable or disable event routing for COMPARE[0] event
+ type EVTEN_COMPARE0_Field is
+ (-- Disable
+ Disabled,
+ -- Enable
+ Enabled)
+ with Size => 1;
+ for EVTEN_COMPARE0_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- EVTEN_COMPARE array
+ type EVTEN_COMPARE_Field_Array is array (0 .. 3) of EVTEN_COMPARE0_Field
+ with Component_Size => 1, Size => 4;
+
+ -- Type definition for EVTEN_COMPARE
+ type EVTEN_COMPARE_Field
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- COMPARE as a value
+ Val : Interfaces.NRF52.UInt4;
+ when True =>
+ -- COMPARE as an array
+ Arr : EVTEN_COMPARE_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 4;
+
+ for EVTEN_COMPARE_Field use record
+ Val at 0 range 0 .. 3;
+ Arr at 0 range 0 .. 3;
+ end record;
+
+ -- Enable or disable event routing
+ type EVTEN_Register is record
+ -- Enable or disable event routing for TICK event
+ TICK : EVTEN_TICK_Field := Interfaces.NRF52.RTC.Disabled;
+ -- Enable or disable event routing for OVRFLW event
+ OVRFLW : EVTEN_OVRFLW_Field := Interfaces.NRF52.RTC.Disabled;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14 := 16#0#;
+ -- Enable or disable event routing for COMPARE[0] event
+ COMPARE : EVTEN_COMPARE_Field :=
+ (As_Array => False, Val => 16#0#);
+ -- unspecified
+ Reserved_20_31 : Interfaces.NRF52.UInt12 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVTEN_Register use record
+ TICK at 0 range 0 .. 0;
+ OVRFLW at 0 range 1 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ COMPARE at 0 range 16 .. 19;
+ Reserved_20_31 at 0 range 20 .. 31;
+ end record;
+
+ -- Write '1' to Enable event routing for TICK event
+ type EVTENSET_TICK_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for EVTENSET_TICK_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable event routing for TICK event
+ type EVTENSET_TICK_Field_1 is
+ (-- Reset value for the field
+ Evtenset_Tick_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for EVTENSET_TICK_Field_1 use
+ (Evtenset_Tick_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to Enable event routing for OVRFLW event
+ type EVTENSET_OVRFLW_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for EVTENSET_OVRFLW_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable event routing for OVRFLW event
+ type EVTENSET_OVRFLW_Field_1 is
+ (-- Reset value for the field
+ Evtenset_Ovrflw_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for EVTENSET_OVRFLW_Field_1 use
+ (Evtenset_Ovrflw_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to Enable event routing for COMPARE[0] event
+ type EVTENSET_COMPARE0_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for EVTENSET_COMPARE0_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable event routing for COMPARE[0] event
+ type EVTENSET_COMPARE0_Field_1 is
+ (-- Reset value for the field
+ Evtenset_Compare0_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for EVTENSET_COMPARE0_Field_1 use
+ (Evtenset_Compare0_Field_Reset => 0,
+ Set => 1);
+
+ -- EVTENSET_COMPARE array
+ type EVTENSET_COMPARE_Field_Array is array (0 .. 3)
+ of EVTENSET_COMPARE0_Field_1
+ with Component_Size => 1, Size => 4;
+
+ -- Type definition for EVTENSET_COMPARE
+ type EVTENSET_COMPARE_Field
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- COMPARE as a value
+ Val : Interfaces.NRF52.UInt4;
+ when True =>
+ -- COMPARE as an array
+ Arr : EVTENSET_COMPARE_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 4;
+
+ for EVTENSET_COMPARE_Field use record
+ Val at 0 range 0 .. 3;
+ Arr at 0 range 0 .. 3;
+ end record;
+
+ -- Enable event routing
+ type EVTENSET_Register is record
+ -- Write '1' to Enable event routing for TICK event
+ TICK : EVTENSET_TICK_Field_1 := Evtenset_Tick_Field_Reset;
+ -- Write '1' to Enable event routing for OVRFLW event
+ OVRFLW : EVTENSET_OVRFLW_Field_1 := Evtenset_Ovrflw_Field_Reset;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14 := 16#0#;
+ -- Write '1' to Enable event routing for COMPARE[0] event
+ COMPARE : EVTENSET_COMPARE_Field :=
+ (As_Array => False, Val => 16#0#);
+ -- unspecified
+ Reserved_20_31 : Interfaces.NRF52.UInt12 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVTENSET_Register use record
+ TICK at 0 range 0 .. 0;
+ OVRFLW at 0 range 1 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ COMPARE at 0 range 16 .. 19;
+ Reserved_20_31 at 0 range 20 .. 31;
+ end record;
+
+ -- Write '1' to Disable event routing for TICK event
+ type EVTENCLR_TICK_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for EVTENCLR_TICK_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable event routing for TICK event
+ type EVTENCLR_TICK_Field_1 is
+ (-- Reset value for the field
+ Evtenclr_Tick_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for EVTENCLR_TICK_Field_1 use
+ (Evtenclr_Tick_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to Disable event routing for OVRFLW event
+ type EVTENCLR_OVRFLW_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for EVTENCLR_OVRFLW_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable event routing for OVRFLW event
+ type EVTENCLR_OVRFLW_Field_1 is
+ (-- Reset value for the field
+ Evtenclr_Ovrflw_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for EVTENCLR_OVRFLW_Field_1 use
+ (Evtenclr_Ovrflw_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to Disable event routing for COMPARE[0] event
+ type EVTENCLR_COMPARE0_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for EVTENCLR_COMPARE0_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable event routing for COMPARE[0] event
+ type EVTENCLR_COMPARE0_Field_1 is
+ (-- Reset value for the field
+ Evtenclr_Compare0_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for EVTENCLR_COMPARE0_Field_1 use
+ (Evtenclr_Compare0_Field_Reset => 0,
+ Clear => 1);
+
+ -- EVTENCLR_COMPARE array
+ type EVTENCLR_COMPARE_Field_Array is array (0 .. 3)
+ of EVTENCLR_COMPARE0_Field_1
+ with Component_Size => 1, Size => 4;
+
+ -- Type definition for EVTENCLR_COMPARE
+ type EVTENCLR_COMPARE_Field
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- COMPARE as a value
+ Val : Interfaces.NRF52.UInt4;
+ when True =>
+ -- COMPARE as an array
+ Arr : EVTENCLR_COMPARE_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 4;
+
+ for EVTENCLR_COMPARE_Field use record
+ Val at 0 range 0 .. 3;
+ Arr at 0 range 0 .. 3;
+ end record;
+
+ -- Disable event routing
+ type EVTENCLR_Register is record
+ -- Write '1' to Disable event routing for TICK event
+ TICK : EVTENCLR_TICK_Field_1 := Evtenclr_Tick_Field_Reset;
+ -- Write '1' to Disable event routing for OVRFLW event
+ OVRFLW : EVTENCLR_OVRFLW_Field_1 := Evtenclr_Ovrflw_Field_Reset;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14 := 16#0#;
+ -- Write '1' to Disable event routing for COMPARE[0] event
+ COMPARE : EVTENCLR_COMPARE_Field :=
+ (As_Array => False, Val => 16#0#);
+ -- unspecified
+ Reserved_20_31 : Interfaces.NRF52.UInt12 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVTENCLR_Register use record
+ TICK at 0 range 0 .. 0;
+ OVRFLW at 0 range 1 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ COMPARE at 0 range 16 .. 19;
+ Reserved_20_31 at 0 range 20 .. 31;
+ end record;
+
+ subtype COUNTER_COUNTER_Field is Interfaces.NRF52.UInt24;
+
+ -- Current COUNTER value
+ type COUNTER_Register is record
+ -- Read-only. Counter value
+ COUNTER : COUNTER_COUNTER_Field;
+ -- unspecified
+ Reserved_24_31 : Interfaces.NRF52.Byte;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for COUNTER_Register use record
+ COUNTER at 0 range 0 .. 23;
+ Reserved_24_31 at 0 range 24 .. 31;
+ end record;
+
+ subtype PRESCALER_PRESCALER_Field is Interfaces.NRF52.UInt12;
+
+ -- 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be
+ -- written when RTC is stopped
+ type PRESCALER_Register is record
+ -- Prescaler value
+ PRESCALER : PRESCALER_PRESCALER_Field := 16#0#;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for PRESCALER_Register use record
+ PRESCALER at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype CC_COMPARE_Field is Interfaces.NRF52.UInt24;
+
+ -- Description collection[0]: Compare register 0
+ type CC_Register is record
+ -- Compare value
+ COMPARE : CC_COMPARE_Field := 16#0#;
+ -- unspecified
+ Reserved_24_31 : Interfaces.NRF52.Byte := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for CC_Register use record
+ COMPARE at 0 range 0 .. 23;
+ Reserved_24_31 at 0 range 24 .. 31;
+ end record;
+
+ -- Description collection[0]: Compare register 0
+ type CC_Registers is array (0 .. 3) of CC_Register;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ -- Real time counter 0
+ type RTC_Peripheral is record
+ -- Start RTC COUNTER
+ TASKS_START : aliased TASKS_START_Register;
+ -- Stop RTC COUNTER
+ TASKS_STOP : aliased TASKS_STOP_Register;
+ -- Clear RTC COUNTER
+ TASKS_CLEAR : aliased TASKS_CLEAR_Register;
+ -- Set COUNTER to 0xFFFFF0
+ TASKS_TRIGOVRFLW : aliased TASKS_TRIGOVRFLW_Register;
+ -- Event on COUNTER increment
+ EVENTS_TICK : aliased EVENTS_TICK_Register;
+ -- Event on COUNTER overflow
+ EVENTS_OVRFLW : aliased EVENTS_OVRFLW_Register;
+ -- Description collection[0]: Compare event on CC[0] match
+ EVENTS_COMPARE : aliased EVENTS_COMPARE_Registers;
+ -- Enable interrupt
+ INTENSET : aliased INTENSET_Register;
+ -- Disable interrupt
+ INTENCLR : aliased INTENCLR_Register;
+ -- Enable or disable event routing
+ EVTEN : aliased EVTEN_Register;
+ -- Enable event routing
+ EVTENSET : aliased EVTENSET_Register;
+ -- Disable event routing
+ EVTENCLR : aliased EVTENCLR_Register;
+ -- Current COUNTER value
+ COUNTER : aliased COUNTER_Register;
+ -- 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be
+ -- written when RTC is stopped
+ PRESCALER : aliased PRESCALER_Register;
+ -- Description collection[0]: Compare register 0
+ CC : aliased CC_Registers;
+ end record
+ with Volatile;
+
+ for RTC_Peripheral use record
+ TASKS_START at 16#0# range 0 .. 31;
+ TASKS_STOP at 16#4# range 0 .. 31;
+ TASKS_CLEAR at 16#8# range 0 .. 31;
+ TASKS_TRIGOVRFLW at 16#C# range 0 .. 31;
+ EVENTS_TICK at 16#100# range 0 .. 31;
+ EVENTS_OVRFLW at 16#104# range 0 .. 31;
+ EVENTS_COMPARE at 16#140# range 0 .. 127;
+ INTENSET at 16#304# range 0 .. 31;
+ INTENCLR at 16#308# range 0 .. 31;
+ EVTEN at 16#340# range 0 .. 31;
+ EVTENSET at 16#344# range 0 .. 31;
+ EVTENCLR at 16#348# range 0 .. 31;
+ COUNTER at 16#504# range 0 .. 31;
+ PRESCALER at 16#508# range 0 .. 31;
+ CC at 16#540# range 0 .. 127;
+ end record;
+
+ -- Real time counter 0
+ RTC0_Periph : aliased RTC_Peripheral
+ with Import, Address => RTC0_Base;
+
+ -- Real time counter 1
+ RTC1_Periph : aliased RTC_Peripheral
+ with Import, Address => RTC1_Base;
+
+ -- Real time counter 2
+ RTC2_Periph : aliased RTC_Peripheral
+ with Import, Address => RTC2_Base;
+
+end Interfaces.NRF52.RTC;
diff --git a/arm/nordic/nrf52/nrf52832/svd/i-nrf52-temp.ads b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-temp.ads
new file mode 100644
index 00000000..cb98e1eb
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-temp.ads
@@ -0,0 +1,559 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update for
+-- such product, must reproduce the above copyright notice, this list of
+-- conditions and the following disclaimer in the documentation and/or other
+-- materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from this
+-- software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.TEMP is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ subtype TASKS_START_TASKS_START_Field is Interfaces.NRF52.Bit;
+
+ -- Start temperature measurement
+ type TASKS_START_Register is record
+ -- Write-only.
+ TASKS_START : TASKS_START_TASKS_START_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_START_Register use record
+ TASKS_START at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_STOP_TASKS_STOP_Field is Interfaces.NRF52.Bit;
+
+ -- Stop temperature measurement
+ type TASKS_STOP_Register is record
+ -- Write-only.
+ TASKS_STOP : TASKS_STOP_TASKS_STOP_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_STOP_Register use record
+ TASKS_STOP at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_DATARDY_EVENTS_DATARDY_Field is Interfaces.NRF52.Bit;
+
+ -- Temperature measurement complete, data ready
+ type EVENTS_DATARDY_Register is record
+ EVENTS_DATARDY : EVENTS_DATARDY_EVENTS_DATARDY_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_DATARDY_Register use record
+ EVENTS_DATARDY at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Write '1' to Enable interrupt for DATARDY event
+ type INTENSET_DATARDY_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_DATARDY_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable interrupt for DATARDY event
+ type INTENSET_DATARDY_Field_1 is
+ (-- Reset value for the field
+ Intenset_Datardy_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_DATARDY_Field_1 use
+ (Intenset_Datardy_Field_Reset => 0,
+ Set => 1);
+
+ -- Enable interrupt
+ type INTENSET_Register is record
+ -- Write '1' to Enable interrupt for DATARDY event
+ DATARDY : INTENSET_DATARDY_Field_1 :=
+ Intenset_Datardy_Field_Reset;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENSET_Register use record
+ DATARDY at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Write '1' to Disable interrupt for DATARDY event
+ type INTENCLR_DATARDY_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_DATARDY_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable interrupt for DATARDY event
+ type INTENCLR_DATARDY_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Datardy_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_DATARDY_Field_1 use
+ (Intenclr_Datardy_Field_Reset => 0,
+ Clear => 1);
+
+ -- Disable interrupt
+ type INTENCLR_Register is record
+ -- Write '1' to Disable interrupt for DATARDY event
+ DATARDY : INTENCLR_DATARDY_Field_1 :=
+ Intenclr_Datardy_Field_Reset;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENCLR_Register use record
+ DATARDY at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype A0_A0_Field is Interfaces.NRF52.UInt12;
+
+ -- Slope of 1st piece wise linear function
+ type A0_Register is record
+ -- Slope of 1st piece wise linear function
+ A0 : A0_A0_Field := 16#320#;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for A0_Register use record
+ A0 at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype A1_A1_Field is Interfaces.NRF52.UInt12;
+
+ -- Slope of 2nd piece wise linear function
+ type A1_Register is record
+ -- Slope of 2nd piece wise linear function
+ A1 : A1_A1_Field := 16#343#;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for A1_Register use record
+ A1 at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype A2_A2_Field is Interfaces.NRF52.UInt12;
+
+ -- Slope of 3rd piece wise linear function
+ type A2_Register is record
+ -- Slope of 3rd piece wise linear function
+ A2 : A2_A2_Field := 16#35D#;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for A2_Register use record
+ A2 at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype A3_A3_Field is Interfaces.NRF52.UInt12;
+
+ -- Slope of 4th piece wise linear function
+ type A3_Register is record
+ -- Slope of 4th piece wise linear function
+ A3 : A3_A3_Field := 16#400#;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for A3_Register use record
+ A3 at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype A4_A4_Field is Interfaces.NRF52.UInt12;
+
+ -- Slope of 5th piece wise linear function
+ type A4_Register is record
+ -- Slope of 5th piece wise linear function
+ A4 : A4_A4_Field := 16#47F#;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for A4_Register use record
+ A4 at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype A5_A5_Field is Interfaces.NRF52.UInt12;
+
+ -- Slope of 6th piece wise linear function
+ type A5_Register is record
+ -- Slope of 6th piece wise linear function
+ A5 : A5_A5_Field := 16#37B#;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for A5_Register use record
+ A5 at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype B0_B0_Field is Interfaces.NRF52.UInt14;
+
+ -- y-intercept of 1st piece wise linear function
+ type B0_Register is record
+ -- y-intercept of 1st piece wise linear function
+ B0 : B0_B0_Field := 16#3FCC#;
+ -- unspecified
+ Reserved_14_31 : Interfaces.NRF52.UInt18 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for B0_Register use record
+ B0 at 0 range 0 .. 13;
+ Reserved_14_31 at 0 range 14 .. 31;
+ end record;
+
+ subtype B1_B1_Field is Interfaces.NRF52.UInt14;
+
+ -- y-intercept of 2nd piece wise linear function
+ type B1_Register is record
+ -- y-intercept of 2nd piece wise linear function
+ B1 : B1_B1_Field := 16#3F98#;
+ -- unspecified
+ Reserved_14_31 : Interfaces.NRF52.UInt18 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for B1_Register use record
+ B1 at 0 range 0 .. 13;
+ Reserved_14_31 at 0 range 14 .. 31;
+ end record;
+
+ subtype B2_B2_Field is Interfaces.NRF52.UInt14;
+
+ -- y-intercept of 3rd piece wise linear function
+ type B2_Register is record
+ -- y-intercept of 3rd piece wise linear function
+ B2 : B2_B2_Field := 16#3F98#;
+ -- unspecified
+ Reserved_14_31 : Interfaces.NRF52.UInt18 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for B2_Register use record
+ B2 at 0 range 0 .. 13;
+ Reserved_14_31 at 0 range 14 .. 31;
+ end record;
+
+ subtype B3_B3_Field is Interfaces.NRF52.UInt14;
+
+ -- y-intercept of 4th piece wise linear function
+ type B3_Register is record
+ -- y-intercept of 4th piece wise linear function
+ B3 : B3_B3_Field := 16#12#;
+ -- unspecified
+ Reserved_14_31 : Interfaces.NRF52.UInt18 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for B3_Register use record
+ B3 at 0 range 0 .. 13;
+ Reserved_14_31 at 0 range 14 .. 31;
+ end record;
+
+ subtype B4_B4_Field is Interfaces.NRF52.UInt14;
+
+ -- y-intercept of 5th piece wise linear function
+ type B4_Register is record
+ -- y-intercept of 5th piece wise linear function
+ B4 : B4_B4_Field := 16#6A#;
+ -- unspecified
+ Reserved_14_31 : Interfaces.NRF52.UInt18 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for B4_Register use record
+ B4 at 0 range 0 .. 13;
+ Reserved_14_31 at 0 range 14 .. 31;
+ end record;
+
+ subtype B5_B5_Field is Interfaces.NRF52.UInt14;
+
+ -- y-intercept of 6th piece wise linear function
+ type B5_Register is record
+ -- y-intercept of 6th piece wise linear function
+ B5 : B5_B5_Field := 16#3DD0#;
+ -- unspecified
+ Reserved_14_31 : Interfaces.NRF52.UInt18 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for B5_Register use record
+ B5 at 0 range 0 .. 13;
+ Reserved_14_31 at 0 range 14 .. 31;
+ end record;
+
+ subtype T0_T0_Field is Interfaces.NRF52.Byte;
+
+ -- End point of 1st piece wise linear function
+ type T0_Register is record
+ -- End point of 1st piece wise linear function
+ T0 : T0_T0_Field := 16#E2#;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for T0_Register use record
+ T0 at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ subtype T1_T1_Field is Interfaces.NRF52.Byte;
+
+ -- End point of 2nd piece wise linear function
+ type T1_Register is record
+ -- End point of 2nd piece wise linear function
+ T1 : T1_T1_Field := 16#0#;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for T1_Register use record
+ T1 at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ subtype T2_T2_Field is Interfaces.NRF52.Byte;
+
+ -- End point of 3rd piece wise linear function
+ type T2_Register is record
+ -- End point of 3rd piece wise linear function
+ T2 : T2_T2_Field := 16#14#;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for T2_Register use record
+ T2 at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ subtype T3_T3_Field is Interfaces.NRF52.Byte;
+
+ -- End point of 4th piece wise linear function
+ type T3_Register is record
+ -- End point of 4th piece wise linear function
+ T3 : T3_T3_Field := 16#19#;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for T3_Register use record
+ T3 at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ subtype T4_T4_Field is Interfaces.NRF52.Byte;
+
+ -- End point of 5th piece wise linear function
+ type T4_Register is record
+ -- End point of 5th piece wise linear function
+ T4 : T4_T4_Field := 16#50#;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for T4_Register use record
+ T4 at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ -- Temperature Sensor
+ type TEMP_Peripheral is record
+ -- Start temperature measurement
+ TASKS_START : aliased TASKS_START_Register;
+ -- Stop temperature measurement
+ TASKS_STOP : aliased TASKS_STOP_Register;
+ -- Temperature measurement complete, data ready
+ EVENTS_DATARDY : aliased EVENTS_DATARDY_Register;
+ -- Enable interrupt
+ INTENSET : aliased INTENSET_Register;
+ -- Disable interrupt
+ INTENCLR : aliased INTENCLR_Register;
+ -- Temperature in degC (0.25deg steps)
+ TEMP : aliased Interfaces.NRF52.UInt32;
+ -- Slope of 1st piece wise linear function
+ A0 : aliased A0_Register;
+ -- Slope of 2nd piece wise linear function
+ A1 : aliased A1_Register;
+ -- Slope of 3rd piece wise linear function
+ A2 : aliased A2_Register;
+ -- Slope of 4th piece wise linear function
+ A3 : aliased A3_Register;
+ -- Slope of 5th piece wise linear function
+ A4 : aliased A4_Register;
+ -- Slope of 6th piece wise linear function
+ A5 : aliased A5_Register;
+ -- y-intercept of 1st piece wise linear function
+ B0 : aliased B0_Register;
+ -- y-intercept of 2nd piece wise linear function
+ B1 : aliased B1_Register;
+ -- y-intercept of 3rd piece wise linear function
+ B2 : aliased B2_Register;
+ -- y-intercept of 4th piece wise linear function
+ B3 : aliased B3_Register;
+ -- y-intercept of 5th piece wise linear function
+ B4 : aliased B4_Register;
+ -- y-intercept of 6th piece wise linear function
+ B5 : aliased B5_Register;
+ -- End point of 1st piece wise linear function
+ T0 : aliased T0_Register;
+ -- End point of 2nd piece wise linear function
+ T1 : aliased T1_Register;
+ -- End point of 3rd piece wise linear function
+ T2 : aliased T2_Register;
+ -- End point of 4th piece wise linear function
+ T3 : aliased T3_Register;
+ -- End point of 5th piece wise linear function
+ T4 : aliased T4_Register;
+ end record
+ with Volatile;
+
+ for TEMP_Peripheral use record
+ TASKS_START at 16#0# range 0 .. 31;
+ TASKS_STOP at 16#4# range 0 .. 31;
+ EVENTS_DATARDY at 16#100# range 0 .. 31;
+ INTENSET at 16#304# range 0 .. 31;
+ INTENCLR at 16#308# range 0 .. 31;
+ TEMP at 16#508# range 0 .. 31;
+ A0 at 16#520# range 0 .. 31;
+ A1 at 16#524# range 0 .. 31;
+ A2 at 16#528# range 0 .. 31;
+ A3 at 16#52C# range 0 .. 31;
+ A4 at 16#530# range 0 .. 31;
+ A5 at 16#534# range 0 .. 31;
+ B0 at 16#540# range 0 .. 31;
+ B1 at 16#544# range 0 .. 31;
+ B2 at 16#548# range 0 .. 31;
+ B3 at 16#54C# range 0 .. 31;
+ B4 at 16#550# range 0 .. 31;
+ B5 at 16#554# range 0 .. 31;
+ T0 at 16#560# range 0 .. 31;
+ T1 at 16#564# range 0 .. 31;
+ T2 at 16#568# range 0 .. 31;
+ T3 at 16#56C# range 0 .. 31;
+ T4 at 16#570# range 0 .. 31;
+ end record;
+
+ -- Temperature Sensor
+ TEMP_Periph : aliased TEMP_Peripheral
+ with Import, Address => TEMP_Base;
+
+end Interfaces.NRF52.TEMP;
diff --git a/arm/nordic/nrf52/nrf52832/svd/i-nrf52-uart.ads b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-uart.ads
new file mode 100644
index 00000000..e5a2b5b3
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-uart.ads
@@ -0,0 +1,888 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update for
+-- such product, must reproduce the above copyright notice, this list of
+-- conditions and the following disclaimer in the documentation and/or other
+-- materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from this
+-- software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.UART is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ subtype TASKS_STARTRX_TASKS_STARTRX_Field is Interfaces.NRF52.Bit;
+
+ -- Start UART receiver
+ type TASKS_STARTRX_Register is record
+ -- Write-only.
+ TASKS_STARTRX : TASKS_STARTRX_TASKS_STARTRX_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_STARTRX_Register use record
+ TASKS_STARTRX at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_STOPRX_TASKS_STOPRX_Field is Interfaces.NRF52.Bit;
+
+ -- Stop UART receiver
+ type TASKS_STOPRX_Register is record
+ -- Write-only.
+ TASKS_STOPRX : TASKS_STOPRX_TASKS_STOPRX_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_STOPRX_Register use record
+ TASKS_STOPRX at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_STARTTX_TASKS_STARTTX_Field is Interfaces.NRF52.Bit;
+
+ -- Start UART transmitter
+ type TASKS_STARTTX_Register is record
+ -- Write-only.
+ TASKS_STARTTX : TASKS_STARTTX_TASKS_STARTTX_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_STARTTX_Register use record
+ TASKS_STARTTX at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_STOPTX_TASKS_STOPTX_Field is Interfaces.NRF52.Bit;
+
+ -- Stop UART transmitter
+ type TASKS_STOPTX_Register is record
+ -- Write-only.
+ TASKS_STOPTX : TASKS_STOPTX_TASKS_STOPTX_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_STOPTX_Register use record
+ TASKS_STOPTX at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_SUSPEND_TASKS_SUSPEND_Field is Interfaces.NRF52.Bit;
+
+ -- Suspend UART
+ type TASKS_SUSPEND_Register is record
+ -- Write-only.
+ TASKS_SUSPEND : TASKS_SUSPEND_TASKS_SUSPEND_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_SUSPEND_Register use record
+ TASKS_SUSPEND at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_CTS_EVENTS_CTS_Field is Interfaces.NRF52.Bit;
+
+ -- CTS is activated (set low). Clear To Send.
+ type EVENTS_CTS_Register is record
+ EVENTS_CTS : EVENTS_CTS_EVENTS_CTS_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_CTS_Register use record
+ EVENTS_CTS at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_NCTS_EVENTS_NCTS_Field is Interfaces.NRF52.Bit;
+
+ -- CTS is deactivated (set high). Not Clear To Send.
+ type EVENTS_NCTS_Register is record
+ EVENTS_NCTS : EVENTS_NCTS_EVENTS_NCTS_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_NCTS_Register use record
+ EVENTS_NCTS at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_RXDRDY_EVENTS_RXDRDY_Field is Interfaces.NRF52.Bit;
+
+ -- Data received in RXD
+ type EVENTS_RXDRDY_Register is record
+ EVENTS_RXDRDY : EVENTS_RXDRDY_EVENTS_RXDRDY_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_RXDRDY_Register use record
+ EVENTS_RXDRDY at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_TXDRDY_EVENTS_TXDRDY_Field is Interfaces.NRF52.Bit;
+
+ -- Data sent from TXD
+ type EVENTS_TXDRDY_Register is record
+ EVENTS_TXDRDY : EVENTS_TXDRDY_EVENTS_TXDRDY_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_TXDRDY_Register use record
+ EVENTS_TXDRDY at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_ERROR_EVENTS_ERROR_Field is Interfaces.NRF52.Bit;
+
+ -- Error detected
+ type EVENTS_ERROR_Register is record
+ EVENTS_ERROR : EVENTS_ERROR_EVENTS_ERROR_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_ERROR_Register use record
+ EVENTS_ERROR at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_RXTO_EVENTS_RXTO_Field is Interfaces.NRF52.Bit;
+
+ -- Receiver timeout
+ type EVENTS_RXTO_Register is record
+ EVENTS_RXTO : EVENTS_RXTO_EVENTS_RXTO_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_RXTO_Register use record
+ EVENTS_RXTO at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Shortcut between CTS event and STARTRX task
+ type SHORTS_CTS_STARTRX_Field is
+ (-- Disable shortcut
+ Disabled,
+ -- Enable shortcut
+ Enabled)
+ with Size => 1;
+ for SHORTS_CTS_STARTRX_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Shortcut between NCTS event and STOPRX task
+ type SHORTS_NCTS_STOPRX_Field is
+ (-- Disable shortcut
+ Disabled,
+ -- Enable shortcut
+ Enabled)
+ with Size => 1;
+ for SHORTS_NCTS_STOPRX_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Shortcut register
+ type SHORTS_Register is record
+ -- unspecified
+ Reserved_0_2 : Interfaces.NRF52.UInt3 := 16#0#;
+ -- Shortcut between CTS event and STARTRX task
+ CTS_STARTRX : SHORTS_CTS_STARTRX_Field :=
+ Interfaces.NRF52.UART.Disabled;
+ -- Shortcut between NCTS event and STOPRX task
+ NCTS_STOPRX : SHORTS_NCTS_STOPRX_Field :=
+ Interfaces.NRF52.UART.Disabled;
+ -- unspecified
+ Reserved_5_31 : Interfaces.NRF52.UInt27 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for SHORTS_Register use record
+ Reserved_0_2 at 0 range 0 .. 2;
+ CTS_STARTRX at 0 range 3 .. 3;
+ NCTS_STOPRX at 0 range 4 .. 4;
+ Reserved_5_31 at 0 range 5 .. 31;
+ end record;
+
+ -- Write '1' to Enable interrupt for CTS event
+ type INTENSET_CTS_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_CTS_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable interrupt for CTS event
+ type INTENSET_CTS_Field_1 is
+ (-- Reset value for the field
+ Intenset_Cts_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_CTS_Field_1 use
+ (Intenset_Cts_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to Enable interrupt for NCTS event
+ type INTENSET_NCTS_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_NCTS_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable interrupt for NCTS event
+ type INTENSET_NCTS_Field_1 is
+ (-- Reset value for the field
+ Intenset_Ncts_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_NCTS_Field_1 use
+ (Intenset_Ncts_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to Enable interrupt for RXDRDY event
+ type INTENSET_RXDRDY_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_RXDRDY_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable interrupt for RXDRDY event
+ type INTENSET_RXDRDY_Field_1 is
+ (-- Reset value for the field
+ Intenset_Rxdrdy_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_RXDRDY_Field_1 use
+ (Intenset_Rxdrdy_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to Enable interrupt for TXDRDY event
+ type INTENSET_TXDRDY_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_TXDRDY_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable interrupt for TXDRDY event
+ type INTENSET_TXDRDY_Field_1 is
+ (-- Reset value for the field
+ Intenset_Txdrdy_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_TXDRDY_Field_1 use
+ (Intenset_Txdrdy_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to Enable interrupt for ERROR event
+ type INTENSET_ERROR_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_ERROR_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable interrupt for ERROR event
+ type INTENSET_ERROR_Field_1 is
+ (-- Reset value for the field
+ Intenset_Error_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_ERROR_Field_1 use
+ (Intenset_Error_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to Enable interrupt for RXTO event
+ type INTENSET_RXTO_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_RXTO_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Enable interrupt for RXTO event
+ type INTENSET_RXTO_Field_1 is
+ (-- Reset value for the field
+ Intenset_Rxto_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_RXTO_Field_1 use
+ (Intenset_Rxto_Field_Reset => 0,
+ Set => 1);
+
+ -- Enable interrupt
+ type INTENSET_Register is record
+ -- Write '1' to Enable interrupt for CTS event
+ CTS : INTENSET_CTS_Field_1 := Intenset_Cts_Field_Reset;
+ -- Write '1' to Enable interrupt for NCTS event
+ NCTS : INTENSET_NCTS_Field_1 := Intenset_Ncts_Field_Reset;
+ -- Write '1' to Enable interrupt for RXDRDY event
+ RXDRDY : INTENSET_RXDRDY_Field_1 := Intenset_Rxdrdy_Field_Reset;
+ -- unspecified
+ Reserved_3_6 : Interfaces.NRF52.UInt4 := 16#0#;
+ -- Write '1' to Enable interrupt for TXDRDY event
+ TXDRDY : INTENSET_TXDRDY_Field_1 := Intenset_Txdrdy_Field_Reset;
+ -- unspecified
+ Reserved_8_8 : Interfaces.NRF52.Bit := 16#0#;
+ -- Write '1' to Enable interrupt for ERROR event
+ ERROR : INTENSET_ERROR_Field_1 := Intenset_Error_Field_Reset;
+ -- unspecified
+ Reserved_10_16 : Interfaces.NRF52.UInt7 := 16#0#;
+ -- Write '1' to Enable interrupt for RXTO event
+ RXTO : INTENSET_RXTO_Field_1 := Intenset_Rxto_Field_Reset;
+ -- unspecified
+ Reserved_18_31 : Interfaces.NRF52.UInt14 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENSET_Register use record
+ CTS at 0 range 0 .. 0;
+ NCTS at 0 range 1 .. 1;
+ RXDRDY at 0 range 2 .. 2;
+ Reserved_3_6 at 0 range 3 .. 6;
+ TXDRDY at 0 range 7 .. 7;
+ Reserved_8_8 at 0 range 8 .. 8;
+ ERROR at 0 range 9 .. 9;
+ Reserved_10_16 at 0 range 10 .. 16;
+ RXTO at 0 range 17 .. 17;
+ Reserved_18_31 at 0 range 18 .. 31;
+ end record;
+
+ -- Write '1' to Disable interrupt for CTS event
+ type INTENCLR_CTS_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_CTS_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable interrupt for CTS event
+ type INTENCLR_CTS_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Cts_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_CTS_Field_1 use
+ (Intenclr_Cts_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to Disable interrupt for NCTS event
+ type INTENCLR_NCTS_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_NCTS_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable interrupt for NCTS event
+ type INTENCLR_NCTS_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Ncts_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_NCTS_Field_1 use
+ (Intenclr_Ncts_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to Disable interrupt for RXDRDY event
+ type INTENCLR_RXDRDY_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_RXDRDY_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable interrupt for RXDRDY event
+ type INTENCLR_RXDRDY_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Rxdrdy_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_RXDRDY_Field_1 use
+ (Intenclr_Rxdrdy_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to Disable interrupt for TXDRDY event
+ type INTENCLR_TXDRDY_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_TXDRDY_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable interrupt for TXDRDY event
+ type INTENCLR_TXDRDY_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Txdrdy_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_TXDRDY_Field_1 use
+ (Intenclr_Txdrdy_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to Disable interrupt for ERROR event
+ type INTENCLR_ERROR_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_ERROR_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable interrupt for ERROR event
+ type INTENCLR_ERROR_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Error_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_ERROR_Field_1 use
+ (Intenclr_Error_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to Disable interrupt for RXTO event
+ type INTENCLR_RXTO_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_RXTO_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to Disable interrupt for RXTO event
+ type INTENCLR_RXTO_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Rxto_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_RXTO_Field_1 use
+ (Intenclr_Rxto_Field_Reset => 0,
+ Clear => 1);
+
+ -- Disable interrupt
+ type INTENCLR_Register is record
+ -- Write '1' to Disable interrupt for CTS event
+ CTS : INTENCLR_CTS_Field_1 := Intenclr_Cts_Field_Reset;
+ -- Write '1' to Disable interrupt for NCTS event
+ NCTS : INTENCLR_NCTS_Field_1 := Intenclr_Ncts_Field_Reset;
+ -- Write '1' to Disable interrupt for RXDRDY event
+ RXDRDY : INTENCLR_RXDRDY_Field_1 := Intenclr_Rxdrdy_Field_Reset;
+ -- unspecified
+ Reserved_3_6 : Interfaces.NRF52.UInt4 := 16#0#;
+ -- Write '1' to Disable interrupt for TXDRDY event
+ TXDRDY : INTENCLR_TXDRDY_Field_1 := Intenclr_Txdrdy_Field_Reset;
+ -- unspecified
+ Reserved_8_8 : Interfaces.NRF52.Bit := 16#0#;
+ -- Write '1' to Disable interrupt for ERROR event
+ ERROR : INTENCLR_ERROR_Field_1 := Intenclr_Error_Field_Reset;
+ -- unspecified
+ Reserved_10_16 : Interfaces.NRF52.UInt7 := 16#0#;
+ -- Write '1' to Disable interrupt for RXTO event
+ RXTO : INTENCLR_RXTO_Field_1 := Intenclr_Rxto_Field_Reset;
+ -- unspecified
+ Reserved_18_31 : Interfaces.NRF52.UInt14 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENCLR_Register use record
+ CTS at 0 range 0 .. 0;
+ NCTS at 0 range 1 .. 1;
+ RXDRDY at 0 range 2 .. 2;
+ Reserved_3_6 at 0 range 3 .. 6;
+ TXDRDY at 0 range 7 .. 7;
+ Reserved_8_8 at 0 range 8 .. 8;
+ ERROR at 0 range 9 .. 9;
+ Reserved_10_16 at 0 range 10 .. 16;
+ RXTO at 0 range 17 .. 17;
+ Reserved_18_31 at 0 range 18 .. 31;
+ end record;
+
+ -- Overrun error
+ type ERRORSRC_OVERRUN_Field is
+ (-- Read: error not present
+ Notpresent,
+ -- Read: error present
+ Present)
+ with Size => 1;
+ for ERRORSRC_OVERRUN_Field use
+ (Notpresent => 0,
+ Present => 1);
+
+ -- Parity error
+ type ERRORSRC_PARITY_Field is
+ (-- Read: error not present
+ Notpresent,
+ -- Read: error present
+ Present)
+ with Size => 1;
+ for ERRORSRC_PARITY_Field use
+ (Notpresent => 0,
+ Present => 1);
+
+ -- Framing error occurred
+ type ERRORSRC_FRAMING_Field is
+ (-- Read: error not present
+ Notpresent,
+ -- Read: error present
+ Present)
+ with Size => 1;
+ for ERRORSRC_FRAMING_Field use
+ (Notpresent => 0,
+ Present => 1);
+
+ -- Break condition
+ type ERRORSRC_BREAK_Field is
+ (-- Read: error not present
+ Notpresent,
+ -- Read: error present
+ Present)
+ with Size => 1;
+ for ERRORSRC_BREAK_Field use
+ (Notpresent => 0,
+ Present => 1);
+
+ -- Error source
+ type ERRORSRC_Register is record
+ -- Overrun error
+ OVERRUN : ERRORSRC_OVERRUN_Field :=
+ Interfaces.NRF52.UART.Notpresent;
+ -- Parity error
+ PARITY : ERRORSRC_PARITY_Field :=
+ Interfaces.NRF52.UART.Notpresent;
+ -- Framing error occurred
+ FRAMING : ERRORSRC_FRAMING_Field :=
+ Interfaces.NRF52.UART.Notpresent;
+ -- Break condition
+ BREAK : ERRORSRC_BREAK_Field :=
+ Interfaces.NRF52.UART.Notpresent;
+ -- unspecified
+ Reserved_4_31 : Interfaces.NRF52.UInt28 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for ERRORSRC_Register use record
+ OVERRUN at 0 range 0 .. 0;
+ PARITY at 0 range 1 .. 1;
+ FRAMING at 0 range 2 .. 2;
+ BREAK at 0 range 3 .. 3;
+ Reserved_4_31 at 0 range 4 .. 31;
+ end record;
+
+ -- Enable or disable UART
+ type ENABLE_ENABLE_Field is
+ (-- Disable UART
+ Disabled,
+ -- Enable UART
+ Enabled)
+ with Size => 4;
+ for ENABLE_ENABLE_Field use
+ (Disabled => 0,
+ Enabled => 4);
+
+ -- Enable UART
+ type ENABLE_Register is record
+ -- Enable or disable UART
+ ENABLE : ENABLE_ENABLE_Field := Interfaces.NRF52.UART.Disabled;
+ -- unspecified
+ Reserved_4_31 : Interfaces.NRF52.UInt28 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for ENABLE_Register use record
+ ENABLE at 0 range 0 .. 3;
+ Reserved_4_31 at 0 range 4 .. 31;
+ end record;
+
+ subtype RXD_RXD_Field is Interfaces.NRF52.Byte;
+
+ -- RXD register
+ type RXD_Register is record
+ -- Read-only. *** Reading this field has side effects on other resources
+ -- ***. RX data received in previous transfers, double buffered
+ RXD : RXD_RXD_Field;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for RXD_Register use record
+ RXD at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ subtype TXD_TXD_Field is Interfaces.NRF52.Byte;
+
+ -- TXD register
+ type TXD_Register is record
+ -- Write-only. TX data to be transferred
+ TXD : TXD_TXD_Field := 16#0#;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TXD_Register use record
+ TXD at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ -- Hardware flow control
+ type CONFIG_HWFC_Field is
+ (-- Disabled
+ Disabled,
+ -- Enabled
+ Enabled)
+ with Size => 1;
+ for CONFIG_HWFC_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Parity
+ type CONFIG_PARITY_Field is
+ (-- Exclude parity bit
+ Excluded,
+ -- Include parity bit
+ Included)
+ with Size => 3;
+ for CONFIG_PARITY_Field use
+ (Excluded => 0,
+ Included => 7);
+
+ -- Configuration of parity and hardware flow control
+ type CONFIG_Register is record
+ -- Hardware flow control
+ HWFC : CONFIG_HWFC_Field := Interfaces.NRF52.UART.Disabled;
+ -- Parity
+ PARITY : CONFIG_PARITY_Field := Interfaces.NRF52.UART.Excluded;
+ -- unspecified
+ Reserved_4_31 : Interfaces.NRF52.UInt28 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for CONFIG_Register use record
+ HWFC at 0 range 0 .. 0;
+ PARITY at 0 range 1 .. 3;
+ Reserved_4_31 at 0 range 4 .. 31;
+ end record;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ -- Universal Asynchronous Receiver/Transmitter
+ type UART_Peripheral is record
+ -- Start UART receiver
+ TASKS_STARTRX : aliased TASKS_STARTRX_Register;
+ -- Stop UART receiver
+ TASKS_STOPRX : aliased TASKS_STOPRX_Register;
+ -- Start UART transmitter
+ TASKS_STARTTX : aliased TASKS_STARTTX_Register;
+ -- Stop UART transmitter
+ TASKS_STOPTX : aliased TASKS_STOPTX_Register;
+ -- Suspend UART
+ TASKS_SUSPEND : aliased TASKS_SUSPEND_Register;
+ -- CTS is activated (set low). Clear To Send.
+ EVENTS_CTS : aliased EVENTS_CTS_Register;
+ -- CTS is deactivated (set high). Not Clear To Send.
+ EVENTS_NCTS : aliased EVENTS_NCTS_Register;
+ -- Data received in RXD
+ EVENTS_RXDRDY : aliased EVENTS_RXDRDY_Register;
+ -- Data sent from TXD
+ EVENTS_TXDRDY : aliased EVENTS_TXDRDY_Register;
+ -- Error detected
+ EVENTS_ERROR : aliased EVENTS_ERROR_Register;
+ -- Receiver timeout
+ EVENTS_RXTO : aliased EVENTS_RXTO_Register;
+ -- Shortcut register
+ SHORTS : aliased SHORTS_Register;
+ -- Enable interrupt
+ INTENSET : aliased INTENSET_Register;
+ -- Disable interrupt
+ INTENCLR : aliased INTENCLR_Register;
+ -- Error source
+ ERRORSRC : aliased ERRORSRC_Register;
+ -- Enable UART
+ ENABLE : aliased ENABLE_Register;
+ -- Pin select for RTS
+ PSELRTS : aliased Interfaces.NRF52.UInt32;
+ -- Pin select for TXD
+ PSELTXD : aliased Interfaces.NRF52.UInt32;
+ -- Pin select for CTS
+ PSELCTS : aliased Interfaces.NRF52.UInt32;
+ -- Pin select for RXD
+ PSELRXD : aliased Interfaces.NRF52.UInt32;
+ -- RXD register
+ RXD : aliased RXD_Register;
+ -- TXD register
+ TXD : aliased TXD_Register;
+ -- Baud rate
+ BAUDRATE : aliased Interfaces.NRF52.UInt32;
+ -- Configuration of parity and hardware flow control
+ CONFIG : aliased CONFIG_Register;
+ end record
+ with Volatile;
+
+ for UART_Peripheral use record
+ TASKS_STARTRX at 16#0# range 0 .. 31;
+ TASKS_STOPRX at 16#4# range 0 .. 31;
+ TASKS_STARTTX at 16#8# range 0 .. 31;
+ TASKS_STOPTX at 16#C# range 0 .. 31;
+ TASKS_SUSPEND at 16#1C# range 0 .. 31;
+ EVENTS_CTS at 16#100# range 0 .. 31;
+ EVENTS_NCTS at 16#104# range 0 .. 31;
+ EVENTS_RXDRDY at 16#108# range 0 .. 31;
+ EVENTS_TXDRDY at 16#11C# range 0 .. 31;
+ EVENTS_ERROR at 16#124# range 0 .. 31;
+ EVENTS_RXTO at 16#144# range 0 .. 31;
+ SHORTS at 16#200# range 0 .. 31;
+ INTENSET at 16#304# range 0 .. 31;
+ INTENCLR at 16#308# range 0 .. 31;
+ ERRORSRC at 16#480# range 0 .. 31;
+ ENABLE at 16#500# range 0 .. 31;
+ PSELRTS at 16#508# range 0 .. 31;
+ PSELTXD at 16#50C# range 0 .. 31;
+ PSELCTS at 16#510# range 0 .. 31;
+ PSELRXD at 16#514# range 0 .. 31;
+ RXD at 16#518# range 0 .. 31;
+ TXD at 16#51C# range 0 .. 31;
+ BAUDRATE at 16#524# range 0 .. 31;
+ CONFIG at 16#56C# range 0 .. 31;
+ end record;
+
+ -- Universal Asynchronous Receiver/Transmitter
+ UART0_Periph : aliased UART_Peripheral
+ with Import, Address => UART0_Base;
+
+end Interfaces.NRF52.UART;
diff --git a/arm/nordic/nrf52/nrf52832/svd/i-nrf52-uicr.ads b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-uicr.ads
new file mode 100644
index 00000000..c745a98e
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52832/svd/i-nrf52-uicr.ads
@@ -0,0 +1,212 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update for
+-- such product, must reproduce the above copyright notice, this list of
+-- conditions and the following disclaimer in the documentation and/or other
+-- materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from this
+-- software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.UICR is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ -- Description collection[0]: Reserved for Nordic firmware design
+
+ -- Description collection[0]: Reserved for Nordic firmware design
+ type NRFFW_Registers is array (0 .. 14) of Interfaces.NRF52.UInt32;
+
+ -- Description collection[0]: Reserved for Nordic hardware design
+
+ -- Description collection[0]: Reserved for Nordic hardware design
+ type NRFHW_Registers is array (0 .. 11) of Interfaces.NRF52.UInt32;
+
+ -- Description collection[0]: Reserved for customer
+
+ -- Description collection[0]: Reserved for customer
+ type CUSTOMER_Registers is array (0 .. 31) of Interfaces.NRF52.UInt32;
+
+ subtype PSELRESET_PIN_Field is Interfaces.NRF52.UInt6;
+
+ -- Connection
+ type PSELRESET_CONNECT_Field is
+ (-- Connect
+ Connected,
+ -- Disconnect
+ Disconnected)
+ with Size => 1;
+ for PSELRESET_CONNECT_Field use
+ (Connected => 0,
+ Disconnected => 1);
+
+ -- Description collection[0]: Mapping of the nRESET function (see POWER
+ -- chapter for details)
+ type PSELRESET_Register is record
+ -- GPIO number P0.n onto which Reset is exposed
+ PIN : PSELRESET_PIN_Field := 16#3F#;
+ -- unspecified
+ Reserved_6_30 : Interfaces.NRF52.UInt25 := 16#1FFFFFF#;
+ -- Connection
+ CONNECT : PSELRESET_CONNECT_Field :=
+ Interfaces.NRF52.UICR.Disconnected;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for PSELRESET_Register use record
+ PIN at 0 range 0 .. 5;
+ Reserved_6_30 at 0 range 6 .. 30;
+ CONNECT at 0 range 31 .. 31;
+ end record;
+
+ -- Description collection[0]: Mapping of the nRESET function (see POWER
+ -- chapter for details)
+ type PSELRESET_Registers is array (0 .. 1) of PSELRESET_Register;
+
+ -- Enable or disable Access Port protection. Any other value than 0xFF
+ -- being written to this field will enable protection.
+ type APPROTECT_PALL_Field is
+ (-- Enable
+ Enabled,
+ -- Disable
+ Disabled)
+ with Size => 8;
+ for APPROTECT_PALL_Field use
+ (Enabled => 0,
+ Disabled => 255);
+
+ -- Access Port protection
+ type APPROTECT_Register is record
+ -- Enable or disable Access Port protection. Any other value than 0xFF
+ -- being written to this field will enable protection.
+ PALL : APPROTECT_PALL_Field := Interfaces.NRF52.UICR.Disabled;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#FFFFFF#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for APPROTECT_Register use record
+ PALL at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ -- Setting of pins dedicated to NFC functionality
+ type NFCPINS_PROTECT_Field is
+ (-- Operation as GPIO pins. Same protection as normal GPIO pins
+ Disabled,
+ -- Operation as NFC antenna pins. Configures the protection for NFC operation
+ Nfc)
+ with Size => 1;
+ for NFCPINS_PROTECT_Field use
+ (Disabled => 0,
+ Nfc => 1);
+
+ -- Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
+ type NFCPINS_Register is record
+ -- Setting of pins dedicated to NFC functionality
+ PROTECT : NFCPINS_PROTECT_Field := Interfaces.NRF52.UICR.Nfc;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#7FFFFFFF#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for NFCPINS_Register use record
+ PROTECT at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ -- User Information Configuration Registers
+ type UICR_Peripheral is record
+ -- Unspecified
+ UNUSED0 : aliased Interfaces.NRF52.UInt32;
+ -- Unspecified
+ UNUSED1 : aliased Interfaces.NRF52.UInt32;
+ -- Unspecified
+ UNUSED2 : aliased Interfaces.NRF52.UInt32;
+ -- Unspecified
+ UNUSED3 : aliased Interfaces.NRF52.UInt32;
+ -- Description collection[0]: Reserved for Nordic firmware design
+ NRFFW : aliased NRFFW_Registers;
+ -- Description collection[0]: Reserved for Nordic hardware design
+ NRFHW : aliased NRFHW_Registers;
+ -- Description collection[0]: Reserved for customer
+ CUSTOMER : aliased CUSTOMER_Registers;
+ -- Description collection[0]: Mapping of the nRESET function (see POWER
+ -- chapter for details)
+ PSELRESET : aliased PSELRESET_Registers;
+ -- Access Port protection
+ APPROTECT : aliased APPROTECT_Register;
+ -- Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
+ NFCPINS : aliased NFCPINS_Register;
+ end record
+ with Volatile;
+
+ for UICR_Peripheral use record
+ UNUSED0 at 16#0# range 0 .. 31;
+ UNUSED1 at 16#4# range 0 .. 31;
+ UNUSED2 at 16#8# range 0 .. 31;
+ UNUSED3 at 16#10# range 0 .. 31;
+ NRFFW at 16#14# range 0 .. 479;
+ NRFHW at 16#50# range 0 .. 383;
+ CUSTOMER at 16#80# range 0 .. 1023;
+ PSELRESET at 16#200# range 0 .. 63;
+ APPROTECT at 16#208# range 0 .. 31;
+ NFCPINS at 16#20C# range 0 .. 31;
+ end record;
+
+ -- User Information Configuration Registers
+ UICR_Periph : aliased UICR_Peripheral
+ with Import, Address => UICR_Base;
+
+end Interfaces.NRF52.UICR;
diff --git a/arm/nordic/nrf52/nrf52832/svd/i-nrf52.ads b/arm/nordic/nrf52/nrf52832/svd/i-nrf52.ads
new file mode 100644
index 00000000..e6e6bb09
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52832/svd/i-nrf52.ads
@@ -0,0 +1,258 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update for
+-- such product, must reproduce the above copyright notice, this list of
+-- conditions and the following disclaimer in the documentation and/or other
+-- materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from this
+-- software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+-- nRF52832 reference description for radio MCU with ARM 32-bit Cortex-M4
+-- Microcontroller
+package Interfaces.NRF52 is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Base type --
+ ---------------
+
+ type UInt32 is new Interfaces.Unsigned_32;
+ type UInt16 is new Interfaces.Unsigned_16;
+ type Byte is new Interfaces.Unsigned_8;
+ type Bit is mod 2**1
+ with Size => 1;
+ type UInt2 is mod 2**2
+ with Size => 2;
+ type UInt3 is mod 2**3
+ with Size => 3;
+ type UInt4 is mod 2**4
+ with Size => 4;
+ type UInt5 is mod 2**5
+ with Size => 5;
+ type UInt6 is mod 2**6
+ with Size => 6;
+ type UInt7 is mod 2**7
+ with Size => 7;
+ type UInt9 is mod 2**9
+ with Size => 9;
+ type UInt10 is mod 2**10
+ with Size => 10;
+ type UInt11 is mod 2**11
+ with Size => 11;
+ type UInt12 is mod 2**12
+ with Size => 12;
+ type UInt13 is mod 2**13
+ with Size => 13;
+ type UInt14 is mod 2**14
+ with Size => 14;
+ type UInt15 is mod 2**15
+ with Size => 15;
+ type UInt17 is mod 2**17
+ with Size => 17;
+ type UInt18 is mod 2**18
+ with Size => 18;
+ type UInt19 is mod 2**19
+ with Size => 19;
+ type UInt20 is mod 2**20
+ with Size => 20;
+ type UInt21 is mod 2**21
+ with Size => 21;
+ type UInt22 is mod 2**22
+ with Size => 22;
+ type UInt23 is mod 2**23
+ with Size => 23;
+ type UInt24 is mod 2**24
+ with Size => 24;
+ type UInt25 is mod 2**25
+ with Size => 25;
+ type UInt26 is mod 2**26
+ with Size => 26;
+ type UInt27 is mod 2**27
+ with Size => 27;
+ type UInt28 is mod 2**28
+ with Size => 28;
+ type UInt29 is mod 2**29
+ with Size => 29;
+ type UInt30 is mod 2**30
+ with Size => 30;
+ type UInt31 is mod 2**31
+ with Size => 31;
+
+ --------------------
+ -- Base addresses --
+ --------------------
+
+ FICR_Base : constant System.Address :=
+ System'To_Address (16#10000000#);
+ UICR_Base : constant System.Address :=
+ System'To_Address (16#10001000#);
+ BPROT_Base : constant System.Address :=
+ System'To_Address (16#40000000#);
+ POWER_Base : constant System.Address :=
+ System'To_Address (16#40000000#);
+ CLOCK_Base : constant System.Address :=
+ System'To_Address (16#40000000#);
+ RADIO_Base : constant System.Address :=
+ System'To_Address (16#40001000#);
+ UARTE0_Base : constant System.Address :=
+ System'To_Address (16#40002000#);
+ UART0_Base : constant System.Address :=
+ System'To_Address (16#40002000#);
+ SPIM0_Base : constant System.Address :=
+ System'To_Address (16#40003000#);
+ SPIS0_Base : constant System.Address :=
+ System'To_Address (16#40003000#);
+ TWIM0_Base : constant System.Address :=
+ System'To_Address (16#40003000#);
+ TWIS0_Base : constant System.Address :=
+ System'To_Address (16#40003000#);
+ SPI0_Base : constant System.Address :=
+ System'To_Address (16#40003000#);
+ TWI0_Base : constant System.Address :=
+ System'To_Address (16#40003000#);
+ SPIM1_Base : constant System.Address :=
+ System'To_Address (16#40004000#);
+ SPIS1_Base : constant System.Address :=
+ System'To_Address (16#40004000#);
+ TWIM1_Base : constant System.Address :=
+ System'To_Address (16#40004000#);
+ TWIS1_Base : constant System.Address :=
+ System'To_Address (16#40004000#);
+ SPI1_Base : constant System.Address :=
+ System'To_Address (16#40004000#);
+ TWI1_Base : constant System.Address :=
+ System'To_Address (16#40004000#);
+ NFCT_Base : constant System.Address :=
+ System'To_Address (16#40005000#);
+ GPIOTE_Base : constant System.Address :=
+ System'To_Address (16#40006000#);
+ SAADC_Base : constant System.Address :=
+ System'To_Address (16#40007000#);
+ TIMER0_Base : constant System.Address :=
+ System'To_Address (16#40008000#);
+ TIMER1_Base : constant System.Address :=
+ System'To_Address (16#40009000#);
+ TIMER2_Base : constant System.Address :=
+ System'To_Address (16#4000A000#);
+ RTC0_Base : constant System.Address :=
+ System'To_Address (16#4000B000#);
+ TEMP_Base : constant System.Address :=
+ System'To_Address (16#4000C000#);
+ RNG_Base : constant System.Address :=
+ System'To_Address (16#4000D000#);
+ ECB_Base : constant System.Address :=
+ System'To_Address (16#4000E000#);
+ CCM_Base : constant System.Address :=
+ System'To_Address (16#4000F000#);
+ AAR_Base : constant System.Address :=
+ System'To_Address (16#4000F000#);
+ WDT_Base : constant System.Address :=
+ System'To_Address (16#40010000#);
+ RTC1_Base : constant System.Address :=
+ System'To_Address (16#40011000#);
+ QDEC_Base : constant System.Address :=
+ System'To_Address (16#40012000#);
+ COMP_Base : constant System.Address :=
+ System'To_Address (16#40013000#);
+ LPCOMP_Base : constant System.Address :=
+ System'To_Address (16#40013000#);
+ SWI0_Base : constant System.Address :=
+ System'To_Address (16#40014000#);
+ EGU0_Base : constant System.Address :=
+ System'To_Address (16#40014000#);
+ SWI1_Base : constant System.Address :=
+ System'To_Address (16#40015000#);
+ EGU1_Base : constant System.Address :=
+ System'To_Address (16#40015000#);
+ SWI2_Base : constant System.Address :=
+ System'To_Address (16#40016000#);
+ EGU2_Base : constant System.Address :=
+ System'To_Address (16#40016000#);
+ SWI3_Base : constant System.Address :=
+ System'To_Address (16#40017000#);
+ EGU3_Base : constant System.Address :=
+ System'To_Address (16#40017000#);
+ SWI4_Base : constant System.Address :=
+ System'To_Address (16#40018000#);
+ EGU4_Base : constant System.Address :=
+ System'To_Address (16#40018000#);
+ SWI5_Base : constant System.Address :=
+ System'To_Address (16#40019000#);
+ EGU5_Base : constant System.Address :=
+ System'To_Address (16#40019000#);
+ TIMER3_Base : constant System.Address :=
+ System'To_Address (16#4001A000#);
+ TIMER4_Base : constant System.Address :=
+ System'To_Address (16#4001B000#);
+ PWM0_Base : constant System.Address :=
+ System'To_Address (16#4001C000#);
+ PDM_Base : constant System.Address :=
+ System'To_Address (16#4001D000#);
+ NVMC_Base : constant System.Address :=
+ System'To_Address (16#4001E000#);
+ PPI_Base : constant System.Address :=
+ System'To_Address (16#4001F000#);
+ MWU_Base : constant System.Address :=
+ System'To_Address (16#40020000#);
+ PWM1_Base : constant System.Address :=
+ System'To_Address (16#40021000#);
+ PWM2_Base : constant System.Address :=
+ System'To_Address (16#40022000#);
+ SPIM2_Base : constant System.Address :=
+ System'To_Address (16#40023000#);
+ SPIS2_Base : constant System.Address :=
+ System'To_Address (16#40023000#);
+ SPI2_Base : constant System.Address :=
+ System'To_Address (16#40023000#);
+ RTC2_Base : constant System.Address :=
+ System'To_Address (16#40024000#);
+ I2S_Base : constant System.Address :=
+ System'To_Address (16#40025000#);
+ FPU_Base : constant System.Address :=
+ System'To_Address (16#40026000#);
+ P0_Base : constant System.Address :=
+ System'To_Address (16#50000000#);
+
+end Interfaces.NRF52;
diff --git a/arm/nordic/nrf52/nrf52840/s-bbbopa.ads b/arm/nordic/nrf52/nrf52840/s-bbbopa.ads
new file mode 100644
index 00000000..12552d09
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52840/s-bbbopa.ads
@@ -0,0 +1,67 @@
+------------------------------------------------------------------------------
+-- --
+-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS --
+-- --
+-- S Y S T E M . B B . B O A R D _ P A R A M E T E R S --
+-- --
+-- S p e c --
+-- --
+-- Copyright (C) 2016-2019, AdaCore --
+-- --
+-- GNAT is free software; you can redistribute it and/or modify it under --
+-- terms of the GNU General Public License as published by the Free Soft- --
+-- ware Foundation; either version 3, or (at your option) any later ver- --
+-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
+-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
+-- or FITNESS FOR A PARTICULAR PURPOSE. --
+-- --
+-- As a special exception under Section 7 of GPL version 3, you are granted --
+-- additional permissions described in the GCC Runtime Library Exception, --
+-- version 3.1, as published by the Free Software Foundation. --
+-- --
+-- You should have received a copy of the GNU General Public License and --
+-- a copy of the GCC Runtime Library Exception along with this program; --
+-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
+-- . --
+-- --
+-- GNAT was originally developed by the GNAT team at New York University. --
+-- Extensive contributions were provided by Ada Core Technologies Inc. --
+-- --
+-- The port of GNARL to bare board targets was initially developed by the --
+-- Real-Time Systems Group at the Technical University of Madrid. --
+-- --
+------------------------------------------------------------------------------
+
+-- This package defines board parameters for the nRF52840-DK board
+
+package System.BB.Board_Parameters is
+ pragma No_Elaboration_Code_All;
+ pragma Pure;
+
+ --------------------
+ -- Hardware clock --
+ --------------------
+
+ RTC_Tick_Scaling_Factor : constant := 32; -- 32.768 kHz * 32 = 1.048576 MHz
+ -- Use a fairly high scaling factor so that Ada.Real_Time.Time_Unit is
+ -- at least 1 microsecond. This improves the long-running accuracy of
+ -- periodic tasks where the period is not integer divisible by 32.768 kHz.
+ --
+ -- The maximum permitted scaling factor is 255, otherwise the 24-bit RTC
+ -- period (@ 32 kHz) cannot be scaled to the 32-bit range of
+ -- Timer_Interval.
+
+ Main_Clock_Frequency : constant := 32_768 * RTC_Tick_Scaling_Factor;
+ -- On the nRF52 we use the RTC peripheral as the system tick, instead of
+ -- the Cortex-M4 SysTick because the SysTick is powered down when the CPU
+ -- enters sleep mode (via the "wfi" instruction). Since we still want to
+ -- be able to put the CPU to sleep (to save power) we instead use the
+ -- low-power RTC peripheral, which runs at 32.768 kHz.
+ --
+ -- In this runtime, the minimum allowed frequency is 50_000 Hz so that
+ -- Ada.Real_Time.Time_Unit does not exceed 20 µs as required by
+ -- Ada RM D.8 (30). Since the RTC's actual period is 30.518 µs we multiply
+ -- the RTC frequency by RTC_Tick_Scaling_Factor so that Time_Unit meets the
+ -- requirement in Ada RM D.8 (30).
+
+end System.BB.Board_Parameters;
diff --git a/arm/nordic/nrf52/nrf52840/setup_board.adb b/arm/nordic/nrf52/nrf52840/setup_board.adb
new file mode 100644
index 00000000..d376554c
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52840/setup_board.adb
@@ -0,0 +1,312 @@
+------------------------------------------------------------------------------
+-- --
+-- GNAT RUN-TIME COMPONENTS --
+-- --
+-- Copyright (C) 2012-2019, Free Software Foundation, Inc. --
+-- --
+-- GNAT is free software; you can redistribute it and/or modify it under --
+-- terms of the GNU General Public License as published by the Free Soft- --
+-- ware Foundation; either version 3, or (at your option) any later ver- --
+-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
+-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
+-- or FITNESS FOR A PARTICULAR PURPOSE. --
+-- --
+-- As a special exception under Section 7 of GPL version 3, you are granted --
+-- additional permissions described in the GCC Runtime Library Exception, --
+-- version 3.1, as published by the Free Software Foundation. --
+-- --
+-- You should have received a copy of the GNU General Public License and --
+-- a copy of the GCC Runtime Library Exception along with this program; --
+-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
+-- . --
+-- --
+-- GNAT was originally developed by the GNAT team at New York University. --
+-- Extensive contributions were provided by Ada Core Technologies Inc. --
+-- --
+------------------------------------------------------------------------------
+
+-- This file is based on the startup code from the following file in Nordic's
+-- nRF5 SDK (version 15.1.0): modules/nrfx/mdk/system_nrf52840.c for errata
+-- workarounds and configuration of the SWD pins and reset pin.
+--
+-- This Errata_X functions detect if certain errata are applicable for the
+-- MCU. If they are applicable, then a workaround is applied for the errata.
+-- Some of these errata workarounds rely on reading and/or writing registers
+-- that are not documented in the datasheet. As mentioned above, these
+-- register addresses and values are copied from Nordic's nRF5 SDK.
+
+pragma Ada_2012; -- To work around pre-commit check?
+pragma Suppress (All_Checks);
+
+with System;
+with System.Machine_Code; use System.Machine_Code;
+
+with Interfaces.NRF52; use Interfaces.NRF52;
+with Interfaces.NRF52.CCM; use Interfaces.NRF52.CCM;
+with Interfaces.NRF52.CLOCK; use Interfaces.NRF52.CLOCK;
+with Interfaces.NRF52.FICR; use Interfaces.NRF52.FICR;
+with Interfaces.NRF52.GPIO; use Interfaces.NRF52.GPIO;
+with Interfaces.NRF52.NVMC; use Interfaces.NRF52.NVMC;
+with Interfaces.NRF52.UICR; use Interfaces.NRF52.UICR;
+with Interfaces.NRF52.TEMP; use Interfaces.NRF52.TEMP;
+
+procedure Setup_Board is
+
+ ---------------------------
+ -- Board Configuration --
+ ---------------------------
+
+ Use_HFXO : constant Boolean := False;
+ -- Set to True to use the high-frequency external oscillator (HFXO).
+ -- When False, the on-chip oscillator is used.
+ -- The HFXO can also be turned on and off later by the main program.
+
+ LFCLK_Source : constant LFCLKSRC_SRC_Field := Xtal;
+ -- Selects the source for the LFCLK.
+ -- Xtal selects the external 32.768 kHz crystal (LFXO).
+ -- Rc selects the internal 32.768 kHz RC oscillator.
+ -- Synth selects the LFCLK synthesized from the 16 MHz HFCLK.
+
+ Use_SWO_Trace : constant Boolean := True;
+ -- Set to True to enable the SWO trace pins.
+
+ Use_Reset_Pin : constant Boolean := True;
+ -- When True, P0.18 will be configured as the reset pin.
+
+ LFRC_Used : constant Boolean := LFCLK_Source = Rc;
+ -- When the LFRC oscillator is not used it is put into ultra-low power mode
+
+ --------------------------
+ -- Errata Workarounds --
+ --------------------------
+
+ -- Some of these registers are not documented in the Objective Product Spec
+ -- but they are used in the nRF5 SDK startup code to detect when
+ -- certain errata are applicable.
+
+ Undocumented_Reg_1 : UInt32
+ with Address => System'To_Address (16#1000_0130#);
+
+ Undocumented_Reg_2 : UInt32
+ with Address => System'To_Address (16#1000_0134#);
+
+ -- Undocumented Registers used for the workaround of Erratas 98, 115, 120.
+ Errata_98_Reg : UInt32
+ with Volatile, Address => System'To_Address (16#4000_568C#);
+ Errata_115_Reg_1 : UInt32
+ with Volatile, Address => System'To_Address (16#4000_0EE4#);
+ Errata_115_Reg_2 : UInt32
+ with Volatile, Address => System'To_Address (16#1000_0258#);
+ Errata_120_Reg : UInt32
+ with Volatile, Address => System'To_Address (16#4002_9640#);
+
+ -- The POWER.RESETREAS register.
+ -- We define this here instead of including Interfaces.POWER as a
+ -- workaround for a warning about unused bits in the definition
+ -- of RAM_Cluster in the auto-generated code.
+ POWER_RESETREAS : UInt32
+ with Volatile, Address => System'To_Address (16#4000_0400#);
+
+ -- The following functions detect if different errata are applicable on
+ -- the specific MCU revision. For example, Errata_36 checks if a errata #36
+ -- is applicable ("CLOCK: Some registers are not reset when expected").
+
+ function Errata_36 return Boolean is
+ (Undocumented_Reg_1 = 8 and Undocumented_Reg_2 = 0)
+ with Inline_Always;
+
+ function Errata_66 return Boolean is
+ (Undocumented_Reg_1 = 8 and Undocumented_Reg_2 = 0)
+ with Inline_Always;
+
+ function Errata_98 return Boolean is
+ (Undocumented_Reg_1 = 8 and Undocumented_Reg_2 = 0)
+ with Inline_Always;
+
+ function Errata_103 return Boolean is
+ (Undocumented_Reg_1 = 8 and Undocumented_Reg_2 = 0)
+ with Inline_Always;
+
+ function Errata_115 return Boolean is
+ (Undocumented_Reg_1 = 8 and Undocumented_Reg_2 = 0)
+ with Inline_Always;
+
+ function Errata_120 return Boolean is
+ (Undocumented_Reg_1 = 8 and Undocumented_Reg_2 = 0)
+ with Inline_Always;
+
+ function Errata_136 return Boolean is
+ (Undocumented_Reg_1 = 8 and Undocumented_Reg_2 = 0)
+ with Inline_Always;
+
+ procedure NVIC_SystemReset;
+
+ procedure NVIC_SystemReset is
+ SCB_AIRCR : UInt32
+ with Volatile, Address => System'To_Address (16#E000_ED0C#);
+
+ VECTKEY : constant UInt32 := 16#05FA_0000#;
+
+ PRIGROUP_Mask : constant UInt32 := 16#0000_0700#;
+
+ SYSRESETREQ : constant UInt32 := 16#0000_0004#;
+
+ begin
+ -- Ensure all outstanding memory accesses including buffered write
+ -- are completed before reset
+ Asm ("dsb", Volatile => True);
+
+ SCB_AIRCR := VECTKEY or (SCB_AIRCR and PRIGROUP_Mask) or SYSRESETREQ;
+
+ Asm ("dsb", Volatile => True);
+
+ loop
+ null;
+ end loop;
+ end NVIC_SystemReset;
+
+begin
+
+ -- Enable SWO trace pins
+ if Use_SWO_Trace then
+ CLOCK_Periph.TRACECONFIG.TRACEMUX := Serial;
+ P1_Periph.PIN_CNF (0) := PIN_CNF_Register'
+ (DIR => Output,
+ INPUT => Connect,
+ PULL => Disabled,
+ Reserved_4_7 => 0,
+ DRIVE => H0H1,
+ Reserved_11_15 => 0,
+ SENSE => Disabled,
+ Reserved_18_31 => 0);
+ end if;
+
+ -- Workaround for Errata 36 "CLOCK: Some registers are not reset when
+ -- expected".
+ if Errata_36 then
+ CLOCK_Periph.EVENTS_DONE := (EVENTS_DONE => 0, others => <>);
+ CLOCK_Periph.EVENTS_CTTO := (EVENTS_CTTO => 0, others => <>);
+ CLOCK_Periph.CTIV.CTIV := 0;
+ end if;
+
+ -- Workaround for Errata 66 "TEMP: Linearity specification not met with
+ -- default settings"
+ if Errata_66 then
+ TEMP_Periph.A0.A0 := FICR_Periph.TEMP.A0.A;
+ TEMP_Periph.A1.A1 := FICR_Periph.TEMP.A1.A;
+ TEMP_Periph.A2.A2 := FICR_Periph.TEMP.A2.A;
+ TEMP_Periph.A3.A3 := FICR_Periph.TEMP.A3.A;
+ TEMP_Periph.A4.A4 := FICR_Periph.TEMP.A4.A;
+ TEMP_Periph.A5.A5 := FICR_Periph.TEMP.A5.A;
+ TEMP_Periph.B0.B0 := FICR_Periph.TEMP.B0.B;
+ TEMP_Periph.B1.B1 := FICR_Periph.TEMP.B1.B;
+ TEMP_Periph.B2.B2 := FICR_Periph.TEMP.B2.B;
+ TEMP_Periph.B3.B3 := FICR_Periph.TEMP.B3.B;
+ TEMP_Periph.B4.B4 := FICR_Periph.TEMP.B4.B;
+ TEMP_Periph.B5.B5 := FICR_Periph.TEMP.B5.B;
+ TEMP_Periph.T0.T0 := FICR_Periph.TEMP.T0.T;
+ TEMP_Periph.T1.T1 := FICR_Periph.TEMP.T1.T;
+ TEMP_Periph.T2.T2 := FICR_Periph.TEMP.T2.T;
+ TEMP_Periph.T3.T3 := FICR_Periph.TEMP.T3.T;
+ TEMP_Periph.T4.T4 := FICR_Periph.TEMP.T4.T;
+ end if;
+
+ -- Workaround for Errata 98 "NFCT: Not able to communicate with the peer"
+ if Errata_98 then
+ Errata_98_Reg := 16#0003_8148#;
+ end if;
+
+ -- Workaround for Errata 103 "CCM: Wrong reset value of CCM MAXPACKETSIZE"
+ if Errata_103 then
+ CCM_Periph.MAXPACKETSIZE.MAXPACKETSIZE := 16#FB#;
+ end if;
+
+ -- Workaround for Errata 115 "RAM: RAM content cannot be trusted upon
+ -- waking up from System ON Idle or System OFF mode"
+ if Errata_115 then
+ Errata_115_Reg_1 := ((Errata_115_Reg_1 and 16#FFFF_FFF0#)
+ or (Errata_115_Reg_2 and 16#0000_000F#));
+ end if;
+
+ -- Workaround for Errata 120 "QSPI: Data read or written is corrupted"
+ if Errata_120 then
+ Errata_120_Reg := 16#200#;
+ end if;
+
+ -- Workaround for Errata 136 "System: Bits in RESETREAS are set when they
+ -- should not be"
+ if Errata_136 then
+ -- Clear all flags except RESETPIN if RESETPIN is the reset reason
+ if (POWER_RESETREAS and 16#0000_0001#) /= 0 then
+ POWER_RESETREAS := 16#FFFF_FFFE#;
+ end if;
+ end if;
+
+ if Use_Reset_Pin then
+ -- Enable nRESET pin on P0.18
+ if UICR_Periph.PSELRESET (0).CONNECT = Disconnected or
+ UICR_Periph.PSELRESET (1).CONNECT = Disconnected
+ then
+ NVMC_Periph.CONFIG := CONFIG_Register'
+ (WEN => Wen,
+ Reserved_2_31 => 0);
+ loop
+ exit when NVMC_Periph.READY.READY = Ready;
+ end loop;
+
+ UICR_Periph.PSELRESET (0) := PSELRESET_Register'
+ (PIN => 18,
+ PORT => 0,
+ Reserved_6_30 => 0,
+ CONNECT => Connected);
+ loop
+ exit when NVMC_Periph.READY.READY = Ready;
+ end loop;
+
+ UICR_Periph.PSELRESET (1) := PSELRESET_Register'
+ (PIN => 18,
+ PORT => 0,
+ Reserved_6_30 => 0,
+ CONNECT => Connected);
+ loop
+ exit when NVMC_Periph.READY.READY = Ready;
+ end loop;
+
+ NVMC_Periph.CONFIG := CONFIG_Register'
+ (WEN => Ren,
+ Reserved_2_31 => 0);
+ loop
+ exit when NVMC_Periph.READY.READY = Ready;
+ end loop;
+
+ NVIC_SystemReset;
+ end if;
+ end if;
+
+ -- Configure the 32.768 kHz external crystal.
+ -- The LFCLK will be started later, if required by the runtime.
+ --
+ -- The Ravenscar runtime uses LFCLK as its timing source for task delays,
+ -- so LFCLK will be started by System.BB.Board_Support.Initialize_Board.
+ --
+ -- The ZFP runtime does not use LFCLK, so it is not started in ZFP.
+ CLOCK_Periph.LFCLKSRC := LFCLKSRC_Register'
+ (SRC => LFCLK_Source,
+ Reserved_2_15 => 0,
+ BYPASS => Disabled,
+ EXTERNAL => Disabled,
+ Reserved_18_31 => 0);
+
+ -- If the internal RC oscillator is not used as the LFCLK source, then
+ -- put it into ultra-low power (ULP) mode to save some power.
+ if not LFRC_Used then
+ CLOCK_Periph.LFRCMODE.MODE := Ulp;
+ end if;
+
+ -- Optionally enable the external HFXO.
+ -- If HFXO is disabled, then the HFCLK will use the internal HF oscillator
+ if Use_HFXO then
+ CLOCK_Periph.TASKS_HFCLKSTART := (TASKS_HFCLKSTART => 1,
+ others => <>);
+ end if;
+end Setup_Board;
diff --git a/arm/nordic/nrf52/nrf52840/svd/a-intnam.ads b/arm/nordic/nrf52/nrf52840/svd/a-intnam.ads
new file mode 100644
index 00000000..a784bec1
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52840/svd/a-intnam.ads
@@ -0,0 +1,104 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update
+-- for such product, must reproduce the above copyright notice, this list
+-- of conditions and the following disclaimer in the documentation and/or
+-- other materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from
+-- this software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52840.svd
+
+-- This is a version for the nRF52840 reference description for radio MCU with
+-- ARM 32-bit Cortex-M4 Microcontroller MCU
+package Ada.Interrupts.Names is
+
+ -- All identifiers in this unit are implementation defined
+
+ pragma Implementation_Defined;
+
+ ----------------
+ -- Interrupts --
+ ----------------
+
+ -- System tick
+ Sys_Tick_Interrupt : constant Interrupt_ID := -1;
+ POWER_CLOCK_Interrupt : constant Interrupt_ID := 0;
+ RADIO_Interrupt : constant Interrupt_ID := 1;
+ UARTE0_UART0_Interrupt : constant Interrupt_ID := 2;
+ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_Interrupt : constant Interrupt_ID := 3;
+ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_Interrupt : constant Interrupt_ID := 4;
+ NFCT_Interrupt : constant Interrupt_ID := 5;
+ GPIOTE_Interrupt : constant Interrupt_ID := 6;
+ SAADC_Interrupt : constant Interrupt_ID := 7;
+ TIMER0_Interrupt : constant Interrupt_ID := 8;
+ TIMER1_Interrupt : constant Interrupt_ID := 9;
+ TIMER2_Interrupt : constant Interrupt_ID := 10;
+ RTC0_Interrupt : constant Interrupt_ID := 11;
+ TEMP_Interrupt : constant Interrupt_ID := 12;
+ RNG_Interrupt : constant Interrupt_ID := 13;
+ ECB_Interrupt : constant Interrupt_ID := 14;
+ CCM_AAR_Interrupt : constant Interrupt_ID := 15;
+ WDT_Interrupt : constant Interrupt_ID := 16;
+ RTC1_Interrupt : constant Interrupt_ID := 17;
+ QDEC_Interrupt : constant Interrupt_ID := 18;
+ COMP_LPCOMP_Interrupt : constant Interrupt_ID := 19;
+ SWI0_EGU0_Interrupt : constant Interrupt_ID := 20;
+ SWI1_EGU1_Interrupt : constant Interrupt_ID := 21;
+ SWI2_EGU2_Interrupt : constant Interrupt_ID := 22;
+ SWI3_EGU3_Interrupt : constant Interrupt_ID := 23;
+ SWI4_EGU4_Interrupt : constant Interrupt_ID := 24;
+ SWI5_EGU5_Interrupt : constant Interrupt_ID := 25;
+ TIMER3_Interrupt : constant Interrupt_ID := 26;
+ TIMER4_Interrupt : constant Interrupt_ID := 27;
+ PWM0_Interrupt : constant Interrupt_ID := 28;
+ PDM_Interrupt : constant Interrupt_ID := 29;
+ MWU_Interrupt : constant Interrupt_ID := 32;
+ PWM1_Interrupt : constant Interrupt_ID := 33;
+ PWM2_Interrupt : constant Interrupt_ID := 34;
+ SPIM2_SPIS2_SPI2_Interrupt : constant Interrupt_ID := 35;
+ RTC2_Interrupt : constant Interrupt_ID := 36;
+ I2S_Interrupt : constant Interrupt_ID := 37;
+ FPU_Interrupt : constant Interrupt_ID := 38;
+ USBD_Interrupt : constant Interrupt_ID := 39;
+ UARTE1_Interrupt : constant Interrupt_ID := 40;
+ QSPI_Interrupt : constant Interrupt_ID := 41;
+ CRYPTOCELL_Interrupt : constant Interrupt_ID := 42;
+ PWM3_Interrupt : constant Interrupt_ID := 45;
+ SPIM3_Interrupt : constant Interrupt_ID := 47;
+
+end Ada.Interrupts.Names;
diff --git a/arm/nordic/nrf52/nrf52840/svd/handler.S b/arm/nordic/nrf52/nrf52840/svd/handler.S
new file mode 100644
index 00000000..4813a6c9
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52840/svd/handler.S
@@ -0,0 +1,112 @@
+## -*- asm -*- #############################
+# Automatically generated by SVD2Ada
+# For the nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller target
+############################################
+
+ .syntax unified
+ .cpu cortex-m4
+ .thumb
+
+ .text
+ .globl __vectors
+ .p2align 8
+__vectors:
+ /* Cortex-M core interrupts */
+ .word 0 /* stack top address */
+ .word fault /* 1 Reset. */
+ .word fault /* 2 NMI. */
+ .word fault /* 3 Hard fault. */
+ .word fault /* 4 Mem manage. */
+ .word fault /* 5 Bus fault. */
+ .word fault /* 6 Usage fault. */
+ .word fault /* 7 reserved. */
+ .word fault /* 8 reserved. */
+ .word fault /* 9 reserved. */
+ .word fault /* 10 reserved. */
+ .word __gnat_sv_call_trap /* 11 SVCall. */
+ .word __gnat_bkpt_trap /* 12 Breakpoint. */
+ .word fault /* 13 reserved. */
+ .word __gnat_pend_sv_trap /* 14 PendSV. */
+ .word __gnat_sys_tick_trap /* 15 Systick. */
+ /* MCU interrupts */
+ .word __gnat_irq_trap /* 16 POWER_CLOCK */
+ .word __gnat_irq_trap /* 17 RADIO */
+ .word __gnat_irq_trap /* 18 UARTE0_UART0 */
+ .word __gnat_irq_trap /* 19 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */
+ .word __gnat_irq_trap /* 20 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */
+ .word __gnat_irq_trap /* 21 NFCT */
+ .word __gnat_irq_trap /* 22 GPIOTE */
+ .word __gnat_irq_trap /* 23 SAADC */
+ .word __gnat_irq_trap /* 24 TIMER0 */
+ .word __gnat_irq_trap /* 25 TIMER1 */
+ .word __gnat_irq_trap /* 26 TIMER2 */
+ .word __gnat_irq_trap /* 27 RTC0 */
+ .word __gnat_irq_trap /* 28 TEMP */
+ .word __gnat_irq_trap /* 29 RNG */
+ .word __gnat_irq_trap /* 30 ECB */
+ .word __gnat_irq_trap /* 31 CCM_AAR */
+ .word __gnat_irq_trap /* 32 WDT */
+ .word __gnat_irq_trap /* 33 RTC1 */
+ .word __gnat_irq_trap /* 34 QDEC */
+ .word __gnat_irq_trap /* 35 COMP_LPCOMP */
+ .word __gnat_irq_trap /* 36 SWI0_EGU0 */
+ .word __gnat_irq_trap /* 37 SWI1_EGU1 */
+ .word __gnat_irq_trap /* 38 SWI2_EGU2 */
+ .word __gnat_irq_trap /* 39 SWI3_EGU3 */
+ .word __gnat_irq_trap /* 40 SWI4_EGU4 */
+ .word __gnat_irq_trap /* 41 SWI5_EGU5 */
+ .word __gnat_irq_trap /* 42 TIMER3 */
+ .word __gnat_irq_trap /* 43 TIMER4 */
+ .word __gnat_irq_trap /* 44 PWM0 */
+ .word __gnat_irq_trap /* 45 PDM */
+ .word __gnat_irq_trap /* 46 IRQ 30. */
+ .word __gnat_irq_trap /* 47 IRQ 31. */
+ .word __gnat_irq_trap /* 48 MWU */
+ .word __gnat_irq_trap /* 49 PWM1 */
+ .word __gnat_irq_trap /* 50 PWM2 */
+ .word __gnat_irq_trap /* 51 SPIM2_SPIS2_SPI2 */
+ .word __gnat_irq_trap /* 52 RTC2 */
+ .word __gnat_irq_trap /* 53 I2S */
+ .word __gnat_irq_trap /* 54 FPU */
+ .word __gnat_irq_trap /* 55 USBD */
+ .word __gnat_irq_trap /* 56 UARTE1 */
+ .word __gnat_irq_trap /* 57 QSPI */
+ .word __gnat_irq_trap /* 58 CRYPTOCELL */
+ .word __gnat_irq_trap /* 59 IRQ 43. */
+ .word __gnat_irq_trap /* 60 IRQ 44. */
+ .word __gnat_irq_trap /* 61 PWM3 */
+ .word __gnat_irq_trap /* 62 IRQ 46. */
+ .word __gnat_irq_trap /* 63 SPIM3 */
+
+ .text
+
+ .thumb_func
+.weak __gnat_irq_trap
+.type __gnat_irq_trap, %function
+__gnat_irq_trap:
+0: b 0b
+ .size __gnat_irq_trap, . - __gnat_irq_trap
+
+ .thumb_func
+.weak __gnat_sv_call_trap
+.type __gnat_sv_call_trap, %function
+__gnat_sv_call_trap:
+0: b 0b
+ .size __gnat_sv_call_trap, . - __gnat_sv_call_trap
+
+ .thumb_func
+.weak __gnat_pend_sv_trap
+.type __gnat_pend_sv_trap, %function
+__gnat_pend_sv_trap:
+0: b 0b
+ .size __gnat_pend_sv_trap, . - __gnat_pend_sv_trap
+
+ .thumb_func
+.weak __gnat_sys_tick_trap
+.type __gnat_sys_tick_trap, %function
+__gnat_sys_tick_trap:
+0: b 0b
+ .size __gnat_sys_tick_trap, . - __gnat_sys_tick_trap
+
+ .thumb_func
+fault: b fault
diff --git a/arm/nordic/nrf52/nrf52840/svd/i-nrf52-ccm.ads b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-ccm.ads
new file mode 100644
index 00000000..a03865dd
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-ccm.ads
@@ -0,0 +1,638 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update
+-- for such product, must reproduce the above copyright notice, this list
+-- of conditions and the following disclaimer in the documentation and/or
+-- other materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from
+-- this software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52840.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.CCM is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ subtype TASKS_KSGEN_TASKS_KSGEN_Field is Interfaces.NRF52.Bit;
+
+ -- Start generation of key-stream. This operation will stop by itself when
+ -- completed.
+ type TASKS_KSGEN_Register is record
+ -- Write-only.
+ TASKS_KSGEN : TASKS_KSGEN_TASKS_KSGEN_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_KSGEN_Register use record
+ TASKS_KSGEN at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_CRYPT_TASKS_CRYPT_Field is Interfaces.NRF52.Bit;
+
+ -- Start encryption/decryption. This operation will stop by itself when
+ -- completed.
+ type TASKS_CRYPT_Register is record
+ -- Write-only.
+ TASKS_CRYPT : TASKS_CRYPT_TASKS_CRYPT_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_CRYPT_Register use record
+ TASKS_CRYPT at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_STOP_TASKS_STOP_Field is Interfaces.NRF52.Bit;
+
+ -- Stop encryption/decryption
+ type TASKS_STOP_Register is record
+ -- Write-only.
+ TASKS_STOP : TASKS_STOP_TASKS_STOP_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_STOP_Register use record
+ TASKS_STOP at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Field is Interfaces.NRF52.Bit;
+
+ -- Override DATARATE setting in MODE register with the contents of the
+ -- RATEOVERRIDE register for any ongoing encryption/decryption
+ type TASKS_RATEOVERRIDE_Register is record
+ -- Write-only.
+ TASKS_RATEOVERRIDE : TASKS_RATEOVERRIDE_TASKS_RATEOVERRIDE_Field :=
+ 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_RATEOVERRIDE_Register use record
+ TASKS_RATEOVERRIDE at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Field is Interfaces.NRF52.Bit;
+
+ -- Key-stream generation complete
+ type EVENTS_ENDKSGEN_Register is record
+ EVENTS_ENDKSGEN : EVENTS_ENDKSGEN_EVENTS_ENDKSGEN_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_ENDKSGEN_Register use record
+ EVENTS_ENDKSGEN at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Field is Interfaces.NRF52.Bit;
+
+ -- Encrypt/decrypt complete
+ type EVENTS_ENDCRYPT_Register is record
+ EVENTS_ENDCRYPT : EVENTS_ENDCRYPT_EVENTS_ENDCRYPT_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_ENDCRYPT_Register use record
+ EVENTS_ENDCRYPT at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_ERROR_EVENTS_ERROR_Field is Interfaces.NRF52.Bit;
+
+ -- Deprecated register - CCM error event
+ type EVENTS_ERROR_Register is record
+ EVENTS_ERROR : EVENTS_ERROR_EVENTS_ERROR_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_ERROR_Register use record
+ EVENTS_ERROR at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Shortcut between ENDKSGEN event and CRYPT task
+ type SHORTS_ENDKSGEN_CRYPT_Field is
+ (-- Disable shortcut
+ Disabled,
+ -- Enable shortcut
+ Enabled)
+ with Size => 1;
+ for SHORTS_ENDKSGEN_CRYPT_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Shortcut register
+ type SHORTS_Register is record
+ -- Shortcut between ENDKSGEN event and CRYPT task
+ ENDKSGEN_CRYPT : SHORTS_ENDKSGEN_CRYPT_Field :=
+ Interfaces.NRF52.CCM.Disabled;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for SHORTS_Register use record
+ ENDKSGEN_CRYPT at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Write '1' to enable interrupt for ENDKSGEN event
+ type INTENSET_ENDKSGEN_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_ENDKSGEN_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable interrupt for ENDKSGEN event
+ type INTENSET_ENDKSGEN_Field_1 is
+ (-- Reset value for the field
+ Intenset_Endksgen_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_ENDKSGEN_Field_1 use
+ (Intenset_Endksgen_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to enable interrupt for ENDCRYPT event
+ type INTENSET_ENDCRYPT_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_ENDCRYPT_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable interrupt for ENDCRYPT event
+ type INTENSET_ENDCRYPT_Field_1 is
+ (-- Reset value for the field
+ Intenset_Endcrypt_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_ENDCRYPT_Field_1 use
+ (Intenset_Endcrypt_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to enable interrupt for ERROR event
+ type INTENSET_ERROR_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_ERROR_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable interrupt for ERROR event
+ type INTENSET_ERROR_Field_1 is
+ (-- Reset value for the field
+ Intenset_Error_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_ERROR_Field_1 use
+ (Intenset_Error_Field_Reset => 0,
+ Set => 1);
+
+ -- Enable interrupt
+ type INTENSET_Register is record
+ -- Write '1' to enable interrupt for ENDKSGEN event
+ ENDKSGEN : INTENSET_ENDKSGEN_Field_1 :=
+ Intenset_Endksgen_Field_Reset;
+ -- Write '1' to enable interrupt for ENDCRYPT event
+ ENDCRYPT : INTENSET_ENDCRYPT_Field_1 :=
+ Intenset_Endcrypt_Field_Reset;
+ -- Write '1' to enable interrupt for ERROR event
+ ERROR : INTENSET_ERROR_Field_1 := Intenset_Error_Field_Reset;
+ -- unspecified
+ Reserved_3_31 : Interfaces.NRF52.UInt29 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENSET_Register use record
+ ENDKSGEN at 0 range 0 .. 0;
+ ENDCRYPT at 0 range 1 .. 1;
+ ERROR at 0 range 2 .. 2;
+ Reserved_3_31 at 0 range 3 .. 31;
+ end record;
+
+ -- Write '1' to disable interrupt for ENDKSGEN event
+ type INTENCLR_ENDKSGEN_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_ENDKSGEN_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable interrupt for ENDKSGEN event
+ type INTENCLR_ENDKSGEN_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Endksgen_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_ENDKSGEN_Field_1 use
+ (Intenclr_Endksgen_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to disable interrupt for ENDCRYPT event
+ type INTENCLR_ENDCRYPT_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_ENDCRYPT_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable interrupt for ENDCRYPT event
+ type INTENCLR_ENDCRYPT_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Endcrypt_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_ENDCRYPT_Field_1 use
+ (Intenclr_Endcrypt_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to disable interrupt for ERROR event
+ type INTENCLR_ERROR_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_ERROR_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable interrupt for ERROR event
+ type INTENCLR_ERROR_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Error_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_ERROR_Field_1 use
+ (Intenclr_Error_Field_Reset => 0,
+ Clear => 1);
+
+ -- Disable interrupt
+ type INTENCLR_Register is record
+ -- Write '1' to disable interrupt for ENDKSGEN event
+ ENDKSGEN : INTENCLR_ENDKSGEN_Field_1 :=
+ Intenclr_Endksgen_Field_Reset;
+ -- Write '1' to disable interrupt for ENDCRYPT event
+ ENDCRYPT : INTENCLR_ENDCRYPT_Field_1 :=
+ Intenclr_Endcrypt_Field_Reset;
+ -- Write '1' to disable interrupt for ERROR event
+ ERROR : INTENCLR_ERROR_Field_1 := Intenclr_Error_Field_Reset;
+ -- unspecified
+ Reserved_3_31 : Interfaces.NRF52.UInt29 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENCLR_Register use record
+ ENDKSGEN at 0 range 0 .. 0;
+ ENDCRYPT at 0 range 1 .. 1;
+ ERROR at 0 range 2 .. 2;
+ Reserved_3_31 at 0 range 3 .. 31;
+ end record;
+
+ -- The result of the MIC check performed during the previous decryption
+ -- operation
+ type MICSTATUS_MICSTATUS_Field is
+ (-- MIC check failed
+ Checkfailed,
+ -- MIC check passed
+ Checkpassed)
+ with Size => 1;
+ for MICSTATUS_MICSTATUS_Field use
+ (Checkfailed => 0,
+ Checkpassed => 1);
+
+ -- MIC check result
+ type MICSTATUS_Register is record
+ -- Read-only. The result of the MIC check performed during the previous
+ -- decryption operation
+ MICSTATUS : MICSTATUS_MICSTATUS_Field;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for MICSTATUS_Register use record
+ MICSTATUS at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Enable or disable CCM
+ type ENABLE_ENABLE_Field is
+ (-- Disable
+ Disabled,
+ -- Enable
+ Enabled)
+ with Size => 2;
+ for ENABLE_ENABLE_Field use
+ (Disabled => 0,
+ Enabled => 2);
+
+ -- Enable
+ type ENABLE_Register is record
+ -- Enable or disable CCM
+ ENABLE : ENABLE_ENABLE_Field := Interfaces.NRF52.CCM.Disabled;
+ -- unspecified
+ Reserved_2_31 : Interfaces.NRF52.UInt30 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for ENABLE_Register use record
+ ENABLE at 0 range 0 .. 1;
+ Reserved_2_31 at 0 range 2 .. 31;
+ end record;
+
+ -- The mode of operation to be used. The settings in this register apply
+ -- whenever either the KSGEN or CRYPT tasks are triggered.
+ type MODE_MODE_Field is
+ (-- AES CCM packet encryption mode
+ Encryption,
+ -- AES CCM packet decryption mode
+ Decryption)
+ with Size => 1;
+ for MODE_MODE_Field use
+ (Encryption => 0,
+ Decryption => 1);
+
+ -- Radio data rate that the CCM shall run synchronous with
+ type MODE_DATARATE_Field is
+ (-- 1 Mbps
+ Val_1Mbit,
+ -- 2 Mbps
+ Val_2Mbit,
+ -- 125 Kbps
+ Val_125Kbps,
+ -- 500 Kbps
+ Val_500Kbps)
+ with Size => 2;
+ for MODE_DATARATE_Field use
+ (Val_1Mbit => 0,
+ Val_2Mbit => 1,
+ Val_125Kbps => 2,
+ Val_500Kbps => 3);
+
+ -- Packet length configuration
+ type MODE_LENGTH_Field is
+ (-- Default length. Effective length of LENGTH field in encrypted/decrypted
+-- packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be
+-- generated.
+ Default,
+ -- Extended length. Effective length of LENGTH field in encrypted/decrypted
+-- packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE
+-- bytes will be generated.
+ Extended)
+ with Size => 1;
+ for MODE_LENGTH_Field use
+ (Default => 0,
+ Extended => 1);
+
+ -- Operation mode
+ type MODE_Register is record
+ -- The mode of operation to be used. The settings in this register apply
+ -- whenever either the KSGEN or CRYPT tasks are triggered.
+ MODE : MODE_MODE_Field := Interfaces.NRF52.CCM.Decryption;
+ -- unspecified
+ Reserved_1_15 : Interfaces.NRF52.UInt15 := 16#0#;
+ -- Radio data rate that the CCM shall run synchronous with
+ DATARATE : MODE_DATARATE_Field := Interfaces.NRF52.CCM.Val_1Mbit;
+ -- unspecified
+ Reserved_18_23 : Interfaces.NRF52.UInt6 := 16#0#;
+ -- Packet length configuration
+ LENGTH : MODE_LENGTH_Field := Interfaces.NRF52.CCM.Default;
+ -- unspecified
+ Reserved_25_31 : Interfaces.NRF52.UInt7 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for MODE_Register use record
+ MODE at 0 range 0 .. 0;
+ Reserved_1_15 at 0 range 1 .. 15;
+ DATARATE at 0 range 16 .. 17;
+ Reserved_18_23 at 0 range 18 .. 23;
+ LENGTH at 0 range 24 .. 24;
+ Reserved_25_31 at 0 range 25 .. 31;
+ end record;
+
+ subtype MAXPACKETSIZE_MAXPACKETSIZE_Field is Interfaces.NRF52.Byte;
+
+ -- Length of key-stream generated when MODE.LENGTH = Extended.
+ type MAXPACKETSIZE_Register is record
+ -- Length of key-stream generated when MODE.LENGTH = Extended. This
+ -- value must be greater or equal to the subsequent packet payload to be
+ -- encrypted/decrypted.
+ MAXPACKETSIZE : MAXPACKETSIZE_MAXPACKETSIZE_Field := 16#FB#;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for MAXPACKETSIZE_Register use record
+ MAXPACKETSIZE at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ -- Data rate override setting.
+ type RATEOVERRIDE_RATEOVERRIDE_Field is
+ (-- 1 Mbps
+ Val_1Mbit,
+ -- 2 Mbps
+ Val_2Mbit,
+ -- 125 Kbps
+ Val_125Kbps,
+ -- 500 Kbps
+ Val_500Kbps)
+ with Size => 2;
+ for RATEOVERRIDE_RATEOVERRIDE_Field use
+ (Val_1Mbit => 0,
+ Val_2Mbit => 1,
+ Val_125Kbps => 2,
+ Val_500Kbps => 3);
+
+ -- Data rate override setting.
+ type RATEOVERRIDE_Register is record
+ -- Data rate override setting.
+ RATEOVERRIDE : RATEOVERRIDE_RATEOVERRIDE_Field :=
+ Interfaces.NRF52.CCM.Val_1Mbit;
+ -- unspecified
+ Reserved_2_31 : Interfaces.NRF52.UInt30 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for RATEOVERRIDE_Register use record
+ RATEOVERRIDE at 0 range 0 .. 1;
+ Reserved_2_31 at 0 range 2 .. 31;
+ end record;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ -- AES CCM Mode Encryption
+ type CCM_Peripheral is record
+ -- Start generation of key-stream. This operation will stop by itself
+ -- when completed.
+ TASKS_KSGEN : aliased TASKS_KSGEN_Register;
+ -- Start encryption/decryption. This operation will stop by itself when
+ -- completed.
+ TASKS_CRYPT : aliased TASKS_CRYPT_Register;
+ -- Stop encryption/decryption
+ TASKS_STOP : aliased TASKS_STOP_Register;
+ -- Override DATARATE setting in MODE register with the contents of the
+ -- RATEOVERRIDE register for any ongoing encryption/decryption
+ TASKS_RATEOVERRIDE : aliased TASKS_RATEOVERRIDE_Register;
+ -- Key-stream generation complete
+ EVENTS_ENDKSGEN : aliased EVENTS_ENDKSGEN_Register;
+ -- Encrypt/decrypt complete
+ EVENTS_ENDCRYPT : aliased EVENTS_ENDCRYPT_Register;
+ -- Deprecated register - CCM error event
+ EVENTS_ERROR : aliased EVENTS_ERROR_Register;
+ -- Shortcut register
+ SHORTS : aliased SHORTS_Register;
+ -- Enable interrupt
+ INTENSET : aliased INTENSET_Register;
+ -- Disable interrupt
+ INTENCLR : aliased INTENCLR_Register;
+ -- MIC check result
+ MICSTATUS : aliased MICSTATUS_Register;
+ -- Enable
+ ENABLE : aliased ENABLE_Register;
+ -- Operation mode
+ MODE : aliased MODE_Register;
+ -- Pointer to data structure holding AES key and NONCE vector
+ CNFPTR : aliased Interfaces.NRF52.UInt32;
+ -- Input pointer
+ INPTR : aliased Interfaces.NRF52.UInt32;
+ -- Output pointer
+ OUTPTR : aliased Interfaces.NRF52.UInt32;
+ -- Pointer to data area used for temporary storage
+ SCRATCHPTR : aliased Interfaces.NRF52.UInt32;
+ -- Length of key-stream generated when MODE.LENGTH = Extended.
+ MAXPACKETSIZE : aliased MAXPACKETSIZE_Register;
+ -- Data rate override setting.
+ RATEOVERRIDE : aliased RATEOVERRIDE_Register;
+ end record
+ with Volatile;
+
+ for CCM_Peripheral use record
+ TASKS_KSGEN at 16#0# range 0 .. 31;
+ TASKS_CRYPT at 16#4# range 0 .. 31;
+ TASKS_STOP at 16#8# range 0 .. 31;
+ TASKS_RATEOVERRIDE at 16#C# range 0 .. 31;
+ EVENTS_ENDKSGEN at 16#100# range 0 .. 31;
+ EVENTS_ENDCRYPT at 16#104# range 0 .. 31;
+ EVENTS_ERROR at 16#108# range 0 .. 31;
+ SHORTS at 16#200# range 0 .. 31;
+ INTENSET at 16#304# range 0 .. 31;
+ INTENCLR at 16#308# range 0 .. 31;
+ MICSTATUS at 16#400# range 0 .. 31;
+ ENABLE at 16#500# range 0 .. 31;
+ MODE at 16#504# range 0 .. 31;
+ CNFPTR at 16#508# range 0 .. 31;
+ INPTR at 16#50C# range 0 .. 31;
+ OUTPTR at 16#510# range 0 .. 31;
+ SCRATCHPTR at 16#514# range 0 .. 31;
+ MAXPACKETSIZE at 16#518# range 0 .. 31;
+ RATEOVERRIDE at 16#51C# range 0 .. 31;
+ end record;
+
+ -- AES CCM Mode Encryption
+ CCM_Periph : aliased CCM_Peripheral
+ with Import, Address => CCM_Base;
+
+end Interfaces.NRF52.CCM;
diff --git a/arm/nordic/nrf52/nrf52840/svd/i-nrf52-clock.ads b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-clock.ads
new file mode 100644
index 00000000..2fb66a19
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-clock.ads
@@ -0,0 +1,1096 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update
+-- for such product, must reproduce the above copyright notice, this list
+-- of conditions and the following disclaimer in the documentation and/or
+-- other materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from
+-- this software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52840.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.CLOCK is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ subtype TASKS_HFCLKSTART_TASKS_HFCLKSTART_Field is Interfaces.NRF52.Bit;
+
+ -- Start HFXO crystal oscillator
+ type TASKS_HFCLKSTART_Register is record
+ -- Write-only.
+ TASKS_HFCLKSTART : TASKS_HFCLKSTART_TASKS_HFCLKSTART_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_HFCLKSTART_Register use record
+ TASKS_HFCLKSTART at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Field is Interfaces.NRF52.Bit;
+
+ -- Stop HFXO crystal oscillator
+ type TASKS_HFCLKSTOP_Register is record
+ -- Write-only.
+ TASKS_HFCLKSTOP : TASKS_HFCLKSTOP_TASKS_HFCLKSTOP_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_HFCLKSTOP_Register use record
+ TASKS_HFCLKSTOP at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_LFCLKSTART_TASKS_LFCLKSTART_Field is Interfaces.NRF52.Bit;
+
+ -- Start LFCLK
+ type TASKS_LFCLKSTART_Register is record
+ -- Write-only.
+ TASKS_LFCLKSTART : TASKS_LFCLKSTART_TASKS_LFCLKSTART_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_LFCLKSTART_Register use record
+ TASKS_LFCLKSTART at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Field is Interfaces.NRF52.Bit;
+
+ -- Stop LFCLK
+ type TASKS_LFCLKSTOP_Register is record
+ -- Write-only.
+ TASKS_LFCLKSTOP : TASKS_LFCLKSTOP_TASKS_LFCLKSTOP_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_LFCLKSTOP_Register use record
+ TASKS_LFCLKSTOP at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_CAL_TASKS_CAL_Field is Interfaces.NRF52.Bit;
+
+ -- Start calibration of LFRC
+ type TASKS_CAL_Register is record
+ -- Write-only.
+ TASKS_CAL : TASKS_CAL_TASKS_CAL_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_CAL_Register use record
+ TASKS_CAL at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_CTSTART_TASKS_CTSTART_Field is Interfaces.NRF52.Bit;
+
+ -- Start calibration timer
+ type TASKS_CTSTART_Register is record
+ -- Write-only.
+ TASKS_CTSTART : TASKS_CTSTART_TASKS_CTSTART_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_CTSTART_Register use record
+ TASKS_CTSTART at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_CTSTOP_TASKS_CTSTOP_Field is Interfaces.NRF52.Bit;
+
+ -- Stop calibration timer
+ type TASKS_CTSTOP_Register is record
+ -- Write-only.
+ TASKS_CTSTOP : TASKS_CTSTOP_TASKS_CTSTOP_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_CTSTOP_Register use record
+ TASKS_CTSTOP at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Field is
+ Interfaces.NRF52.Bit;
+
+ -- HFXO crystal oscillator started
+ type EVENTS_HFCLKSTARTED_Register is record
+ EVENTS_HFCLKSTARTED : EVENTS_HFCLKSTARTED_EVENTS_HFCLKSTARTED_Field :=
+ 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_HFCLKSTARTED_Register use record
+ EVENTS_HFCLKSTARTED at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Field is
+ Interfaces.NRF52.Bit;
+
+ -- LFCLK started
+ type EVENTS_LFCLKSTARTED_Register is record
+ EVENTS_LFCLKSTARTED : EVENTS_LFCLKSTARTED_EVENTS_LFCLKSTARTED_Field :=
+ 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_LFCLKSTARTED_Register use record
+ EVENTS_LFCLKSTARTED at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_DONE_EVENTS_DONE_Field is Interfaces.NRF52.Bit;
+
+ -- Calibration of LFRC completed
+ type EVENTS_DONE_Register is record
+ EVENTS_DONE : EVENTS_DONE_EVENTS_DONE_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_DONE_Register use record
+ EVENTS_DONE at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_CTTO_EVENTS_CTTO_Field is Interfaces.NRF52.Bit;
+
+ -- Calibration timer timeout
+ type EVENTS_CTTO_Register is record
+ EVENTS_CTTO : EVENTS_CTTO_EVENTS_CTTO_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_CTTO_Register use record
+ EVENTS_CTTO at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_CTSTARTED_EVENTS_CTSTARTED_Field is Interfaces.NRF52.Bit;
+
+ -- Calibration timer has been started and is ready to process new tasks
+ type EVENTS_CTSTARTED_Register is record
+ EVENTS_CTSTARTED : EVENTS_CTSTARTED_EVENTS_CTSTARTED_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_CTSTARTED_Register use record
+ EVENTS_CTSTARTED at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Field is Interfaces.NRF52.Bit;
+
+ -- Calibration timer has been stopped and is ready to process new tasks
+ type EVENTS_CTSTOPPED_Register is record
+ EVENTS_CTSTOPPED : EVENTS_CTSTOPPED_EVENTS_CTSTOPPED_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_CTSTOPPED_Register use record
+ EVENTS_CTSTOPPED at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Write '1' to enable interrupt for HFCLKSTARTED event
+ type INTENSET_HFCLKSTARTED_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_HFCLKSTARTED_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable interrupt for HFCLKSTARTED event
+ type INTENSET_HFCLKSTARTED_Field_1 is
+ (-- Reset value for the field
+ Intenset_Hfclkstarted_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_HFCLKSTARTED_Field_1 use
+ (Intenset_Hfclkstarted_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to enable interrupt for LFCLKSTARTED event
+ type INTENSET_LFCLKSTARTED_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_LFCLKSTARTED_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable interrupt for LFCLKSTARTED event
+ type INTENSET_LFCLKSTARTED_Field_1 is
+ (-- Reset value for the field
+ Intenset_Lfclkstarted_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_LFCLKSTARTED_Field_1 use
+ (Intenset_Lfclkstarted_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to enable interrupt for DONE event
+ type INTENSET_DONE_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_DONE_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable interrupt for DONE event
+ type INTENSET_DONE_Field_1 is
+ (-- Reset value for the field
+ Intenset_Done_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_DONE_Field_1 use
+ (Intenset_Done_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to enable interrupt for CTTO event
+ type INTENSET_CTTO_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_CTTO_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable interrupt for CTTO event
+ type INTENSET_CTTO_Field_1 is
+ (-- Reset value for the field
+ Intenset_Ctto_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_CTTO_Field_1 use
+ (Intenset_Ctto_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to enable interrupt for CTSTARTED event
+ type INTENSET_CTSTARTED_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_CTSTARTED_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable interrupt for CTSTARTED event
+ type INTENSET_CTSTARTED_Field_1 is
+ (-- Reset value for the field
+ Intenset_Ctstarted_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_CTSTARTED_Field_1 use
+ (Intenset_Ctstarted_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to enable interrupt for CTSTOPPED event
+ type INTENSET_CTSTOPPED_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_CTSTOPPED_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable interrupt for CTSTOPPED event
+ type INTENSET_CTSTOPPED_Field_1 is
+ (-- Reset value for the field
+ Intenset_Ctstopped_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_CTSTOPPED_Field_1 use
+ (Intenset_Ctstopped_Field_Reset => 0,
+ Set => 1);
+
+ -- Enable interrupt
+ type INTENSET_Register is record
+ -- Write '1' to enable interrupt for HFCLKSTARTED event
+ HFCLKSTARTED : INTENSET_HFCLKSTARTED_Field_1 :=
+ Intenset_Hfclkstarted_Field_Reset;
+ -- Write '1' to enable interrupt for LFCLKSTARTED event
+ LFCLKSTARTED : INTENSET_LFCLKSTARTED_Field_1 :=
+ Intenset_Lfclkstarted_Field_Reset;
+ -- unspecified
+ Reserved_2_2 : Interfaces.NRF52.Bit := 16#0#;
+ -- Write '1' to enable interrupt for DONE event
+ DONE : INTENSET_DONE_Field_1 := Intenset_Done_Field_Reset;
+ -- Write '1' to enable interrupt for CTTO event
+ CTTO : INTENSET_CTTO_Field_1 := Intenset_Ctto_Field_Reset;
+ -- unspecified
+ Reserved_5_9 : Interfaces.NRF52.UInt5 := 16#0#;
+ -- Write '1' to enable interrupt for CTSTARTED event
+ CTSTARTED : INTENSET_CTSTARTED_Field_1 :=
+ Intenset_Ctstarted_Field_Reset;
+ -- Write '1' to enable interrupt for CTSTOPPED event
+ CTSTOPPED : INTENSET_CTSTOPPED_Field_1 :=
+ Intenset_Ctstopped_Field_Reset;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENSET_Register use record
+ HFCLKSTARTED at 0 range 0 .. 0;
+ LFCLKSTARTED at 0 range 1 .. 1;
+ Reserved_2_2 at 0 range 2 .. 2;
+ DONE at 0 range 3 .. 3;
+ CTTO at 0 range 4 .. 4;
+ Reserved_5_9 at 0 range 5 .. 9;
+ CTSTARTED at 0 range 10 .. 10;
+ CTSTOPPED at 0 range 11 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ -- Write '1' to disable interrupt for HFCLKSTARTED event
+ type INTENCLR_HFCLKSTARTED_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_HFCLKSTARTED_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable interrupt for HFCLKSTARTED event
+ type INTENCLR_HFCLKSTARTED_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Hfclkstarted_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_HFCLKSTARTED_Field_1 use
+ (Intenclr_Hfclkstarted_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to disable interrupt for LFCLKSTARTED event
+ type INTENCLR_LFCLKSTARTED_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_LFCLKSTARTED_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable interrupt for LFCLKSTARTED event
+ type INTENCLR_LFCLKSTARTED_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Lfclkstarted_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_LFCLKSTARTED_Field_1 use
+ (Intenclr_Lfclkstarted_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to disable interrupt for DONE event
+ type INTENCLR_DONE_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_DONE_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable interrupt for DONE event
+ type INTENCLR_DONE_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Done_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_DONE_Field_1 use
+ (Intenclr_Done_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to disable interrupt for CTTO event
+ type INTENCLR_CTTO_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_CTTO_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable interrupt for CTTO event
+ type INTENCLR_CTTO_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Ctto_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_CTTO_Field_1 use
+ (Intenclr_Ctto_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to disable interrupt for CTSTARTED event
+ type INTENCLR_CTSTARTED_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_CTSTARTED_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable interrupt for CTSTARTED event
+ type INTENCLR_CTSTARTED_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Ctstarted_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_CTSTARTED_Field_1 use
+ (Intenclr_Ctstarted_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to disable interrupt for CTSTOPPED event
+ type INTENCLR_CTSTOPPED_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_CTSTOPPED_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable interrupt for CTSTOPPED event
+ type INTENCLR_CTSTOPPED_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Ctstopped_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_CTSTOPPED_Field_1 use
+ (Intenclr_Ctstopped_Field_Reset => 0,
+ Clear => 1);
+
+ -- Disable interrupt
+ type INTENCLR_Register is record
+ -- Write '1' to disable interrupt for HFCLKSTARTED event
+ HFCLKSTARTED : INTENCLR_HFCLKSTARTED_Field_1 :=
+ Intenclr_Hfclkstarted_Field_Reset;
+ -- Write '1' to disable interrupt for LFCLKSTARTED event
+ LFCLKSTARTED : INTENCLR_LFCLKSTARTED_Field_1 :=
+ Intenclr_Lfclkstarted_Field_Reset;
+ -- unspecified
+ Reserved_2_2 : Interfaces.NRF52.Bit := 16#0#;
+ -- Write '1' to disable interrupt for DONE event
+ DONE : INTENCLR_DONE_Field_1 := Intenclr_Done_Field_Reset;
+ -- Write '1' to disable interrupt for CTTO event
+ CTTO : INTENCLR_CTTO_Field_1 := Intenclr_Ctto_Field_Reset;
+ -- unspecified
+ Reserved_5_9 : Interfaces.NRF52.UInt5 := 16#0#;
+ -- Write '1' to disable interrupt for CTSTARTED event
+ CTSTARTED : INTENCLR_CTSTARTED_Field_1 :=
+ Intenclr_Ctstarted_Field_Reset;
+ -- Write '1' to disable interrupt for CTSTOPPED event
+ CTSTOPPED : INTENCLR_CTSTOPPED_Field_1 :=
+ Intenclr_Ctstopped_Field_Reset;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENCLR_Register use record
+ HFCLKSTARTED at 0 range 0 .. 0;
+ LFCLKSTARTED at 0 range 1 .. 1;
+ Reserved_2_2 at 0 range 2 .. 2;
+ DONE at 0 range 3 .. 3;
+ CTTO at 0 range 4 .. 4;
+ Reserved_5_9 at 0 range 5 .. 9;
+ CTSTARTED at 0 range 10 .. 10;
+ CTSTOPPED at 0 range 11 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ -- HFCLKSTART task triggered or not
+ type HFCLKRUN_STATUS_Field is
+ (-- Task not triggered
+ Nottriggered,
+ -- Task triggered
+ Triggered)
+ with Size => 1;
+ for HFCLKRUN_STATUS_Field use
+ (Nottriggered => 0,
+ Triggered => 1);
+
+ -- Status indicating that HFCLKSTART task has been triggered
+ type HFCLKRUN_Register is record
+ -- Read-only. HFCLKSTART task triggered or not
+ STATUS : HFCLKRUN_STATUS_Field;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for HFCLKRUN_Register use record
+ STATUS at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Source of HFCLK
+ type HFCLKSTAT_SRC_Field is
+ (-- 64 MHz internal oscillator (HFINT)
+ Rc,
+ -- 64 MHz crystal oscillator (HFXO)
+ Xtal)
+ with Size => 1;
+ for HFCLKSTAT_SRC_Field use
+ (Rc => 0,
+ Xtal => 1);
+
+ -- HFCLK state
+ type HFCLKSTAT_STATE_Field is
+ (-- HFCLK not running
+ Notrunning,
+ -- HFCLK running
+ Running)
+ with Size => 1;
+ for HFCLKSTAT_STATE_Field use
+ (Notrunning => 0,
+ Running => 1);
+
+ -- HFCLK status
+ type HFCLKSTAT_Register is record
+ -- Read-only. Source of HFCLK
+ SRC : HFCLKSTAT_SRC_Field;
+ -- unspecified
+ Reserved_1_15 : Interfaces.NRF52.UInt15;
+ -- Read-only. HFCLK state
+ STATE : HFCLKSTAT_STATE_Field;
+ -- unspecified
+ Reserved_17_31 : Interfaces.NRF52.UInt15;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for HFCLKSTAT_Register use record
+ SRC at 0 range 0 .. 0;
+ Reserved_1_15 at 0 range 1 .. 15;
+ STATE at 0 range 16 .. 16;
+ Reserved_17_31 at 0 range 17 .. 31;
+ end record;
+
+ -- LFCLKSTART task triggered or not
+ type LFCLKRUN_STATUS_Field is
+ (-- Task not triggered
+ Nottriggered,
+ -- Task triggered
+ Triggered)
+ with Size => 1;
+ for LFCLKRUN_STATUS_Field use
+ (Nottriggered => 0,
+ Triggered => 1);
+
+ -- Status indicating that LFCLKSTART task has been triggered
+ type LFCLKRUN_Register is record
+ -- Read-only. LFCLKSTART task triggered or not
+ STATUS : LFCLKRUN_STATUS_Field;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for LFCLKRUN_Register use record
+ STATUS at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Source of LFCLK
+ type LFCLKSTAT_SRC_Field is
+ (-- 32.768 kHz RC oscillator (LFRC)
+ Rc,
+ -- 32.768 kHz crystal oscillator (LFXO)
+ Xtal,
+ -- 32.768 kHz synthesized from HFCLK (LFSYNT)
+ Synth)
+ with Size => 2;
+ for LFCLKSTAT_SRC_Field use
+ (Rc => 0,
+ Xtal => 1,
+ Synth => 2);
+
+ -- LFCLK state
+ type LFCLKSTAT_STATE_Field is
+ (-- LFCLK not running
+ Notrunning,
+ -- LFCLK running
+ Running)
+ with Size => 1;
+ for LFCLKSTAT_STATE_Field use
+ (Notrunning => 0,
+ Running => 1);
+
+ -- LFCLK status
+ type LFCLKSTAT_Register is record
+ -- Read-only. Source of LFCLK
+ SRC : LFCLKSTAT_SRC_Field;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14;
+ -- Read-only. LFCLK state
+ STATE : LFCLKSTAT_STATE_Field;
+ -- unspecified
+ Reserved_17_31 : Interfaces.NRF52.UInt15;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for LFCLKSTAT_Register use record
+ SRC at 0 range 0 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ STATE at 0 range 16 .. 16;
+ Reserved_17_31 at 0 range 17 .. 31;
+ end record;
+
+ -- Clock source
+ type LFCLKSRCCOPY_SRC_Field is
+ (-- 32.768 kHz RC oscillator (LFRC)
+ Rc,
+ -- 32.768 kHz crystal oscillator (LFXO)
+ Xtal,
+ -- 32.768 kHz synthesized from HFCLK (LFSYNT)
+ Synth)
+ with Size => 2;
+ for LFCLKSRCCOPY_SRC_Field use
+ (Rc => 0,
+ Xtal => 1,
+ Synth => 2);
+
+ -- Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
+ type LFCLKSRCCOPY_Register is record
+ -- Read-only. Clock source
+ SRC : LFCLKSRCCOPY_SRC_Field;
+ -- unspecified
+ Reserved_2_31 : Interfaces.NRF52.UInt30;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for LFCLKSRCCOPY_Register use record
+ SRC at 0 range 0 .. 1;
+ Reserved_2_31 at 0 range 2 .. 31;
+ end record;
+
+ -- Clock source
+ type LFCLKSRC_SRC_Field is
+ (-- 32.768 kHz RC oscillator (LFRC)
+ Rc,
+ -- 32.768 kHz crystal oscillator (LFXO)
+ Xtal,
+ -- 32.768 kHz synthesized from HFCLK (LFSYNT)
+ Synth)
+ with Size => 2;
+ for LFCLKSRC_SRC_Field use
+ (Rc => 0,
+ Xtal => 1,
+ Synth => 2);
+
+ -- Enable or disable bypass of LFCLK crystal oscillator with external clock
+ -- source
+ type LFCLKSRC_BYPASS_Field is
+ (-- Disable (use with Xtal or low-swing external source)
+ Disabled,
+ -- Enable (use with rail-to-rail external source)
+ Enabled)
+ with Size => 1;
+ for LFCLKSRC_BYPASS_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Enable or disable external source for LFCLK
+ type LFCLKSRC_EXTERNAL_Field is
+ (-- Disable external source (use with Xtal)
+ Disabled,
+ -- Enable use of external source instead of Xtal (SRC needs to be set to Xtal)
+ Enabled)
+ with Size => 1;
+ for LFCLKSRC_EXTERNAL_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Clock source for the LFCLK
+ type LFCLKSRC_Register is record
+ -- Clock source
+ SRC : LFCLKSRC_SRC_Field := Interfaces.NRF52.CLOCK.Rc;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14 := 16#0#;
+ -- Enable or disable bypass of LFCLK crystal oscillator with external
+ -- clock source
+ BYPASS : LFCLKSRC_BYPASS_Field :=
+ Interfaces.NRF52.CLOCK.Disabled;
+ -- Enable or disable external source for LFCLK
+ EXTERNAL : LFCLKSRC_EXTERNAL_Field :=
+ Interfaces.NRF52.CLOCK.Disabled;
+ -- unspecified
+ Reserved_18_31 : Interfaces.NRF52.UInt14 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for LFCLKSRC_Register use record
+ SRC at 0 range 0 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ BYPASS at 0 range 16 .. 16;
+ EXTERNAL at 0 range 17 .. 17;
+ Reserved_18_31 at 0 range 18 .. 31;
+ end record;
+
+ -- HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us.
+ type HFXODEBOUNCE_HFXODEBOUNCE_Field is
+ (-- 256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals.
+ Db256US,
+ -- 1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals.
+ Db1024US)
+ with Size => 8;
+ for HFXODEBOUNCE_HFXODEBOUNCE_Field use
+ (Db256US => 16,
+ Db1024US => 64);
+
+ -- HFXO debounce time. The HFXO is started by triggering the
+ -- TASKS_HFCLKSTART task.
+ type HFXODEBOUNCE_Register is record
+ -- HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us.
+ HFXODEBOUNCE : HFXODEBOUNCE_HFXODEBOUNCE_Field :=
+ Interfaces.NRF52.CLOCK.Db256US;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for HFXODEBOUNCE_Register use record
+ HFXODEBOUNCE at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ subtype CTIV_CTIV_Field is Interfaces.NRF52.UInt7;
+
+ -- Calibration timer interval
+ type CTIV_Register is record
+ -- Calibration timer interval in multiple of 0.25 seconds. Range: 0.25
+ -- seconds to 31.75 seconds.
+ CTIV : CTIV_CTIV_Field := 16#0#;
+ -- unspecified
+ Reserved_7_31 : Interfaces.NRF52.UInt25 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for CTIV_Register use record
+ CTIV at 0 range 0 .. 6;
+ Reserved_7_31 at 0 range 7 .. 31;
+ end record;
+
+ -- Speed of trace port clock. Note that the TRACECLK pin will output this
+ -- clock divided by two.
+ type TRACECONFIG_TRACEPORTSPEED_Field is
+ (-- 32 MHz trace port clock (TRACECLK = 16 MHz)
+ Val_32Mhz,
+ -- 16 MHz trace port clock (TRACECLK = 8 MHz)
+ Val_16Mhz,
+ -- 8 MHz trace port clock (TRACECLK = 4 MHz)
+ Val_8Mhz,
+ -- 4 MHz trace port clock (TRACECLK = 2 MHz)
+ Val_4Mhz)
+ with Size => 2;
+ for TRACECONFIG_TRACEPORTSPEED_Field use
+ (Val_32Mhz => 0,
+ Val_16Mhz => 1,
+ Val_8Mhz => 2,
+ Val_4Mhz => 3);
+
+ -- Pin multiplexing of trace signals. See pin assignment chapter for more
+ -- details.
+ type TRACECONFIG_TRACEMUX_Field is
+ (-- No trace signals routed to pins. All pins can be used as regular GPIOs.
+ Gpio,
+ -- SWO trace signal routed to pin. Remaining pins can be used as regular
+-- GPIOs.
+ Serial,
+ -- All trace signals (TRACECLK and TRACEDATA[n]) routed to pins.
+ Parallel)
+ with Size => 2;
+ for TRACECONFIG_TRACEMUX_Field use
+ (Gpio => 0,
+ Serial => 1,
+ Parallel => 2);
+
+ -- Clocking options for the trace port debug interface
+ type TRACECONFIG_Register is record
+ -- Speed of trace port clock. Note that the TRACECLK pin will output
+ -- this clock divided by two.
+ TRACEPORTSPEED : TRACECONFIG_TRACEPORTSPEED_Field :=
+ Interfaces.NRF52.CLOCK.Val_32Mhz;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14 := 16#0#;
+ -- Pin multiplexing of trace signals. See pin assignment chapter for
+ -- more details.
+ TRACEMUX : TRACECONFIG_TRACEMUX_Field :=
+ Interfaces.NRF52.CLOCK.Gpio;
+ -- unspecified
+ Reserved_18_31 : Interfaces.NRF52.UInt14 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TRACECONFIG_Register use record
+ TRACEPORTSPEED at 0 range 0 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ TRACEMUX at 0 range 16 .. 17;
+ Reserved_18_31 at 0 range 18 .. 31;
+ end record;
+
+ -- Set LFRC mode
+ type LFRCMODE_MODE_Field is
+ (-- Normal mode
+ Normal,
+ -- Ultra-low power mode (ULP)
+ Ulp)
+ with Size => 1;
+ for LFRCMODE_MODE_Field use
+ (Normal => 0,
+ Ulp => 1);
+
+ -- Active LFRC mode. This field is read only.
+ type LFRCMODE_STATUS_Field is
+ (-- Normal mode
+ Normal,
+ -- Ultra-low power mode (ULP)
+ Ulp)
+ with Size => 1;
+ for LFRCMODE_STATUS_Field use
+ (Normal => 0,
+ Ulp => 1);
+
+ -- LFRC mode configuration
+ type LFRCMODE_Register is record
+ -- Set LFRC mode
+ MODE : LFRCMODE_MODE_Field := Interfaces.NRF52.CLOCK.Normal;
+ -- unspecified
+ Reserved_1_15 : Interfaces.NRF52.UInt15 := 16#0#;
+ -- Active LFRC mode. This field is read only.
+ STATUS : LFRCMODE_STATUS_Field := Interfaces.NRF52.CLOCK.Normal;
+ -- unspecified
+ Reserved_17_31 : Interfaces.NRF52.UInt15 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for LFRCMODE_Register use record
+ MODE at 0 range 0 .. 0;
+ Reserved_1_15 at 0 range 1 .. 15;
+ STATUS at 0 range 16 .. 16;
+ Reserved_17_31 at 0 range 17 .. 31;
+ end record;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ -- Clock control
+ type CLOCK_Peripheral is record
+ -- Start HFXO crystal oscillator
+ TASKS_HFCLKSTART : aliased TASKS_HFCLKSTART_Register;
+ -- Stop HFXO crystal oscillator
+ TASKS_HFCLKSTOP : aliased TASKS_HFCLKSTOP_Register;
+ -- Start LFCLK
+ TASKS_LFCLKSTART : aliased TASKS_LFCLKSTART_Register;
+ -- Stop LFCLK
+ TASKS_LFCLKSTOP : aliased TASKS_LFCLKSTOP_Register;
+ -- Start calibration of LFRC
+ TASKS_CAL : aliased TASKS_CAL_Register;
+ -- Start calibration timer
+ TASKS_CTSTART : aliased TASKS_CTSTART_Register;
+ -- Stop calibration timer
+ TASKS_CTSTOP : aliased TASKS_CTSTOP_Register;
+ -- HFXO crystal oscillator started
+ EVENTS_HFCLKSTARTED : aliased EVENTS_HFCLKSTARTED_Register;
+ -- LFCLK started
+ EVENTS_LFCLKSTARTED : aliased EVENTS_LFCLKSTARTED_Register;
+ -- Calibration of LFRC completed
+ EVENTS_DONE : aliased EVENTS_DONE_Register;
+ -- Calibration timer timeout
+ EVENTS_CTTO : aliased EVENTS_CTTO_Register;
+ -- Calibration timer has been started and is ready to process new tasks
+ EVENTS_CTSTARTED : aliased EVENTS_CTSTARTED_Register;
+ -- Calibration timer has been stopped and is ready to process new tasks
+ EVENTS_CTSTOPPED : aliased EVENTS_CTSTOPPED_Register;
+ -- Enable interrupt
+ INTENSET : aliased INTENSET_Register;
+ -- Disable interrupt
+ INTENCLR : aliased INTENCLR_Register;
+ -- Status indicating that HFCLKSTART task has been triggered
+ HFCLKRUN : aliased HFCLKRUN_Register;
+ -- HFCLK status
+ HFCLKSTAT : aliased HFCLKSTAT_Register;
+ -- Status indicating that LFCLKSTART task has been triggered
+ LFCLKRUN : aliased LFCLKRUN_Register;
+ -- LFCLK status
+ LFCLKSTAT : aliased LFCLKSTAT_Register;
+ -- Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
+ LFCLKSRCCOPY : aliased LFCLKSRCCOPY_Register;
+ -- Clock source for the LFCLK
+ LFCLKSRC : aliased LFCLKSRC_Register;
+ -- HFXO debounce time. The HFXO is started by triggering the
+ -- TASKS_HFCLKSTART task.
+ HFXODEBOUNCE : aliased HFXODEBOUNCE_Register;
+ -- Calibration timer interval
+ CTIV : aliased CTIV_Register;
+ -- Clocking options for the trace port debug interface
+ TRACECONFIG : aliased TRACECONFIG_Register;
+ -- LFRC mode configuration
+ LFRCMODE : aliased LFRCMODE_Register;
+ end record
+ with Volatile;
+
+ for CLOCK_Peripheral use record
+ TASKS_HFCLKSTART at 16#0# range 0 .. 31;
+ TASKS_HFCLKSTOP at 16#4# range 0 .. 31;
+ TASKS_LFCLKSTART at 16#8# range 0 .. 31;
+ TASKS_LFCLKSTOP at 16#C# range 0 .. 31;
+ TASKS_CAL at 16#10# range 0 .. 31;
+ TASKS_CTSTART at 16#14# range 0 .. 31;
+ TASKS_CTSTOP at 16#18# range 0 .. 31;
+ EVENTS_HFCLKSTARTED at 16#100# range 0 .. 31;
+ EVENTS_LFCLKSTARTED at 16#104# range 0 .. 31;
+ EVENTS_DONE at 16#10C# range 0 .. 31;
+ EVENTS_CTTO at 16#110# range 0 .. 31;
+ EVENTS_CTSTARTED at 16#128# range 0 .. 31;
+ EVENTS_CTSTOPPED at 16#12C# range 0 .. 31;
+ INTENSET at 16#304# range 0 .. 31;
+ INTENCLR at 16#308# range 0 .. 31;
+ HFCLKRUN at 16#408# range 0 .. 31;
+ HFCLKSTAT at 16#40C# range 0 .. 31;
+ LFCLKRUN at 16#414# range 0 .. 31;
+ LFCLKSTAT at 16#418# range 0 .. 31;
+ LFCLKSRCCOPY at 16#41C# range 0 .. 31;
+ LFCLKSRC at 16#518# range 0 .. 31;
+ HFXODEBOUNCE at 16#528# range 0 .. 31;
+ CTIV at 16#538# range 0 .. 31;
+ TRACECONFIG at 16#55C# range 0 .. 31;
+ LFRCMODE at 16#5B4# range 0 .. 31;
+ end record;
+
+ -- Clock control
+ CLOCK_Periph : aliased CLOCK_Peripheral
+ with Import, Address => CLOCK_Base;
+
+end Interfaces.NRF52.CLOCK;
diff --git a/arm/nordic/nrf52/nrf52840/svd/i-nrf52-ficr.ads b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-ficr.ads
new file mode 100644
index 00000000..e79a867b
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-ficr.ads
@@ -0,0 +1,511 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update
+-- for such product, must reproduce the above copyright notice, this list
+-- of conditions and the following disclaimer in the documentation and/or
+-- other materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from
+-- this software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52840.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.FICR is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ -- Description collection[n]: Device identifier
+
+ -- Description collection[n]: Device identifier
+ type DEVICEID_Registers is array (0 .. 1) of Interfaces.NRF52.UInt32;
+
+ -- Description collection[n]: Encryption root, word n
+
+ -- Description collection[n]: Encryption root, word n
+ type ER_Registers is array (0 .. 3) of Interfaces.NRF52.UInt32;
+
+ -- Description collection[n]: Identity Root, word n
+
+ -- Description collection[n]: Identity Root, word n
+ type IR_Registers is array (0 .. 3) of Interfaces.NRF52.UInt32;
+
+ -- Device address type
+ type DEVICEADDRTYPE_DEVICEADDRTYPE_Field is
+ (-- Public address
+ Public,
+ -- Random address
+ Random)
+ with Size => 1;
+ for DEVICEADDRTYPE_DEVICEADDRTYPE_Field use
+ (Public => 0,
+ Random => 1);
+
+ -- Device address type
+ type DEVICEADDRTYPE_Register is record
+ -- Read-only. Device address type
+ DEVICEADDRTYPE : DEVICEADDRTYPE_DEVICEADDRTYPE_Field;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for DEVICEADDRTYPE_Register use record
+ DEVICEADDRTYPE at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Description collection[n]: Device address n
+
+ -- Description collection[n]: Device address n
+ type DEVICEADDR_Registers is array (0 .. 1) of Interfaces.NRF52.UInt32;
+
+ -----------------------------------
+ -- FICR_INFO cluster's Registers --
+ -----------------------------------
+
+ -- Unspecified
+
+ -- Unspecified
+ type UNUSED8_INFO_Registers is array (0 .. 2) of Interfaces.NRF52.UInt32;
+
+ -- Device info
+ type FICR_INFO_Cluster is record
+ -- Part code
+ PART : aliased Interfaces.NRF52.UInt32;
+ -- Build code (hardware version and production configuration)
+ VARIANT : aliased Interfaces.NRF52.UInt32;
+ -- Package option
+ PACKAGE_k : aliased Interfaces.NRF52.UInt32;
+ -- RAM variant
+ RAM : aliased Interfaces.NRF52.UInt32;
+ -- Flash variant
+ FLASH : aliased Interfaces.NRF52.UInt32;
+ -- Unspecified
+ UNUSED8 : aliased UNUSED8_INFO_Registers;
+ end record
+ with Size => 256;
+
+ for FICR_INFO_Cluster use record
+ PART at 16#0# range 0 .. 31;
+ VARIANT at 16#4# range 0 .. 31;
+ PACKAGE_k at 16#8# range 0 .. 31;
+ RAM at 16#C# range 0 .. 31;
+ FLASH at 16#10# range 0 .. 31;
+ UNUSED8 at 16#14# range 0 .. 95;
+ end record;
+
+ -- Description collection[n]: Production test signature n
+
+ -- Description collection[n]: Production test signature n
+ type PRODTEST_Registers is array (0 .. 2) of Interfaces.NRF52.UInt32;
+
+ -----------------------------------
+ -- FICR_TEMP cluster's Registers --
+ -----------------------------------
+
+ subtype A_A_Field is Interfaces.NRF52.UInt12;
+
+ -- Slope definition A0
+ type A_Register is record
+ -- Read-only. A (slope definition) register.
+ A : A_A_Field;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for A_Register use record
+ A at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype B_B_Field is Interfaces.NRF52.UInt14;
+
+ -- Y-intercept B0
+ type B_Register is record
+ -- Read-only. B (y-intercept)
+ B : B_B_Field;
+ -- unspecified
+ Reserved_14_31 : Interfaces.NRF52.UInt18;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for B_Register use record
+ B at 0 range 0 .. 13;
+ Reserved_14_31 at 0 range 14 .. 31;
+ end record;
+
+ subtype T_T_Field is Interfaces.NRF52.Byte;
+
+ -- Segment end T0
+ type T_Register is record
+ -- Read-only. T (segment end) register
+ T : T_T_Field;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for T_Register use record
+ T at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ -- Registers storing factory TEMP module linearization coefficients
+ type FICR_TEMP_Cluster is record
+ -- Slope definition A0
+ A0 : aliased A_Register;
+ -- Slope definition A1
+ A1 : aliased A_Register;
+ -- Slope definition A2
+ A2 : aliased A_Register;
+ -- Slope definition A3
+ A3 : aliased A_Register;
+ -- Slope definition A4
+ A4 : aliased A_Register;
+ -- Slope definition A5
+ A5 : aliased A_Register;
+ -- Y-intercept B0
+ B0 : aliased B_Register;
+ -- Y-intercept B1
+ B1 : aliased B_Register;
+ -- Y-intercept B2
+ B2 : aliased B_Register;
+ -- Y-intercept B3
+ B3 : aliased B_Register;
+ -- Y-intercept B4
+ B4 : aliased B_Register;
+ -- Y-intercept B5
+ B5 : aliased B_Register;
+ -- Segment end T0
+ T0 : aliased T_Register;
+ -- Segment end T1
+ T1 : aliased T_Register;
+ -- Segment end T2
+ T2 : aliased T_Register;
+ -- Segment end T3
+ T3 : aliased T_Register;
+ -- Segment end T4
+ T4 : aliased T_Register;
+ end record
+ with Size => 544;
+
+ for FICR_TEMP_Cluster use record
+ A0 at 16#0# range 0 .. 31;
+ A1 at 16#4# range 0 .. 31;
+ A2 at 16#8# range 0 .. 31;
+ A3 at 16#C# range 0 .. 31;
+ A4 at 16#10# range 0 .. 31;
+ A5 at 16#14# range 0 .. 31;
+ B0 at 16#18# range 0 .. 31;
+ B1 at 16#1C# range 0 .. 31;
+ B2 at 16#20# range 0 .. 31;
+ B3 at 16#24# range 0 .. 31;
+ B4 at 16#28# range 0 .. 31;
+ B5 at 16#2C# range 0 .. 31;
+ T0 at 16#30# range 0 .. 31;
+ T1 at 16#34# range 0 .. 31;
+ T2 at 16#38# range 0 .. 31;
+ T3 at 16#3C# range 0 .. 31;
+ T4 at 16#40# range 0 .. 31;
+ end record;
+
+ ----------------------------------
+ -- FICR_NFC cluster's Registers --
+ ----------------------------------
+
+ subtype TAGHEADER0_NFC_MFGID_Field is Interfaces.NRF52.Byte;
+ -- TAGHEADER0_NFC_UD array element
+ subtype TAGHEADER0_NFC_UD_Element is Interfaces.NRF52.Byte;
+
+ -- TAGHEADER0_NFC_UD array
+ type TAGHEADER0_NFC_UD_Field_Array is array (1 .. 3)
+ of TAGHEADER0_NFC_UD_Element
+ with Component_Size => 8, Size => 24;
+
+ -- Type definition for TAGHEADER0_NFC_UD
+ type TAGHEADER0_NFC_UD_Field
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- UD as a value
+ Val : Interfaces.NRF52.UInt24;
+ when True =>
+ -- UD as an array
+ Arr : TAGHEADER0_NFC_UD_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 24;
+
+ for TAGHEADER0_NFC_UD_Field use record
+ Val at 0 range 0 .. 23;
+ Arr at 0 range 0 .. 23;
+ end record;
+
+ -- Default header for NFC tag. Software can read these values to populate
+ -- NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ type TAGHEADER0_NFC_Register is record
+ -- Read-only. Default Manufacturer ID: Nordic Semiconductor ASA has ICM
+ -- 0x5F
+ MFGID : TAGHEADER0_NFC_MFGID_Field;
+ -- Read-only. Unique identifier byte 1
+ UD : TAGHEADER0_NFC_UD_Field;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TAGHEADER0_NFC_Register use record
+ MFGID at 0 range 0 .. 7;
+ UD at 0 range 8 .. 31;
+ end record;
+
+ -- TAGHEADER1_NFC_UD array element
+ subtype TAGHEADER1_NFC_UD_Element is Interfaces.NRF52.Byte;
+
+ -- TAGHEADER1_NFC_UD array
+ type TAGHEADER1_NFC_UD_Field_Array is array (4 .. 7)
+ of TAGHEADER1_NFC_UD_Element
+ with Component_Size => 8, Size => 32;
+
+ -- Default header for NFC tag. Software can read these values to populate
+ -- NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ type TAGHEADER1_NFC_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- UD as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- UD as an array
+ Arr : TAGHEADER1_NFC_UD_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for TAGHEADER1_NFC_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- TAGHEADER2_NFC_UD array element
+ subtype TAGHEADER2_NFC_UD_Element is Interfaces.NRF52.Byte;
+
+ -- TAGHEADER2_NFC_UD array
+ type TAGHEADER2_NFC_UD_Field_Array is array (8 .. 11)
+ of TAGHEADER2_NFC_UD_Element
+ with Component_Size => 8, Size => 32;
+
+ -- Default header for NFC tag. Software can read these values to populate
+ -- NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ type TAGHEADER2_NFC_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- UD as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- UD as an array
+ Arr : TAGHEADER2_NFC_UD_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for TAGHEADER2_NFC_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- TAGHEADER3_NFC_UD array element
+ subtype TAGHEADER3_NFC_UD_Element is Interfaces.NRF52.Byte;
+
+ -- TAGHEADER3_NFC_UD array
+ type TAGHEADER3_NFC_UD_Field_Array is array (12 .. 15)
+ of TAGHEADER3_NFC_UD_Element
+ with Component_Size => 8, Size => 32;
+
+ -- Default header for NFC tag. Software can read these values to populate
+ -- NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ type TAGHEADER3_NFC_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- UD as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- UD as an array
+ Arr : TAGHEADER3_NFC_UD_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for TAGHEADER3_NFC_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Unspecified
+ type FICR_NFC_Cluster is record
+ -- Default header for NFC tag. Software can read these values to
+ -- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ TAGHEADER0 : aliased TAGHEADER0_NFC_Register;
+ -- Default header for NFC tag. Software can read these values to
+ -- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ TAGHEADER1 : aliased TAGHEADER1_NFC_Register;
+ -- Default header for NFC tag. Software can read these values to
+ -- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ TAGHEADER2 : aliased TAGHEADER2_NFC_Register;
+ -- Default header for NFC tag. Software can read these values to
+ -- populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.
+ TAGHEADER3 : aliased TAGHEADER3_NFC_Register;
+ end record
+ with Size => 128;
+
+ for FICR_NFC_Cluster use record
+ TAGHEADER0 at 16#0# range 0 .. 31;
+ TAGHEADER1 at 16#4# range 0 .. 31;
+ TAGHEADER2 at 16#8# range 0 .. 31;
+ TAGHEADER3 at 16#C# range 0 .. 31;
+ end record;
+
+ --------------------------------------
+ -- FICR_TRNG90B cluster's Registers --
+ --------------------------------------
+
+ -- NIST800-90B RNG calibration data
+ type FICR_TRNG90B_Cluster is record
+ -- Amount of bytes for the required entropy bits
+ BYTES : aliased Interfaces.NRF52.UInt32;
+ -- Repetition counter cutoff
+ RCCUTOFF : aliased Interfaces.NRF52.UInt32;
+ -- Adaptive proportion cutoff
+ APCUTOFF : aliased Interfaces.NRF52.UInt32;
+ -- Amount of bytes for the startup tests
+ STARTUP : aliased Interfaces.NRF52.UInt32;
+ -- Sample count for ring oscillator 1
+ ROSC1 : aliased Interfaces.NRF52.UInt32;
+ -- Sample count for ring oscillator 2
+ ROSC2 : aliased Interfaces.NRF52.UInt32;
+ -- Sample count for ring oscillator 3
+ ROSC3 : aliased Interfaces.NRF52.UInt32;
+ -- Sample count for ring oscillator 4
+ ROSC4 : aliased Interfaces.NRF52.UInt32;
+ end record
+ with Size => 256;
+
+ for FICR_TRNG90B_Cluster use record
+ BYTES at 16#0# range 0 .. 31;
+ RCCUTOFF at 16#4# range 0 .. 31;
+ APCUTOFF at 16#8# range 0 .. 31;
+ STARTUP at 16#C# range 0 .. 31;
+ ROSC1 at 16#10# range 0 .. 31;
+ ROSC2 at 16#14# range 0 .. 31;
+ ROSC3 at 16#18# range 0 .. 31;
+ ROSC4 at 16#1C# range 0 .. 31;
+ end record;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ -- Factory information configuration registers
+ type FICR_Peripheral is record
+ -- Code memory page size
+ CODEPAGESIZE : aliased Interfaces.NRF52.UInt32;
+ -- Code memory size
+ CODESIZE : aliased Interfaces.NRF52.UInt32;
+ -- Description collection[n]: Device identifier
+ DEVICEID : aliased DEVICEID_Registers;
+ -- Description collection[n]: Encryption root, word n
+ ER : aliased ER_Registers;
+ -- Description collection[n]: Identity Root, word n
+ IR : aliased IR_Registers;
+ -- Device address type
+ DEVICEADDRTYPE : aliased DEVICEADDRTYPE_Register;
+ -- Description collection[n]: Device address n
+ DEVICEADDR : aliased DEVICEADDR_Registers;
+ -- Device info
+ INFO : aliased FICR_INFO_Cluster;
+ -- Description collection[n]: Production test signature n
+ PRODTEST : aliased PRODTEST_Registers;
+ -- Registers storing factory TEMP module linearization coefficients
+ TEMP : aliased FICR_TEMP_Cluster;
+ -- Unspecified
+ NFC : aliased FICR_NFC_Cluster;
+ -- NIST800-90B RNG calibration data
+ TRNG90B : aliased FICR_TRNG90B_Cluster;
+ end record
+ with Volatile;
+
+ for FICR_Peripheral use record
+ CODEPAGESIZE at 16#10# range 0 .. 31;
+ CODESIZE at 16#14# range 0 .. 31;
+ DEVICEID at 16#60# range 0 .. 63;
+ ER at 16#80# range 0 .. 127;
+ IR at 16#90# range 0 .. 127;
+ DEVICEADDRTYPE at 16#A0# range 0 .. 31;
+ DEVICEADDR at 16#A4# range 0 .. 63;
+ INFO at 16#100# range 0 .. 255;
+ PRODTEST at 16#350# range 0 .. 95;
+ TEMP at 16#404# range 0 .. 543;
+ NFC at 16#450# range 0 .. 127;
+ TRNG90B at 16#C00# range 0 .. 255;
+ end record;
+
+ -- Factory information configuration registers
+ FICR_Periph : aliased FICR_Peripheral
+ with Import, Address => FICR_Base;
+
+end Interfaces.NRF52.FICR;
diff --git a/arm/nordic/nrf52/nrf52840/svd/i-nrf52-gpio.ads b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-gpio.ads
new file mode 100644
index 00000000..e01c3bf1
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-gpio.ads
@@ -0,0 +1,587 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update
+-- for such product, must reproduce the above copyright notice, this list
+-- of conditions and the following disclaimer in the documentation and/or
+-- other materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from
+-- this software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52840.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.GPIO is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ -- Pin 0
+ type OUT_PIN0_Field is
+ (-- Pin driver is low
+ Low,
+ -- Pin driver is high
+ High)
+ with Size => 1;
+ for OUT_PIN0_Field use
+ (Low => 0,
+ High => 1);
+
+ -- OUT_PIN array
+ type OUT_PIN_Field_Array is array (0 .. 31) of OUT_PIN0_Field
+ with Component_Size => 1, Size => 32;
+
+ -- Write GPIO port
+ type OUT_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : OUT_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for OUT_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Pin 0
+ type OUTSET_PIN0_Field is
+ (-- Read: pin driver is low
+ Low,
+ -- Read: pin driver is high
+ High)
+ with Size => 1;
+ for OUTSET_PIN0_Field use
+ (Low => 0,
+ High => 1);
+
+ -- Pin 0
+ type OUTSET_PIN0_Field_1 is
+ (-- Reset value for the field
+ Outset_Pin0_Field_Reset,
+ -- Write: writing a '1' sets the pin high; writing a '0' has no effect
+ Set)
+ with Size => 1;
+ for OUTSET_PIN0_Field_1 use
+ (Outset_Pin0_Field_Reset => 0,
+ Set => 1);
+
+ -- OUTSET_PIN array
+ type OUTSET_PIN_Field_Array is array (0 .. 31) of OUTSET_PIN0_Field_1
+ with Component_Size => 1, Size => 32;
+
+ -- Set individual bits in GPIO port
+ type OUTSET_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : OUTSET_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for OUTSET_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Pin 0
+ type OUTCLR_PIN0_Field is
+ (-- Read: pin driver is low
+ Low,
+ -- Read: pin driver is high
+ High)
+ with Size => 1;
+ for OUTCLR_PIN0_Field use
+ (Low => 0,
+ High => 1);
+
+ -- Pin 0
+ type OUTCLR_PIN0_Field_1 is
+ (-- Reset value for the field
+ Outclr_Pin0_Field_Reset,
+ -- Write: writing a '1' sets the pin low; writing a '0' has no effect
+ Clear)
+ with Size => 1;
+ for OUTCLR_PIN0_Field_1 use
+ (Outclr_Pin0_Field_Reset => 0,
+ Clear => 1);
+
+ -- OUTCLR_PIN array
+ type OUTCLR_PIN_Field_Array is array (0 .. 31) of OUTCLR_PIN0_Field_1
+ with Component_Size => 1, Size => 32;
+
+ -- Clear individual bits in GPIO port
+ type OUTCLR_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : OUTCLR_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for OUTCLR_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Pin 0
+ type IN_PIN0_Field is
+ (-- Pin input is low
+ Low,
+ -- Pin input is high
+ High)
+ with Size => 1;
+ for IN_PIN0_Field use
+ (Low => 0,
+ High => 1);
+
+ -- IN_PIN array
+ type IN_PIN_Field_Array is array (0 .. 31) of IN_PIN0_Field
+ with Component_Size => 1, Size => 32;
+
+ -- Read GPIO port
+ type IN_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : IN_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for IN_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Pin 0
+ type DIR_PIN0_Field is
+ (-- Pin set as input
+ Input,
+ -- Pin set as output
+ Output)
+ with Size => 1;
+ for DIR_PIN0_Field use
+ (Input => 0,
+ Output => 1);
+
+ -- DIR_PIN array
+ type DIR_PIN_Field_Array is array (0 .. 31) of DIR_PIN0_Field
+ with Component_Size => 1, Size => 32;
+
+ -- Direction of GPIO pins
+ type DIR_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : DIR_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for DIR_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Set as output pin 0
+ type DIRSET_PIN0_Field is
+ (-- Read: pin set as input
+ Input,
+ -- Read: pin set as output
+ Output)
+ with Size => 1;
+ for DIRSET_PIN0_Field use
+ (Input => 0,
+ Output => 1);
+
+ -- Set as output pin 0
+ type DIRSET_PIN0_Field_1 is
+ (-- Reset value for the field
+ Dirset_Pin0_Field_Reset,
+ -- Write: writing a '1' sets pin to output; writing a '0' has no effect
+ Set)
+ with Size => 1;
+ for DIRSET_PIN0_Field_1 use
+ (Dirset_Pin0_Field_Reset => 0,
+ Set => 1);
+
+ -- DIRSET_PIN array
+ type DIRSET_PIN_Field_Array is array (0 .. 31) of DIRSET_PIN0_Field_1
+ with Component_Size => 1, Size => 32;
+
+ -- DIR set register
+ type DIRSET_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : DIRSET_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for DIRSET_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Set as input pin 0
+ type DIRCLR_PIN0_Field is
+ (-- Read: pin set as input
+ Input,
+ -- Read: pin set as output
+ Output)
+ with Size => 1;
+ for DIRCLR_PIN0_Field use
+ (Input => 0,
+ Output => 1);
+
+ -- Set as input pin 0
+ type DIRCLR_PIN0_Field_1 is
+ (-- Reset value for the field
+ Dirclr_Pin0_Field_Reset,
+ -- Write: writing a '1' sets pin to input; writing a '0' has no effect
+ Clear)
+ with Size => 1;
+ for DIRCLR_PIN0_Field_1 use
+ (Dirclr_Pin0_Field_Reset => 0,
+ Clear => 1);
+
+ -- DIRCLR_PIN array
+ type DIRCLR_PIN_Field_Array is array (0 .. 31) of DIRCLR_PIN0_Field_1
+ with Component_Size => 1, Size => 32;
+
+ -- DIR clear register
+ type DIRCLR_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : DIRCLR_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for DIRCLR_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register.
+ -- Write '1' to clear.
+ type LATCH_PIN0_Field is
+ (-- Criteria has not been met
+ Notlatched,
+ -- Criteria has been met
+ Latched)
+ with Size => 1;
+ for LATCH_PIN0_Field use
+ (Notlatched => 0,
+ Latched => 1);
+
+ -- LATCH_PIN array
+ type LATCH_PIN_Field_Array is array (0 .. 31) of LATCH_PIN0_Field
+ with Component_Size => 1, Size => 32;
+
+ -- Latch register indicating what GPIO pins that have met the criteria set
+ -- in the PIN_CNF[n].SENSE registers
+ type LATCH_Register
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- PIN as a value
+ Val : Interfaces.NRF52.UInt32;
+ when True =>
+ -- PIN as an array
+ Arr : LATCH_PIN_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 32, Volatile_Full_Access,
+ Bit_Order => System.Low_Order_First;
+
+ for LATCH_Register use record
+ Val at 0 range 0 .. 31;
+ Arr at 0 range 0 .. 31;
+ end record;
+
+ -- Select between default DETECT signal behaviour and LDETECT mode
+ type DETECTMODE_DETECTMODE_Field is
+ (-- DETECT directly connected to PIN DETECT signals
+ Default,
+ -- Use the latched LDETECT behaviour
+ Ldetect)
+ with Size => 1;
+ for DETECTMODE_DETECTMODE_Field use
+ (Default => 0,
+ Ldetect => 1);
+
+ -- Select between default DETECT signal behaviour and LDETECT mode
+ type DETECTMODE_Register is record
+ -- Select between default DETECT signal behaviour and LDETECT mode
+ DETECTMODE : DETECTMODE_DETECTMODE_Field :=
+ Interfaces.NRF52.GPIO.Default;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for DETECTMODE_Register use record
+ DETECTMODE at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Pin direction. Same physical register as DIR register
+ type PIN_CNF_DIR_Field is
+ (-- Configure pin as an input pin
+ Input,
+ -- Configure pin as an output pin
+ Output)
+ with Size => 1;
+ for PIN_CNF_DIR_Field use
+ (Input => 0,
+ Output => 1);
+
+ -- Connect or disconnect input buffer
+ type PIN_CNF_INPUT_Field is
+ (-- Connect input buffer
+ Connect,
+ -- Disconnect input buffer
+ Disconnect)
+ with Size => 1;
+ for PIN_CNF_INPUT_Field use
+ (Connect => 0,
+ Disconnect => 1);
+
+ -- Pull configuration
+ type PIN_CNF_PULL_Field is
+ (-- No pull
+ Disabled,
+ -- Pull down on pin
+ Pulldown,
+ -- Pull up on pin
+ Pullup)
+ with Size => 2;
+ for PIN_CNF_PULL_Field use
+ (Disabled => 0,
+ Pulldown => 1,
+ Pullup => 3);
+
+ -- Drive configuration
+ type PIN_CNF_DRIVE_Field is
+ (-- Standard '0', standard '1'
+ S0S1,
+ -- High drive '0', standard '1'
+ H0S1,
+ -- Standard '0', high drive '1'
+ S0H1,
+ -- High drive '0', high 'drive '1''
+ H0H1,
+ -- Disconnect '0' standard '1' (normally used for wired-or connections)
+ D0S1,
+ -- Disconnect '0', high drive '1' (normally used for wired-or connections)
+ D0H1,
+ -- Standard '0'. disconnect '1' (normally used for wired-and connections)
+ S0D1,
+ -- High drive '0', disconnect '1' (normally used for wired-and connections)
+ H0D1)
+ with Size => 3;
+ for PIN_CNF_DRIVE_Field use
+ (S0S1 => 0,
+ H0S1 => 1,
+ S0H1 => 2,
+ H0H1 => 3,
+ D0S1 => 4,
+ D0H1 => 5,
+ S0D1 => 6,
+ H0D1 => 7);
+
+ -- Pin sensing mechanism
+ type PIN_CNF_SENSE_Field is
+ (-- Disabled
+ Disabled,
+ -- Sense for high level
+ High,
+ -- Sense for low level
+ Low)
+ with Size => 2;
+ for PIN_CNF_SENSE_Field use
+ (Disabled => 0,
+ High => 2,
+ Low => 3);
+
+ -- Description collection[n]: Configuration of GPIO pins
+ type PIN_CNF_Register is record
+ -- Pin direction. Same physical register as DIR register
+ DIR : PIN_CNF_DIR_Field := Interfaces.NRF52.GPIO.Input;
+ -- Connect or disconnect input buffer
+ INPUT : PIN_CNF_INPUT_Field :=
+ Interfaces.NRF52.GPIO.Disconnect;
+ -- Pull configuration
+ PULL : PIN_CNF_PULL_Field := Interfaces.NRF52.GPIO.Disabled;
+ -- unspecified
+ Reserved_4_7 : Interfaces.NRF52.UInt4 := 16#0#;
+ -- Drive configuration
+ DRIVE : PIN_CNF_DRIVE_Field := Interfaces.NRF52.GPIO.S0S1;
+ -- unspecified
+ Reserved_11_15 : Interfaces.NRF52.UInt5 := 16#0#;
+ -- Pin sensing mechanism
+ SENSE : PIN_CNF_SENSE_Field := Interfaces.NRF52.GPIO.Disabled;
+ -- unspecified
+ Reserved_18_31 : Interfaces.NRF52.UInt14 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for PIN_CNF_Register use record
+ DIR at 0 range 0 .. 0;
+ INPUT at 0 range 1 .. 1;
+ PULL at 0 range 2 .. 3;
+ Reserved_4_7 at 0 range 4 .. 7;
+ DRIVE at 0 range 8 .. 10;
+ Reserved_11_15 at 0 range 11 .. 15;
+ SENSE at 0 range 16 .. 17;
+ Reserved_18_31 at 0 range 18 .. 31;
+ end record;
+
+ -- Description collection[n]: Configuration of GPIO pins
+ type PIN_CNF_Registers is array (0 .. 31) of PIN_CNF_Register;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ -- GPIO Port 1
+ type GPIO_Peripheral is record
+ -- Write GPIO port
+ OUT_k : aliased OUT_Register;
+ -- Set individual bits in GPIO port
+ OUTSET : aliased OUTSET_Register;
+ -- Clear individual bits in GPIO port
+ OUTCLR : aliased OUTCLR_Register;
+ -- Read GPIO port
+ IN_k : aliased IN_Register;
+ -- Direction of GPIO pins
+ DIR : aliased DIR_Register;
+ -- DIR set register
+ DIRSET : aliased DIRSET_Register;
+ -- DIR clear register
+ DIRCLR : aliased DIRCLR_Register;
+ -- Latch register indicating what GPIO pins that have met the criteria
+ -- set in the PIN_CNF[n].SENSE registers
+ LATCH : aliased LATCH_Register;
+ -- Select between default DETECT signal behaviour and LDETECT mode
+ DETECTMODE : aliased DETECTMODE_Register;
+ -- Description collection[n]: Configuration of GPIO pins
+ PIN_CNF : aliased PIN_CNF_Registers;
+ end record
+ with Volatile;
+
+ for GPIO_Peripheral use record
+ OUT_k at 16#504# range 0 .. 31;
+ OUTSET at 16#508# range 0 .. 31;
+ OUTCLR at 16#50C# range 0 .. 31;
+ IN_k at 16#510# range 0 .. 31;
+ DIR at 16#514# range 0 .. 31;
+ DIRSET at 16#518# range 0 .. 31;
+ DIRCLR at 16#51C# range 0 .. 31;
+ LATCH at 16#520# range 0 .. 31;
+ DETECTMODE at 16#524# range 0 .. 31;
+ PIN_CNF at 16#700# range 0 .. 1023;
+ end record;
+
+ -- GPIO Port 1
+ P0_Periph : aliased GPIO_Peripheral
+ with Import, Address => P0_Base;
+
+ -- GPIO Port 2
+ P1_Periph : aliased GPIO_Peripheral
+ with Import, Address => P1_Base;
+
+end Interfaces.NRF52.GPIO;
diff --git a/arm/nordic/nrf52/nrf52840/svd/i-nrf52-nvmc.ads b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-nvmc.ads
new file mode 100644
index 00000000..b401767f
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-nvmc.ads
@@ -0,0 +1,335 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update
+-- for such product, must reproduce the above copyright notice, this list
+-- of conditions and the following disclaimer in the documentation and/or
+-- other materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from
+-- this software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52840.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.NVMC is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ -- NVMC is ready or busy
+ type READY_READY_Field is
+ (-- NVMC is busy (on-going write or erase operation)
+ Busy,
+ -- NVMC is ready
+ Ready)
+ with Size => 1;
+ for READY_READY_Field use
+ (Busy => 0,
+ Ready => 1);
+
+ -- Ready flag
+ type READY_Register is record
+ -- Read-only. NVMC is ready or busy
+ READY : READY_READY_Field;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for READY_Register use record
+ READY at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- NVMC can accept a new write operation
+ type READYNEXT_READYNEXT_Field is
+ (-- NVMC cannot accept any write operation
+ Busy,
+ -- NVMC is ready
+ Ready)
+ with Size => 1;
+ for READYNEXT_READYNEXT_Field use
+ (Busy => 0,
+ Ready => 1);
+
+ -- Ready flag
+ type READYNEXT_Register is record
+ -- Read-only. NVMC can accept a new write operation
+ READYNEXT : READYNEXT_READYNEXT_Field;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for READYNEXT_Register use record
+ READYNEXT at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Program memory access mode. It is strongly recommended to only activate
+ -- erase and write modes when they are actively used. Enabling write or
+ -- erase will invalidate the cache and keep it invalidated.
+ type CONFIG_WEN_Field is
+ (-- Read only access
+ Ren,
+ -- Write enabled
+ Wen,
+ -- Erase enabled
+ Een)
+ with Size => 2;
+ for CONFIG_WEN_Field use
+ (Ren => 0,
+ Wen => 1,
+ Een => 2);
+
+ -- Configuration register
+ type CONFIG_Register is record
+ -- Program memory access mode. It is strongly recommended to only
+ -- activate erase and write modes when they are actively used. Enabling
+ -- write or erase will invalidate the cache and keep it invalidated.
+ WEN : CONFIG_WEN_Field := Interfaces.NRF52.NVMC.Ren;
+ -- unspecified
+ Reserved_2_31 : Interfaces.NRF52.UInt30 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for CONFIG_Register use record
+ WEN at 0 range 0 .. 1;
+ Reserved_2_31 at 0 range 2 .. 31;
+ end record;
+
+ -- Erase all non-volatile memory including UICR registers. Note that the
+ -- erase must be enabled using CONFIG.WEN before the non-volatile memory
+ -- can be erased.
+ type ERASEALL_ERASEALL_Field is
+ (-- No operation
+ Nooperation,
+ -- Start chip erase
+ Erase)
+ with Size => 1;
+ for ERASEALL_ERASEALL_Field use
+ (Nooperation => 0,
+ Erase => 1);
+
+ -- Register for erasing all non-volatile user memory
+ type ERASEALL_Register is record
+ -- Erase all non-volatile memory including UICR registers. Note that the
+ -- erase must be enabled using CONFIG.WEN before the non-volatile memory
+ -- can be erased.
+ ERASEALL : ERASEALL_ERASEALL_Field :=
+ Interfaces.NRF52.NVMC.Nooperation;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for ERASEALL_Register use record
+ ERASEALL at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Register starting erase of all user information configuration registers.
+ -- Note that the erase must be enabled using CONFIG.WEN before the UICR can
+ -- be erased.
+ type ERASEUICR_ERASEUICR_Field is
+ (-- No operation
+ Nooperation,
+ -- Start erase of UICR
+ Erase)
+ with Size => 1;
+ for ERASEUICR_ERASEUICR_Field use
+ (Nooperation => 0,
+ Erase => 1);
+
+ -- Register for erasing user information configuration registers
+ type ERASEUICR_Register is record
+ -- Register starting erase of all user information configuration
+ -- registers. Note that the erase must be enabled using CONFIG.WEN
+ -- before the UICR can be erased.
+ ERASEUICR : ERASEUICR_ERASEUICR_Field :=
+ Interfaces.NRF52.NVMC.Nooperation;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for ERASEUICR_Register use record
+ ERASEUICR at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype ERASEPAGEPARTIALCFG_DURATION_Field is Interfaces.NRF52.UInt7;
+
+ -- Register for partial erase configuration
+ type ERASEPAGEPARTIALCFG_Register is record
+ -- Duration of the partial erase in milliseconds
+ DURATION : ERASEPAGEPARTIALCFG_DURATION_Field := 16#A#;
+ -- unspecified
+ Reserved_7_31 : Interfaces.NRF52.UInt25 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for ERASEPAGEPARTIALCFG_Register use record
+ DURATION at 0 range 0 .. 6;
+ Reserved_7_31 at 0 range 7 .. 31;
+ end record;
+
+ -- Cache enable
+ type ICACHECNF_CACHEEN_Field is
+ (-- Disable cache. Invalidates all cache entries.
+ Disabled,
+ -- Enable cache
+ Enabled)
+ with Size => 1;
+ for ICACHECNF_CACHEEN_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Cache profiling enable
+ type ICACHECNF_CACHEPROFEN_Field is
+ (-- Disable cache profiling
+ Disabled,
+ -- Enable cache profiling
+ Enabled)
+ with Size => 1;
+ for ICACHECNF_CACHEPROFEN_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- I-code cache configuration register.
+ type ICACHECNF_Register is record
+ -- Cache enable
+ CACHEEN : ICACHECNF_CACHEEN_Field :=
+ Interfaces.NRF52.NVMC.Disabled;
+ -- unspecified
+ Reserved_1_7 : Interfaces.NRF52.UInt7 := 16#0#;
+ -- Cache profiling enable
+ CACHEPROFEN : ICACHECNF_CACHEPROFEN_Field :=
+ Interfaces.NRF52.NVMC.Disabled;
+ -- unspecified
+ Reserved_9_31 : Interfaces.NRF52.UInt23 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for ICACHECNF_Register use record
+ CACHEEN at 0 range 0 .. 0;
+ Reserved_1_7 at 0 range 1 .. 7;
+ CACHEPROFEN at 0 range 8 .. 8;
+ Reserved_9_31 at 0 range 9 .. 31;
+ end record;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ type NVMC_Disc is
+ (Age,
+ Cr1);
+
+ -- Non Volatile Memory Controller
+ type NVMC_Peripheral
+ (Discriminent : NVMC_Disc := Age)
+ is record
+ -- Ready flag
+ READY : aliased READY_Register;
+ -- Ready flag
+ READYNEXT : aliased READYNEXT_Register;
+ -- Configuration register
+ CONFIG : aliased CONFIG_Register;
+ -- Register for erasing all non-volatile user memory
+ ERASEALL : aliased ERASEALL_Register;
+ -- Deprecated register - Register for erasing a page in code area.
+ -- Equivalent to ERASEPAGE.
+ ERASEPCR0 : aliased Interfaces.NRF52.UInt32;
+ -- Register for erasing user information configuration registers
+ ERASEUICR : aliased ERASEUICR_Register;
+ -- Register for partial erase of a page in code area
+ ERASEPAGEPARTIAL : aliased Interfaces.NRF52.UInt32;
+ -- Register for partial erase configuration
+ ERASEPAGEPARTIALCFG : aliased ERASEPAGEPARTIALCFG_Register;
+ -- I-code cache configuration register.
+ ICACHECNF : aliased ICACHECNF_Register;
+ -- I-code cache hit counter.
+ IHIT : aliased Interfaces.NRF52.UInt32;
+ -- I-code cache miss counter.
+ IMISS : aliased Interfaces.NRF52.UInt32;
+ case Discriminent is
+ when Age =>
+ -- Register for erasing a page in code area
+ ERASEPAGE : aliased Interfaces.NRF52.UInt32;
+ when Cr1 =>
+ -- Deprecated register - Register for erasing a page in code area.
+ -- Equivalent to ERASEPAGE.
+ ERASEPCR1 : aliased Interfaces.NRF52.UInt32;
+ end case;
+ end record
+ with Unchecked_Union, Volatile;
+
+ for NVMC_Peripheral use record
+ READY at 16#400# range 0 .. 31;
+ READYNEXT at 16#408# range 0 .. 31;
+ CONFIG at 16#504# range 0 .. 31;
+ ERASEALL at 16#50C# range 0 .. 31;
+ ERASEPCR0 at 16#510# range 0 .. 31;
+ ERASEUICR at 16#514# range 0 .. 31;
+ ERASEPAGEPARTIAL at 16#518# range 0 .. 31;
+ ERASEPAGEPARTIALCFG at 16#51C# range 0 .. 31;
+ ICACHECNF at 16#540# range 0 .. 31;
+ IHIT at 16#548# range 0 .. 31;
+ IMISS at 16#54C# range 0 .. 31;
+ ERASEPAGE at 16#508# range 0 .. 31;
+ ERASEPCR1 at 16#508# range 0 .. 31;
+ end record;
+
+ -- Non Volatile Memory Controller
+ NVMC_Periph : aliased NVMC_Peripheral
+ with Import, Address => NVMC_Base;
+
+end Interfaces.NRF52.NVMC;
diff --git a/arm/nordic/nrf52/nrf52840/svd/i-nrf52-rtc.ads b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-rtc.ads
new file mode 100644
index 00000000..d9049109
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-rtc.ads
@@ -0,0 +1,849 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update
+-- for such product, must reproduce the above copyright notice, this list
+-- of conditions and the following disclaimer in the documentation and/or
+-- other materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from
+-- this software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52840.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.RTC is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ subtype TASKS_START_TASKS_START_Field is Interfaces.NRF52.Bit;
+
+ -- Start RTC COUNTER
+ type TASKS_START_Register is record
+ -- Write-only.
+ TASKS_START : TASKS_START_TASKS_START_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_START_Register use record
+ TASKS_START at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_STOP_TASKS_STOP_Field is Interfaces.NRF52.Bit;
+
+ -- Stop RTC COUNTER
+ type TASKS_STOP_Register is record
+ -- Write-only.
+ TASKS_STOP : TASKS_STOP_TASKS_STOP_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_STOP_Register use record
+ TASKS_STOP at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_CLEAR_TASKS_CLEAR_Field is Interfaces.NRF52.Bit;
+
+ -- Clear RTC COUNTER
+ type TASKS_CLEAR_Register is record
+ -- Write-only.
+ TASKS_CLEAR : TASKS_CLEAR_TASKS_CLEAR_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_CLEAR_Register use record
+ TASKS_CLEAR at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Field is Interfaces.NRF52.Bit;
+
+ -- Set COUNTER to 0xFFFFF0
+ type TASKS_TRIGOVRFLW_Register is record
+ -- Write-only.
+ TASKS_TRIGOVRFLW : TASKS_TRIGOVRFLW_TASKS_TRIGOVRFLW_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_TRIGOVRFLW_Register use record
+ TASKS_TRIGOVRFLW at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_TICK_EVENTS_TICK_Field is Interfaces.NRF52.Bit;
+
+ -- Event on COUNTER increment
+ type EVENTS_TICK_Register is record
+ EVENTS_TICK : EVENTS_TICK_EVENTS_TICK_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_TICK_Register use record
+ EVENTS_TICK at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_OVRFLW_EVENTS_OVRFLW_Field is Interfaces.NRF52.Bit;
+
+ -- Event on COUNTER overflow
+ type EVENTS_OVRFLW_Register is record
+ EVENTS_OVRFLW : EVENTS_OVRFLW_EVENTS_OVRFLW_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_OVRFLW_Register use record
+ EVENTS_OVRFLW at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_COMPARE_EVENTS_COMPARE_Field is Interfaces.NRF52.Bit;
+
+ -- Description collection[n]: Compare event on CC[n] match
+ type EVENTS_COMPARE_Register is record
+ EVENTS_COMPARE : EVENTS_COMPARE_EVENTS_COMPARE_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_COMPARE_Register use record
+ EVENTS_COMPARE at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Description collection[n]: Compare event on CC[n] match
+ type EVENTS_COMPARE_Registers is array (0 .. 3) of EVENTS_COMPARE_Register;
+
+ -- Write '1' to enable interrupt for TICK event
+ type INTENSET_TICK_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_TICK_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable interrupt for TICK event
+ type INTENSET_TICK_Field_1 is
+ (-- Reset value for the field
+ Intenset_Tick_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_TICK_Field_1 use
+ (Intenset_Tick_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to enable interrupt for OVRFLW event
+ type INTENSET_OVRFLW_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_OVRFLW_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable interrupt for OVRFLW event
+ type INTENSET_OVRFLW_Field_1 is
+ (-- Reset value for the field
+ Intenset_Ovrflw_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_OVRFLW_Field_1 use
+ (Intenset_Ovrflw_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to enable interrupt for COMPARE[0] event
+ type INTENSET_COMPARE0_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_COMPARE0_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable interrupt for COMPARE[0] event
+ type INTENSET_COMPARE0_Field_1 is
+ (-- Reset value for the field
+ Intenset_Compare0_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_COMPARE0_Field_1 use
+ (Intenset_Compare0_Field_Reset => 0,
+ Set => 1);
+
+ -- INTENSET_COMPARE array
+ type INTENSET_COMPARE_Field_Array is array (0 .. 3)
+ of INTENSET_COMPARE0_Field_1
+ with Component_Size => 1, Size => 4;
+
+ -- Type definition for INTENSET_COMPARE
+ type INTENSET_COMPARE_Field
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- COMPARE as a value
+ Val : Interfaces.NRF52.UInt4;
+ when True =>
+ -- COMPARE as an array
+ Arr : INTENSET_COMPARE_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 4;
+
+ for INTENSET_COMPARE_Field use record
+ Val at 0 range 0 .. 3;
+ Arr at 0 range 0 .. 3;
+ end record;
+
+ -- Enable interrupt
+ type INTENSET_Register is record
+ -- Write '1' to enable interrupt for TICK event
+ TICK : INTENSET_TICK_Field_1 := Intenset_Tick_Field_Reset;
+ -- Write '1' to enable interrupt for OVRFLW event
+ OVRFLW : INTENSET_OVRFLW_Field_1 := Intenset_Ovrflw_Field_Reset;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14 := 16#0#;
+ -- Write '1' to enable interrupt for COMPARE[0] event
+ COMPARE : INTENSET_COMPARE_Field :=
+ (As_Array => False, Val => 16#0#);
+ -- unspecified
+ Reserved_20_31 : Interfaces.NRF52.UInt12 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENSET_Register use record
+ TICK at 0 range 0 .. 0;
+ OVRFLW at 0 range 1 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ COMPARE at 0 range 16 .. 19;
+ Reserved_20_31 at 0 range 20 .. 31;
+ end record;
+
+ -- Write '1' to disable interrupt for TICK event
+ type INTENCLR_TICK_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_TICK_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable interrupt for TICK event
+ type INTENCLR_TICK_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Tick_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_TICK_Field_1 use
+ (Intenclr_Tick_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to disable interrupt for OVRFLW event
+ type INTENCLR_OVRFLW_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_OVRFLW_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable interrupt for OVRFLW event
+ type INTENCLR_OVRFLW_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Ovrflw_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_OVRFLW_Field_1 use
+ (Intenclr_Ovrflw_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to disable interrupt for COMPARE[0] event
+ type INTENCLR_COMPARE0_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_COMPARE0_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable interrupt for COMPARE[0] event
+ type INTENCLR_COMPARE0_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Compare0_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_COMPARE0_Field_1 use
+ (Intenclr_Compare0_Field_Reset => 0,
+ Clear => 1);
+
+ -- INTENCLR_COMPARE array
+ type INTENCLR_COMPARE_Field_Array is array (0 .. 3)
+ of INTENCLR_COMPARE0_Field_1
+ with Component_Size => 1, Size => 4;
+
+ -- Type definition for INTENCLR_COMPARE
+ type INTENCLR_COMPARE_Field
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- COMPARE as a value
+ Val : Interfaces.NRF52.UInt4;
+ when True =>
+ -- COMPARE as an array
+ Arr : INTENCLR_COMPARE_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 4;
+
+ for INTENCLR_COMPARE_Field use record
+ Val at 0 range 0 .. 3;
+ Arr at 0 range 0 .. 3;
+ end record;
+
+ -- Disable interrupt
+ type INTENCLR_Register is record
+ -- Write '1' to disable interrupt for TICK event
+ TICK : INTENCLR_TICK_Field_1 := Intenclr_Tick_Field_Reset;
+ -- Write '1' to disable interrupt for OVRFLW event
+ OVRFLW : INTENCLR_OVRFLW_Field_1 := Intenclr_Ovrflw_Field_Reset;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14 := 16#0#;
+ -- Write '1' to disable interrupt for COMPARE[0] event
+ COMPARE : INTENCLR_COMPARE_Field :=
+ (As_Array => False, Val => 16#0#);
+ -- unspecified
+ Reserved_20_31 : Interfaces.NRF52.UInt12 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENCLR_Register use record
+ TICK at 0 range 0 .. 0;
+ OVRFLW at 0 range 1 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ COMPARE at 0 range 16 .. 19;
+ Reserved_20_31 at 0 range 20 .. 31;
+ end record;
+
+ -- Enable or disable event routing for TICK event
+ type EVTEN_TICK_Field is
+ (-- Disable
+ Disabled,
+ -- Enable
+ Enabled)
+ with Size => 1;
+ for EVTEN_TICK_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Enable or disable event routing for OVRFLW event
+ type EVTEN_OVRFLW_Field is
+ (-- Disable
+ Disabled,
+ -- Enable
+ Enabled)
+ with Size => 1;
+ for EVTEN_OVRFLW_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Enable or disable event routing for COMPARE[0] event
+ type EVTEN_COMPARE0_Field is
+ (-- Disable
+ Disabled,
+ -- Enable
+ Enabled)
+ with Size => 1;
+ for EVTEN_COMPARE0_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- EVTEN_COMPARE array
+ type EVTEN_COMPARE_Field_Array is array (0 .. 3) of EVTEN_COMPARE0_Field
+ with Component_Size => 1, Size => 4;
+
+ -- Type definition for EVTEN_COMPARE
+ type EVTEN_COMPARE_Field
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- COMPARE as a value
+ Val : Interfaces.NRF52.UInt4;
+ when True =>
+ -- COMPARE as an array
+ Arr : EVTEN_COMPARE_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 4;
+
+ for EVTEN_COMPARE_Field use record
+ Val at 0 range 0 .. 3;
+ Arr at 0 range 0 .. 3;
+ end record;
+
+ -- Enable or disable event routing
+ type EVTEN_Register is record
+ -- Enable or disable event routing for TICK event
+ TICK : EVTEN_TICK_Field := Interfaces.NRF52.RTC.Disabled;
+ -- Enable or disable event routing for OVRFLW event
+ OVRFLW : EVTEN_OVRFLW_Field := Interfaces.NRF52.RTC.Disabled;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14 := 16#0#;
+ -- Enable or disable event routing for COMPARE[0] event
+ COMPARE : EVTEN_COMPARE_Field :=
+ (As_Array => False, Val => 16#0#);
+ -- unspecified
+ Reserved_20_31 : Interfaces.NRF52.UInt12 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVTEN_Register use record
+ TICK at 0 range 0 .. 0;
+ OVRFLW at 0 range 1 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ COMPARE at 0 range 16 .. 19;
+ Reserved_20_31 at 0 range 20 .. 31;
+ end record;
+
+ -- Write '1' to enable event routing for TICK event
+ type EVTENSET_TICK_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for EVTENSET_TICK_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable event routing for TICK event
+ type EVTENSET_TICK_Field_1 is
+ (-- Reset value for the field
+ Evtenset_Tick_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for EVTENSET_TICK_Field_1 use
+ (Evtenset_Tick_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to enable event routing for OVRFLW event
+ type EVTENSET_OVRFLW_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for EVTENSET_OVRFLW_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable event routing for OVRFLW event
+ type EVTENSET_OVRFLW_Field_1 is
+ (-- Reset value for the field
+ Evtenset_Ovrflw_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for EVTENSET_OVRFLW_Field_1 use
+ (Evtenset_Ovrflw_Field_Reset => 0,
+ Set => 1);
+
+ -- Write '1' to enable event routing for COMPARE[0] event
+ type EVTENSET_COMPARE0_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for EVTENSET_COMPARE0_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable event routing for COMPARE[0] event
+ type EVTENSET_COMPARE0_Field_1 is
+ (-- Reset value for the field
+ Evtenset_Compare0_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for EVTENSET_COMPARE0_Field_1 use
+ (Evtenset_Compare0_Field_Reset => 0,
+ Set => 1);
+
+ -- EVTENSET_COMPARE array
+ type EVTENSET_COMPARE_Field_Array is array (0 .. 3)
+ of EVTENSET_COMPARE0_Field_1
+ with Component_Size => 1, Size => 4;
+
+ -- Type definition for EVTENSET_COMPARE
+ type EVTENSET_COMPARE_Field
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- COMPARE as a value
+ Val : Interfaces.NRF52.UInt4;
+ when True =>
+ -- COMPARE as an array
+ Arr : EVTENSET_COMPARE_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 4;
+
+ for EVTENSET_COMPARE_Field use record
+ Val at 0 range 0 .. 3;
+ Arr at 0 range 0 .. 3;
+ end record;
+
+ -- Enable event routing
+ type EVTENSET_Register is record
+ -- Write '1' to enable event routing for TICK event
+ TICK : EVTENSET_TICK_Field_1 := Evtenset_Tick_Field_Reset;
+ -- Write '1' to enable event routing for OVRFLW event
+ OVRFLW : EVTENSET_OVRFLW_Field_1 := Evtenset_Ovrflw_Field_Reset;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14 := 16#0#;
+ -- Write '1' to enable event routing for COMPARE[0] event
+ COMPARE : EVTENSET_COMPARE_Field :=
+ (As_Array => False, Val => 16#0#);
+ -- unspecified
+ Reserved_20_31 : Interfaces.NRF52.UInt12 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVTENSET_Register use record
+ TICK at 0 range 0 .. 0;
+ OVRFLW at 0 range 1 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ COMPARE at 0 range 16 .. 19;
+ Reserved_20_31 at 0 range 20 .. 31;
+ end record;
+
+ -- Write '1' to disable event routing for TICK event
+ type EVTENCLR_TICK_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for EVTENCLR_TICK_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable event routing for TICK event
+ type EVTENCLR_TICK_Field_1 is
+ (-- Reset value for the field
+ Evtenclr_Tick_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for EVTENCLR_TICK_Field_1 use
+ (Evtenclr_Tick_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to disable event routing for OVRFLW event
+ type EVTENCLR_OVRFLW_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for EVTENCLR_OVRFLW_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable event routing for OVRFLW event
+ type EVTENCLR_OVRFLW_Field_1 is
+ (-- Reset value for the field
+ Evtenclr_Ovrflw_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for EVTENCLR_OVRFLW_Field_1 use
+ (Evtenclr_Ovrflw_Field_Reset => 0,
+ Clear => 1);
+
+ -- Write '1' to disable event routing for COMPARE[0] event
+ type EVTENCLR_COMPARE0_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for EVTENCLR_COMPARE0_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable event routing for COMPARE[0] event
+ type EVTENCLR_COMPARE0_Field_1 is
+ (-- Reset value for the field
+ Evtenclr_Compare0_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for EVTENCLR_COMPARE0_Field_1 use
+ (Evtenclr_Compare0_Field_Reset => 0,
+ Clear => 1);
+
+ -- EVTENCLR_COMPARE array
+ type EVTENCLR_COMPARE_Field_Array is array (0 .. 3)
+ of EVTENCLR_COMPARE0_Field_1
+ with Component_Size => 1, Size => 4;
+
+ -- Type definition for EVTENCLR_COMPARE
+ type EVTENCLR_COMPARE_Field
+ (As_Array : Boolean := False)
+ is record
+ case As_Array is
+ when False =>
+ -- COMPARE as a value
+ Val : Interfaces.NRF52.UInt4;
+ when True =>
+ -- COMPARE as an array
+ Arr : EVTENCLR_COMPARE_Field_Array;
+ end case;
+ end record
+ with Unchecked_Union, Size => 4;
+
+ for EVTENCLR_COMPARE_Field use record
+ Val at 0 range 0 .. 3;
+ Arr at 0 range 0 .. 3;
+ end record;
+
+ -- Disable event routing
+ type EVTENCLR_Register is record
+ -- Write '1' to disable event routing for TICK event
+ TICK : EVTENCLR_TICK_Field_1 := Evtenclr_Tick_Field_Reset;
+ -- Write '1' to disable event routing for OVRFLW event
+ OVRFLW : EVTENCLR_OVRFLW_Field_1 := Evtenclr_Ovrflw_Field_Reset;
+ -- unspecified
+ Reserved_2_15 : Interfaces.NRF52.UInt14 := 16#0#;
+ -- Write '1' to disable event routing for COMPARE[0] event
+ COMPARE : EVTENCLR_COMPARE_Field :=
+ (As_Array => False, Val => 16#0#);
+ -- unspecified
+ Reserved_20_31 : Interfaces.NRF52.UInt12 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVTENCLR_Register use record
+ TICK at 0 range 0 .. 0;
+ OVRFLW at 0 range 1 .. 1;
+ Reserved_2_15 at 0 range 2 .. 15;
+ COMPARE at 0 range 16 .. 19;
+ Reserved_20_31 at 0 range 20 .. 31;
+ end record;
+
+ subtype COUNTER_COUNTER_Field is Interfaces.NRF52.UInt24;
+
+ -- Current COUNTER value
+ type COUNTER_Register is record
+ -- Read-only. Counter value
+ COUNTER : COUNTER_COUNTER_Field;
+ -- unspecified
+ Reserved_24_31 : Interfaces.NRF52.Byte;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for COUNTER_Register use record
+ COUNTER at 0 range 0 .. 23;
+ Reserved_24_31 at 0 range 24 .. 31;
+ end record;
+
+ subtype PRESCALER_PRESCALER_Field is Interfaces.NRF52.UInt12;
+
+ -- 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be
+ -- written when RTC is stopped
+ type PRESCALER_Register is record
+ -- Prescaler value
+ PRESCALER : PRESCALER_PRESCALER_Field := 16#0#;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for PRESCALER_Register use record
+ PRESCALER at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype CC_COMPARE_Field is Interfaces.NRF52.UInt24;
+
+ -- Description collection[n]: Compare register n
+ type CC_Register is record
+ -- Compare value
+ COMPARE : CC_COMPARE_Field := 16#0#;
+ -- unspecified
+ Reserved_24_31 : Interfaces.NRF52.Byte := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for CC_Register use record
+ COMPARE at 0 range 0 .. 23;
+ Reserved_24_31 at 0 range 24 .. 31;
+ end record;
+
+ -- Description collection[n]: Compare register n
+ type CC_Registers is array (0 .. 3) of CC_Register;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ -- Real time counter 0
+ type RTC_Peripheral is record
+ -- Start RTC COUNTER
+ TASKS_START : aliased TASKS_START_Register;
+ -- Stop RTC COUNTER
+ TASKS_STOP : aliased TASKS_STOP_Register;
+ -- Clear RTC COUNTER
+ TASKS_CLEAR : aliased TASKS_CLEAR_Register;
+ -- Set COUNTER to 0xFFFFF0
+ TASKS_TRIGOVRFLW : aliased TASKS_TRIGOVRFLW_Register;
+ -- Event on COUNTER increment
+ EVENTS_TICK : aliased EVENTS_TICK_Register;
+ -- Event on COUNTER overflow
+ EVENTS_OVRFLW : aliased EVENTS_OVRFLW_Register;
+ -- Description collection[n]: Compare event on CC[n] match
+ EVENTS_COMPARE : aliased EVENTS_COMPARE_Registers;
+ -- Enable interrupt
+ INTENSET : aliased INTENSET_Register;
+ -- Disable interrupt
+ INTENCLR : aliased INTENCLR_Register;
+ -- Enable or disable event routing
+ EVTEN : aliased EVTEN_Register;
+ -- Enable event routing
+ EVTENSET : aliased EVTENSET_Register;
+ -- Disable event routing
+ EVTENCLR : aliased EVTENCLR_Register;
+ -- Current COUNTER value
+ COUNTER : aliased COUNTER_Register;
+ -- 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be
+ -- written when RTC is stopped
+ PRESCALER : aliased PRESCALER_Register;
+ -- Description collection[n]: Compare register n
+ CC : aliased CC_Registers;
+ end record
+ with Volatile;
+
+ for RTC_Peripheral use record
+ TASKS_START at 16#0# range 0 .. 31;
+ TASKS_STOP at 16#4# range 0 .. 31;
+ TASKS_CLEAR at 16#8# range 0 .. 31;
+ TASKS_TRIGOVRFLW at 16#C# range 0 .. 31;
+ EVENTS_TICK at 16#100# range 0 .. 31;
+ EVENTS_OVRFLW at 16#104# range 0 .. 31;
+ EVENTS_COMPARE at 16#140# range 0 .. 127;
+ INTENSET at 16#304# range 0 .. 31;
+ INTENCLR at 16#308# range 0 .. 31;
+ EVTEN at 16#340# range 0 .. 31;
+ EVTENSET at 16#344# range 0 .. 31;
+ EVTENCLR at 16#348# range 0 .. 31;
+ COUNTER at 16#504# range 0 .. 31;
+ PRESCALER at 16#508# range 0 .. 31;
+ CC at 16#540# range 0 .. 127;
+ end record;
+
+ -- Real time counter 0
+ RTC0_Periph : aliased RTC_Peripheral
+ with Import, Address => RTC0_Base;
+
+ -- Real time counter 1
+ RTC1_Periph : aliased RTC_Peripheral
+ with Import, Address => RTC1_Base;
+
+ -- Real time counter 2
+ RTC2_Periph : aliased RTC_Peripheral
+ with Import, Address => RTC2_Base;
+
+end Interfaces.NRF52.RTC;
diff --git a/arm/nordic/nrf52/nrf52840/svd/i-nrf52-temp.ads b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-temp.ads
new file mode 100644
index 00000000..51f318f6
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-temp.ads
@@ -0,0 +1,559 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update
+-- for such product, must reproduce the above copyright notice, this list
+-- of conditions and the following disclaimer in the documentation and/or
+-- other materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from
+-- this software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52840.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.TEMP is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ subtype TASKS_START_TASKS_START_Field is Interfaces.NRF52.Bit;
+
+ -- Start temperature measurement
+ type TASKS_START_Register is record
+ -- Write-only.
+ TASKS_START : TASKS_START_TASKS_START_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_START_Register use record
+ TASKS_START at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype TASKS_STOP_TASKS_STOP_Field is Interfaces.NRF52.Bit;
+
+ -- Stop temperature measurement
+ type TASKS_STOP_Register is record
+ -- Write-only.
+ TASKS_STOP : TASKS_STOP_TASKS_STOP_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for TASKS_STOP_Register use record
+ TASKS_STOP at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype EVENTS_DATARDY_EVENTS_DATARDY_Field is Interfaces.NRF52.Bit;
+
+ -- Temperature measurement complete, data ready
+ type EVENTS_DATARDY_Register is record
+ EVENTS_DATARDY : EVENTS_DATARDY_EVENTS_DATARDY_Field := 16#0#;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for EVENTS_DATARDY_Register use record
+ EVENTS_DATARDY at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Write '1' to enable interrupt for DATARDY event
+ type INTENSET_DATARDY_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENSET_DATARDY_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to enable interrupt for DATARDY event
+ type INTENSET_DATARDY_Field_1 is
+ (-- Reset value for the field
+ Intenset_Datardy_Field_Reset,
+ -- Enable
+ Set)
+ with Size => 1;
+ for INTENSET_DATARDY_Field_1 use
+ (Intenset_Datardy_Field_Reset => 0,
+ Set => 1);
+
+ -- Enable interrupt
+ type INTENSET_Register is record
+ -- Write '1' to enable interrupt for DATARDY event
+ DATARDY : INTENSET_DATARDY_Field_1 :=
+ Intenset_Datardy_Field_Reset;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENSET_Register use record
+ DATARDY at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Write '1' to disable interrupt for DATARDY event
+ type INTENCLR_DATARDY_Field is
+ (-- Read: Disabled
+ Disabled,
+ -- Read: Enabled
+ Enabled)
+ with Size => 1;
+ for INTENCLR_DATARDY_Field use
+ (Disabled => 0,
+ Enabled => 1);
+
+ -- Write '1' to disable interrupt for DATARDY event
+ type INTENCLR_DATARDY_Field_1 is
+ (-- Reset value for the field
+ Intenclr_Datardy_Field_Reset,
+ -- Disable
+ Clear)
+ with Size => 1;
+ for INTENCLR_DATARDY_Field_1 use
+ (Intenclr_Datardy_Field_Reset => 0,
+ Clear => 1);
+
+ -- Disable interrupt
+ type INTENCLR_Register is record
+ -- Write '1' to disable interrupt for DATARDY event
+ DATARDY : INTENCLR_DATARDY_Field_1 :=
+ Intenclr_Datardy_Field_Reset;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for INTENCLR_Register use record
+ DATARDY at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ subtype A0_A0_Field is Interfaces.NRF52.UInt12;
+
+ -- Slope of 1st piece wise linear function
+ type A0_Register is record
+ -- Slope of 1st piece wise linear function
+ A0 : A0_A0_Field := 16#326#;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for A0_Register use record
+ A0 at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype A1_A1_Field is Interfaces.NRF52.UInt12;
+
+ -- Slope of 2nd piece wise linear function
+ type A1_Register is record
+ -- Slope of 2nd piece wise linear function
+ A1 : A1_A1_Field := 16#348#;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for A1_Register use record
+ A1 at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype A2_A2_Field is Interfaces.NRF52.UInt12;
+
+ -- Slope of 3rd piece wise linear function
+ type A2_Register is record
+ -- Slope of 3rd piece wise linear function
+ A2 : A2_A2_Field := 16#3AA#;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for A2_Register use record
+ A2 at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype A3_A3_Field is Interfaces.NRF52.UInt12;
+
+ -- Slope of 4th piece wise linear function
+ type A3_Register is record
+ -- Slope of 4th piece wise linear function
+ A3 : A3_A3_Field := 16#40E#;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for A3_Register use record
+ A3 at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype A4_A4_Field is Interfaces.NRF52.UInt12;
+
+ -- Slope of 5th piece wise linear function
+ type A4_Register is record
+ -- Slope of 5th piece wise linear function
+ A4 : A4_A4_Field := 16#4BD#;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for A4_Register use record
+ A4 at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype A5_A5_Field is Interfaces.NRF52.UInt12;
+
+ -- Slope of 6th piece wise linear function
+ type A5_Register is record
+ -- Slope of 6th piece wise linear function
+ A5 : A5_A5_Field := 16#5A3#;
+ -- unspecified
+ Reserved_12_31 : Interfaces.NRF52.UInt20 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for A5_Register use record
+ A5 at 0 range 0 .. 11;
+ Reserved_12_31 at 0 range 12 .. 31;
+ end record;
+
+ subtype B0_B0_Field is Interfaces.NRF52.UInt14;
+
+ -- y-intercept of 1st piece wise linear function
+ type B0_Register is record
+ -- y-intercept of 1st piece wise linear function
+ B0 : B0_B0_Field := 16#3FEF#;
+ -- unspecified
+ Reserved_14_31 : Interfaces.NRF52.UInt18 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for B0_Register use record
+ B0 at 0 range 0 .. 13;
+ Reserved_14_31 at 0 range 14 .. 31;
+ end record;
+
+ subtype B1_B1_Field is Interfaces.NRF52.UInt14;
+
+ -- y-intercept of 2nd piece wise linear function
+ type B1_Register is record
+ -- y-intercept of 2nd piece wise linear function
+ B1 : B1_B1_Field := 16#3FBE#;
+ -- unspecified
+ Reserved_14_31 : Interfaces.NRF52.UInt18 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for B1_Register use record
+ B1 at 0 range 0 .. 13;
+ Reserved_14_31 at 0 range 14 .. 31;
+ end record;
+
+ subtype B2_B2_Field is Interfaces.NRF52.UInt14;
+
+ -- y-intercept of 3rd piece wise linear function
+ type B2_Register is record
+ -- y-intercept of 3rd piece wise linear function
+ B2 : B2_B2_Field := 16#3FBE#;
+ -- unspecified
+ Reserved_14_31 : Interfaces.NRF52.UInt18 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for B2_Register use record
+ B2 at 0 range 0 .. 13;
+ Reserved_14_31 at 0 range 14 .. 31;
+ end record;
+
+ subtype B3_B3_Field is Interfaces.NRF52.UInt14;
+
+ -- y-intercept of 4th piece wise linear function
+ type B3_Register is record
+ -- y-intercept of 4th piece wise linear function
+ B3 : B3_B3_Field := 16#12#;
+ -- unspecified
+ Reserved_14_31 : Interfaces.NRF52.UInt18 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for B3_Register use record
+ B3 at 0 range 0 .. 13;
+ Reserved_14_31 at 0 range 14 .. 31;
+ end record;
+
+ subtype B4_B4_Field is Interfaces.NRF52.UInt14;
+
+ -- y-intercept of 5th piece wise linear function
+ type B4_Register is record
+ -- y-intercept of 5th piece wise linear function
+ B4 : B4_B4_Field := 16#124#;
+ -- unspecified
+ Reserved_14_31 : Interfaces.NRF52.UInt18 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for B4_Register use record
+ B4 at 0 range 0 .. 13;
+ Reserved_14_31 at 0 range 14 .. 31;
+ end record;
+
+ subtype B5_B5_Field is Interfaces.NRF52.UInt14;
+
+ -- y-intercept of 6th piece wise linear function
+ type B5_Register is record
+ -- y-intercept of 6th piece wise linear function
+ B5 : B5_B5_Field := 16#27C#;
+ -- unspecified
+ Reserved_14_31 : Interfaces.NRF52.UInt18 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for B5_Register use record
+ B5 at 0 range 0 .. 13;
+ Reserved_14_31 at 0 range 14 .. 31;
+ end record;
+
+ subtype T0_T0_Field is Interfaces.NRF52.Byte;
+
+ -- End point of 1st piece wise linear function
+ type T0_Register is record
+ -- End point of 1st piece wise linear function
+ T0 : T0_T0_Field := 16#E2#;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for T0_Register use record
+ T0 at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ subtype T1_T1_Field is Interfaces.NRF52.Byte;
+
+ -- End point of 2nd piece wise linear function
+ type T1_Register is record
+ -- End point of 2nd piece wise linear function
+ T1 : T1_T1_Field := 16#0#;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for T1_Register use record
+ T1 at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ subtype T2_T2_Field is Interfaces.NRF52.Byte;
+
+ -- End point of 3rd piece wise linear function
+ type T2_Register is record
+ -- End point of 3rd piece wise linear function
+ T2 : T2_T2_Field := 16#19#;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for T2_Register use record
+ T2 at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ subtype T3_T3_Field is Interfaces.NRF52.Byte;
+
+ -- End point of 4th piece wise linear function
+ type T3_Register is record
+ -- End point of 4th piece wise linear function
+ T3 : T3_T3_Field := 16#3C#;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for T3_Register use record
+ T3 at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ subtype T4_T4_Field is Interfaces.NRF52.Byte;
+
+ -- End point of 5th piece wise linear function
+ type T4_Register is record
+ -- End point of 5th piece wise linear function
+ T4 : T4_T4_Field := 16#50#;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#0#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for T4_Register use record
+ T4 at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ -- Temperature Sensor
+ type TEMP_Peripheral is record
+ -- Start temperature measurement
+ TASKS_START : aliased TASKS_START_Register;
+ -- Stop temperature measurement
+ TASKS_STOP : aliased TASKS_STOP_Register;
+ -- Temperature measurement complete, data ready
+ EVENTS_DATARDY : aliased EVENTS_DATARDY_Register;
+ -- Enable interrupt
+ INTENSET : aliased INTENSET_Register;
+ -- Disable interrupt
+ INTENCLR : aliased INTENCLR_Register;
+ -- Temperature in degC (0.25deg steps)
+ TEMP : aliased Interfaces.NRF52.UInt32;
+ -- Slope of 1st piece wise linear function
+ A0 : aliased A0_Register;
+ -- Slope of 2nd piece wise linear function
+ A1 : aliased A1_Register;
+ -- Slope of 3rd piece wise linear function
+ A2 : aliased A2_Register;
+ -- Slope of 4th piece wise linear function
+ A3 : aliased A3_Register;
+ -- Slope of 5th piece wise linear function
+ A4 : aliased A4_Register;
+ -- Slope of 6th piece wise linear function
+ A5 : aliased A5_Register;
+ -- y-intercept of 1st piece wise linear function
+ B0 : aliased B0_Register;
+ -- y-intercept of 2nd piece wise linear function
+ B1 : aliased B1_Register;
+ -- y-intercept of 3rd piece wise linear function
+ B2 : aliased B2_Register;
+ -- y-intercept of 4th piece wise linear function
+ B3 : aliased B3_Register;
+ -- y-intercept of 5th piece wise linear function
+ B4 : aliased B4_Register;
+ -- y-intercept of 6th piece wise linear function
+ B5 : aliased B5_Register;
+ -- End point of 1st piece wise linear function
+ T0 : aliased T0_Register;
+ -- End point of 2nd piece wise linear function
+ T1 : aliased T1_Register;
+ -- End point of 3rd piece wise linear function
+ T2 : aliased T2_Register;
+ -- End point of 4th piece wise linear function
+ T3 : aliased T3_Register;
+ -- End point of 5th piece wise linear function
+ T4 : aliased T4_Register;
+ end record
+ with Volatile;
+
+ for TEMP_Peripheral use record
+ TASKS_START at 16#0# range 0 .. 31;
+ TASKS_STOP at 16#4# range 0 .. 31;
+ EVENTS_DATARDY at 16#100# range 0 .. 31;
+ INTENSET at 16#304# range 0 .. 31;
+ INTENCLR at 16#308# range 0 .. 31;
+ TEMP at 16#508# range 0 .. 31;
+ A0 at 16#520# range 0 .. 31;
+ A1 at 16#524# range 0 .. 31;
+ A2 at 16#528# range 0 .. 31;
+ A3 at 16#52C# range 0 .. 31;
+ A4 at 16#530# range 0 .. 31;
+ A5 at 16#534# range 0 .. 31;
+ B0 at 16#540# range 0 .. 31;
+ B1 at 16#544# range 0 .. 31;
+ B2 at 16#548# range 0 .. 31;
+ B3 at 16#54C# range 0 .. 31;
+ B4 at 16#550# range 0 .. 31;
+ B5 at 16#554# range 0 .. 31;
+ T0 at 16#560# range 0 .. 31;
+ T1 at 16#564# range 0 .. 31;
+ T2 at 16#568# range 0 .. 31;
+ T3 at 16#56C# range 0 .. 31;
+ T4 at 16#570# range 0 .. 31;
+ end record;
+
+ -- Temperature Sensor
+ TEMP_Periph : aliased TEMP_Peripheral
+ with Import, Address => TEMP_Base;
+
+end Interfaces.NRF52.TEMP;
diff --git a/arm/nordic/nrf52/nrf52840/svd/i-nrf52-uicr.ads b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-uicr.ads
new file mode 100644
index 00000000..144d511f
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52840/svd/i-nrf52-uicr.ads
@@ -0,0 +1,304 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update
+-- for such product, must reproduce the above copyright notice, this list
+-- of conditions and the following disclaimer in the documentation and/or
+-- other materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from
+-- this software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52840.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+package Interfaces.NRF52.UICR is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Registers --
+ ---------------
+
+ -- Description collection[n]: Reserved for Nordic firmware design
+
+ -- Description collection[n]: Reserved for Nordic firmware design
+ type NRFFW_Registers is array (0 .. 14) of Interfaces.NRF52.UInt32;
+
+ -- Description collection[n]: Reserved for Nordic hardware design
+
+ -- Description collection[n]: Reserved for Nordic hardware design
+ type NRFHW_Registers is array (0 .. 11) of Interfaces.NRF52.UInt32;
+
+ -- Description collection[n]: Reserved for customer
+
+ -- Description collection[n]: Reserved for customer
+ type CUSTOMER_Registers is array (0 .. 31) of Interfaces.NRF52.UInt32;
+
+ subtype PSELRESET_PIN_Field is Interfaces.NRF52.UInt5;
+ subtype PSELRESET_PORT_Field is Interfaces.NRF52.Bit;
+
+ -- Connection
+ type PSELRESET_CONNECT_Field is
+ (-- Connect
+ Connected,
+ -- Disconnect
+ Disconnected)
+ with Size => 1;
+ for PSELRESET_CONNECT_Field use
+ (Connected => 0,
+ Disconnected => 1);
+
+ -- Description collection[n]: Mapping of the nRESET function
+ type PSELRESET_Register is record
+ -- Pin number of PORT onto which nRESET is exposed
+ PIN : PSELRESET_PIN_Field := 16#1F#;
+ -- Port number onto which nRESET is exposed
+ PORT : PSELRESET_PORT_Field := 16#1#;
+ -- unspecified
+ Reserved_6_30 : Interfaces.NRF52.UInt25 := 16#1FFFFFF#;
+ -- Connection
+ CONNECT : PSELRESET_CONNECT_Field :=
+ Interfaces.NRF52.UICR.Disconnected;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for PSELRESET_Register use record
+ PIN at 0 range 0 .. 4;
+ PORT at 0 range 5 .. 5;
+ Reserved_6_30 at 0 range 6 .. 30;
+ CONNECT at 0 range 31 .. 31;
+ end record;
+
+ -- Description collection[n]: Mapping of the nRESET function
+ type PSELRESET_Registers is array (0 .. 1) of PSELRESET_Register;
+
+ -- Enable or disable access port protection.
+ type APPROTECT_PALL_Field is
+ (-- Enable
+ Enabled,
+ -- Disable
+ Disabled)
+ with Size => 8;
+ for APPROTECT_PALL_Field use
+ (Enabled => 0,
+ Disabled => 255);
+
+ -- Access port protection
+ type APPROTECT_Register is record
+ -- Enable or disable access port protection.
+ PALL : APPROTECT_PALL_Field := Interfaces.NRF52.UICR.Disabled;
+ -- unspecified
+ Reserved_8_31 : Interfaces.NRF52.UInt24 := 16#FFFFFF#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for APPROTECT_Register use record
+ PALL at 0 range 0 .. 7;
+ Reserved_8_31 at 0 range 8 .. 31;
+ end record;
+
+ -- Setting of pins dedicated to NFC functionality
+ type NFCPINS_PROTECT_Field is
+ (-- Operation as GPIO pins. Same protection as normal GPIO pins
+ Disabled,
+ -- Operation as NFC antenna pins. Configures the protection for NFC operation
+ Nfc)
+ with Size => 1;
+ for NFCPINS_PROTECT_Field use
+ (Disabled => 0,
+ Nfc => 1);
+
+ -- Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
+ type NFCPINS_Register is record
+ -- Setting of pins dedicated to NFC functionality
+ PROTECT : NFCPINS_PROTECT_Field := Interfaces.NRF52.UICR.Nfc;
+ -- unspecified
+ Reserved_1_31 : Interfaces.NRF52.UInt31 := 16#7FFFFFFF#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for NFCPINS_Register use record
+ PROTECT at 0 range 0 .. 0;
+ Reserved_1_31 at 0 range 1 .. 31;
+ end record;
+
+ -- Configure CPU non-intrusive debug features
+ type DEBUGCTRL_CPUNIDEN_Field is
+ (-- Disable CPU ITM and ETM functionality
+ Disabled,
+ -- Enable CPU ITM and ETM functionality (default behavior)
+ Enabled)
+ with Size => 8;
+ for DEBUGCTRL_CPUNIDEN_Field use
+ (Disabled => 0,
+ Enabled => 255);
+
+ -- Configure CPU flash patch and breakpoint (FPB) unit behavior
+ type DEBUGCTRL_CPUFPBEN_Field is
+ (-- Disable CPU FPB unit. Writes into the FPB registers will be ignored.
+ Disabled,
+ -- Enable CPU FPB unit (default behavior)
+ Enabled)
+ with Size => 8;
+ for DEBUGCTRL_CPUFPBEN_Field use
+ (Disabled => 0,
+ Enabled => 255);
+
+ -- Processor debug control
+ type DEBUGCTRL_Register is record
+ -- Configure CPU non-intrusive debug features
+ CPUNIDEN : DEBUGCTRL_CPUNIDEN_Field :=
+ Interfaces.NRF52.UICR.Enabled;
+ -- Configure CPU flash patch and breakpoint (FPB) unit behavior
+ CPUFPBEN : DEBUGCTRL_CPUFPBEN_Field :=
+ Interfaces.NRF52.UICR.Enabled;
+ -- unspecified
+ Reserved_16_31 : Interfaces.NRF52.UInt16 := 16#FFFF#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for DEBUGCTRL_Register use record
+ CPUNIDEN at 0 range 0 .. 7;
+ CPUFPBEN at 0 range 8 .. 15;
+ Reserved_16_31 at 0 range 16 .. 31;
+ end record;
+
+ -- Output voltage from of REG0 regulator stage. The maximum output voltage
+ -- from this stage is given as VDDH - VEXDIF.
+ type REGOUT0_VOUT_Field is
+ (-- 1.8 V
+ Val_1V8,
+ -- 2.1 V
+ Val_2V1,
+ -- 2.4 V
+ Val_2V4,
+ -- 2.7 V
+ Val_2V7,
+ -- 3.0 V
+ Val_3V0,
+ -- 3.3 V
+ Val_3V3,
+ -- Default voltage: 1.8 V
+ Default)
+ with Size => 3;
+ for REGOUT0_VOUT_Field use
+ (Val_1V8 => 0,
+ Val_2V1 => 1,
+ Val_2V4 => 2,
+ Val_2V7 => 3,
+ Val_3V0 => 4,
+ Val_3V3 => 5,
+ Default => 7);
+
+ -- GPIO reference voltage / external output supply voltage in high voltage
+ -- mode
+ type REGOUT0_Register is record
+ -- Output voltage from of REG0 regulator stage. The maximum output
+ -- voltage from this stage is given as VDDH - VEXDIF.
+ VOUT : REGOUT0_VOUT_Field := Interfaces.NRF52.UICR.Default;
+ -- unspecified
+ Reserved_3_31 : Interfaces.NRF52.UInt29 := 16#1FFFFFFF#;
+ end record
+ with Volatile_Full_Access, Size => 32,
+ Bit_Order => System.Low_Order_First;
+
+ for REGOUT0_Register use record
+ VOUT at 0 range 0 .. 2;
+ Reserved_3_31 at 0 range 3 .. 31;
+ end record;
+
+ -----------------
+ -- Peripherals --
+ -----------------
+
+ -- User information configuration registers
+ type UICR_Peripheral is record
+ -- Unspecified
+ UNUSED0 : aliased Interfaces.NRF52.UInt32;
+ -- Unspecified
+ UNUSED1 : aliased Interfaces.NRF52.UInt32;
+ -- Unspecified
+ UNUSED2 : aliased Interfaces.NRF52.UInt32;
+ -- Unspecified
+ UNUSED3 : aliased Interfaces.NRF52.UInt32;
+ -- Description collection[n]: Reserved for Nordic firmware design
+ NRFFW : aliased NRFFW_Registers;
+ -- Description collection[n]: Reserved for Nordic hardware design
+ NRFHW : aliased NRFHW_Registers;
+ -- Description collection[n]: Reserved for customer
+ CUSTOMER : aliased CUSTOMER_Registers;
+ -- Description collection[n]: Mapping of the nRESET function
+ PSELRESET : aliased PSELRESET_Registers;
+ -- Access port protection
+ APPROTECT : aliased APPROTECT_Register;
+ -- Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
+ NFCPINS : aliased NFCPINS_Register;
+ -- Processor debug control
+ DEBUGCTRL : aliased DEBUGCTRL_Register;
+ -- GPIO reference voltage / external output supply voltage in high
+ -- voltage mode
+ REGOUT0 : aliased REGOUT0_Register;
+ end record
+ with Volatile;
+
+ for UICR_Peripheral use record
+ UNUSED0 at 16#0# range 0 .. 31;
+ UNUSED1 at 16#4# range 0 .. 31;
+ UNUSED2 at 16#8# range 0 .. 31;
+ UNUSED3 at 16#10# range 0 .. 31;
+ NRFFW at 16#14# range 0 .. 479;
+ NRFHW at 16#50# range 0 .. 383;
+ CUSTOMER at 16#80# range 0 .. 1023;
+ PSELRESET at 16#200# range 0 .. 63;
+ APPROTECT at 16#208# range 0 .. 31;
+ NFCPINS at 16#20C# range 0 .. 31;
+ DEBUGCTRL at 16#210# range 0 .. 31;
+ REGOUT0 at 16#304# range 0 .. 31;
+ end record;
+
+ -- User information configuration registers
+ UICR_Periph : aliased UICR_Peripheral
+ with Import, Address => UICR_Base;
+
+end Interfaces.NRF52.UICR;
diff --git a/arm/nordic/nrf52/nrf52840/svd/i-nrf52.ads b/arm/nordic/nrf52/nrf52840/svd/i-nrf52.ads
new file mode 100644
index 00000000..3fbd3471
--- /dev/null
+++ b/arm/nordic/nrf52/nrf52840/svd/i-nrf52.ads
@@ -0,0 +1,274 @@
+--
+-- Copyright (C) 2019, AdaCore
+--
+
+-- Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
+--
+-- All rights reserved.
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- 1. Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- 2. Redistributions in binary form, except as embedded into a Nordic
+-- Semiconductor ASA integrated circuit in a product or a software update
+-- for such product, must reproduce the above copyright notice, this list
+-- of conditions and the following disclaimer in the documentation and/or
+-- other materials provided with the distribution.
+--
+-- 3. Neither the name of Nordic Semiconductor ASA nor the names of its
+-- contributors may be used to endorse or promote products derived from
+-- this software without specific prior written permission.
+--
+-- 4. This software, with or without modification, must only be used with a
+-- Nordic Semiconductor ASA integrated circuit.
+--
+-- 5. Any software provided in binary form under this license must not be
+-- reverse engineered, decompiled, modified and/or disassembled.
+--
+-- THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+-- WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR
+-- ASA OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+-- TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+-- PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+-- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+
+-- This spec has been automatically generated from nrf52840.svd
+
+pragma Ada_2012;
+pragma Style_Checks (Off);
+
+with System;
+
+-- nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4
+-- Microcontroller
+package Interfaces.NRF52 is
+ pragma Preelaborate;
+ pragma No_Elaboration_Code_All;
+
+ ---------------
+ -- Base type --
+ ---------------
+
+ type UInt32 is new Interfaces.Unsigned_32;
+ type UInt16 is new Interfaces.Unsigned_16;
+ type Byte is new Interfaces.Unsigned_8;
+ type Bit is mod 2**1
+ with Size => 1;
+ type UInt2 is mod 2**2
+ with Size => 2;
+ type UInt3 is mod 2**3
+ with Size => 3;
+ type UInt4 is mod 2**4
+ with Size => 4;
+ type UInt5 is mod 2**5
+ with Size => 5;
+ type UInt6 is mod 2**6
+ with Size => 6;
+ type UInt7 is mod 2**7
+ with Size => 7;
+ type UInt9 is mod 2**9
+ with Size => 9;
+ type UInt10 is mod 2**10
+ with Size => 10;
+ type UInt11 is mod 2**11
+ with Size => 11;
+ type UInt12 is mod 2**12
+ with Size => 12;
+ type UInt13 is mod 2**13
+ with Size => 13;
+ type UInt14 is mod 2**14
+ with Size => 14;
+ type UInt15 is mod 2**15
+ with Size => 15;
+ type UInt17 is mod 2**17
+ with Size => 17;
+ type UInt18 is mod 2**18
+ with Size => 18;
+ type UInt19 is mod 2**19
+ with Size => 19;
+ type UInt20 is mod 2**20
+ with Size => 20;
+ type UInt21 is mod 2**21
+ with Size => 21;
+ type UInt22 is mod 2**22
+ with Size => 22;
+ type UInt23 is mod 2**23
+ with Size => 23;
+ type UInt24 is mod 2**24
+ with Size => 24;
+ type UInt25 is mod 2**25
+ with Size => 25;
+ type UInt26 is mod 2**26
+ with Size => 26;
+ type UInt27 is mod 2**27
+ with Size => 27;
+ type UInt28 is mod 2**28
+ with Size => 28;
+ type UInt29 is mod 2**29
+ with Size => 29;
+ type UInt30 is mod 2**30
+ with Size => 30;
+ type UInt31 is mod 2**31
+ with Size => 31;
+
+ --------------------
+ -- Base addresses --
+ --------------------
+
+ FICR_Base : constant System.Address :=
+ System'To_Address (16#10000000#);
+ UICR_Base : constant System.Address :=
+ System'To_Address (16#10001000#);
+ CLOCK_Base : constant System.Address :=
+ System'To_Address (16#40000000#);
+ POWER_Base : constant System.Address :=
+ System'To_Address (16#40000000#);
+ RADIO_Base : constant System.Address :=
+ System'To_Address (16#40001000#);
+ UART0_Base : constant System.Address :=
+ System'To_Address (16#40002000#);
+ UARTE0_Base : constant System.Address :=
+ System'To_Address (16#40002000#);
+ SPI0_Base : constant System.Address :=
+ System'To_Address (16#40003000#);
+ SPIM0_Base : constant System.Address :=
+ System'To_Address (16#40003000#);
+ SPIS0_Base : constant System.Address :=
+ System'To_Address (16#40003000#);
+ TWI0_Base : constant System.Address :=
+ System'To_Address (16#40003000#);
+ TWIM0_Base : constant System.Address :=
+ System'To_Address (16#40003000#);
+ TWIS0_Base : constant System.Address :=
+ System'To_Address (16#40003000#);
+ SPI1_Base : constant System.Address :=
+ System'To_Address (16#40004000#);
+ SPIM1_Base : constant System.Address :=
+ System'To_Address (16#40004000#);
+ SPIS1_Base : constant System.Address :=
+ System'To_Address (16#40004000#);
+ TWI1_Base : constant System.Address :=
+ System'To_Address (16#40004000#);
+ TWIM1_Base : constant System.Address :=
+ System'To_Address (16#40004000#);
+ TWIS1_Base : constant System.Address :=
+ System'To_Address (16#40004000#);
+ NFCT_Base : constant System.Address :=
+ System'To_Address (16#40005000#);
+ GPIOTE_Base : constant System.Address :=
+ System'To_Address (16#40006000#);
+ SAADC_Base : constant System.Address :=
+ System'To_Address (16#40007000#);
+ TIMER0_Base : constant System.Address :=
+ System'To_Address (16#40008000#);
+ TIMER1_Base : constant System.Address :=
+ System'To_Address (16#40009000#);
+ TIMER2_Base : constant System.Address :=
+ System'To_Address (16#4000A000#);
+ RTC0_Base : constant System.Address :=
+ System'To_Address (16#4000B000#);
+ TEMP_Base : constant System.Address :=
+ System'To_Address (16#4000C000#);
+ RNG_Base : constant System.Address :=
+ System'To_Address (16#4000D000#);
+ ECB_Base : constant System.Address :=
+ System'To_Address (16#4000E000#);
+ AAR_Base : constant System.Address :=
+ System'To_Address (16#4000F000#);
+ CCM_Base : constant System.Address :=
+ System'To_Address (16#4000F000#);
+ WDT_Base : constant System.Address :=
+ System'To_Address (16#40010000#);
+ RTC1_Base : constant System.Address :=
+ System'To_Address (16#40011000#);
+ QDEC_Base : constant System.Address :=
+ System'To_Address (16#40012000#);
+ COMP_Base : constant System.Address :=
+ System'To_Address (16#40013000#);
+ LPCOMP_Base : constant System.Address :=
+ System'To_Address (16#40013000#);
+ EGU0_Base : constant System.Address :=
+ System'To_Address (16#40014000#);
+ SWI0_Base : constant System.Address :=
+ System'To_Address (16#40014000#);
+ EGU1_Base : constant System.Address :=
+ System'To_Address (16#40015000#);
+ SWI1_Base : constant System.Address :=
+ System'To_Address (16#40015000#);
+ EGU2_Base : constant System.Address :=
+ System'To_Address (16#40016000#);
+ SWI2_Base : constant System.Address :=
+ System'To_Address (16#40016000#);
+ EGU3_Base : constant System.Address :=
+ System'To_Address (16#40017000#);
+ SWI3_Base : constant System.Address :=
+ System'To_Address (16#40017000#);
+ EGU4_Base : constant System.Address :=
+ System'To_Address (16#40018000#);
+ SWI4_Base : constant System.Address :=
+ System'To_Address (16#40018000#);
+ EGU5_Base : constant System.Address :=
+ System'To_Address (16#40019000#);
+ SWI5_Base : constant System.Address :=
+ System'To_Address (16#40019000#);
+ TIMER3_Base : constant System.Address :=
+ System'To_Address (16#4001A000#);
+ TIMER4_Base : constant System.Address :=
+ System'To_Address (16#4001B000#);
+ PWM0_Base : constant System.Address :=
+ System'To_Address (16#4001C000#);
+ PDM_Base : constant System.Address :=
+ System'To_Address (16#4001D000#);
+ ACL_Base : constant System.Address :=
+ System'To_Address (16#4001E000#);
+ NVMC_Base : constant System.Address :=
+ System'To_Address (16#4001E000#);
+ PPI_Base : constant System.Address :=
+ System'To_Address (16#4001F000#);
+ MWU_Base : constant System.Address :=
+ System'To_Address (16#40020000#);
+ PWM1_Base : constant System.Address :=
+ System'To_Address (16#40021000#);
+ PWM2_Base : constant System.Address :=
+ System'To_Address (16#40022000#);
+ SPI2_Base : constant System.Address :=
+ System'To_Address (16#40023000#);
+ SPIM2_Base : constant System.Address :=
+ System'To_Address (16#40023000#);
+ SPIS2_Base : constant System.Address :=
+ System'To_Address (16#40023000#);
+ RTC2_Base : constant System.Address :=
+ System'To_Address (16#40024000#);
+ I2S_Base : constant System.Address :=
+ System'To_Address (16#40025000#);
+ FPU_Base : constant System.Address :=
+ System'To_Address (16#40026000#);
+ USBD_Base : constant System.Address :=
+ System'To_Address (16#40027000#);
+ UARTE1_Base : constant System.Address :=
+ System'To_Address (16#40028000#);
+ QSPI_Base : constant System.Address :=
+ System'To_Address (16#40029000#);
+ PWM3_Base : constant System.Address :=
+ System'To_Address (16#4002D000#);
+ SPIM3_Base : constant System.Address :=
+ System'To_Address (16#4002F000#);
+ P0_Base : constant System.Address :=
+ System'To_Address (16#50000000#);
+ P1_Base : constant System.Address :=
+ System'To_Address (16#50000300#);
+ CC_HOST_RGF_Base : constant System.Address :=
+ System'To_Address (16#5002A000#);
+ CRYPTOCELL_Base : constant System.Address :=
+ System'To_Address (16#5002A000#);
+
+end Interfaces.NRF52;
diff --git a/arm/nordic/nrf52/s-bbmcpa.ads b/arm/nordic/nrf52/s-bbmcpa.ads
new file mode 100644
index 00000000..710f7023
--- /dev/null
+++ b/arm/nordic/nrf52/s-bbmcpa.ads
@@ -0,0 +1,43 @@
+------------------------------------------------------------------------------
+-- --
+-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS --
+-- --
+-- S Y S T E M . B B . M C U _ P A R A M E T E R S --
+-- --
+-- S p e c --
+-- --
+-- Copyright (C) 2019, AdaCore --
+-- --
+-- GNAT is free software; you can redistribute it and/or modify it under --
+-- terms of the GNU General Public License as published by the Free Soft- --
+-- ware Foundation; either version 3, or (at your option) any later ver- --
+-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
+-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
+-- or FITNESS FOR A PARTICULAR PURPOSE. --
+-- --
+-- As a special exception under Section 7 of GPL version 3, you are granted --
+-- additional permissions described in the GCC Runtime Library Exception, --
+-- version 3.1, as published by the Free Software Foundation. --
+-- --
+-- You should have received a copy of the GNU General Public License and --
+-- a copy of the GCC Runtime Library Exception along with this program; --
+-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
+-- . --
+-- --
+-- GNAT was originally developed by the GNAT team at New York University. --
+-- Extensive contributions were provided by Ada Core Technologies Inc. --
+-- --
+-- The port of GNARL to bare board targets was initially developed by the --
+-- Real-Time Systems Group at the Technical University of Madrid. --
+-- --
+------------------------------------------------------------------------------
+
+-- This package defines MCU parameters for the nRF52840
+
+package System.BB.MCU_Parameters is
+ pragma No_Elaboration_Code_All;
+ pragma Preelaborate;
+
+ Number_Of_Interrupts : constant := 47;
+
+end System.BB.MCU_Parameters;
diff --git a/arm/nordic/nrf52/setup_board.ads b/arm/nordic/nrf52/setup_board.ads
new file mode 100644
index 00000000..1387e99e
--- /dev/null
+++ b/arm/nordic/nrf52/setup_board.ads
@@ -0,0 +1,34 @@
+------------------------------------------------------------------------------
+-- --
+-- GNAT RUN-TIME COMPONENTS --
+-- --
+-- Copyright (C) 2012-2019, Free Software Foundation, Inc. --
+-- --
+-- GNAT is free software; you can redistribute it and/or modify it under --
+-- terms of the GNU General Public License as published by the Free Soft- --
+-- ware Foundation; either version 3, or (at your option) any later ver- --
+-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
+-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
+-- or FITNESS FOR A PARTICULAR PURPOSE. --
+-- --
+-- As a special exception under Section 7 of GPL version 3, you are granted --
+-- additional permissions described in the GCC Runtime Library Exception, --
+-- version 3.1, as published by the Free Software Foundation. --
+-- --
+-- You should have received a copy of the GNU General Public License and --
+-- a copy of the GCC Runtime Library Exception along with this program; --
+-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
+-- . --
+-- --
+-- GNAT was originally developed by the GNAT team at New York University. --
+-- Extensive contributions were provided by Ada Core Technologies Inc. --
+-- --
+------------------------------------------------------------------------------
+
+pragma Suppress (All_Checks);
+
+procedure Setup_Board;
+
+pragma No_Elaboration_Code_All (Setup_Board);
+-- This code is executed before elaboration, so better not need elaboration
+-- code.
diff --git a/arm/nordic/nrf52/start-common.S b/arm/nordic/nrf52/start-common.S
new file mode 100644
index 00000000..5dcb64f0
--- /dev/null
+++ b/arm/nordic/nrf52/start-common.S
@@ -0,0 +1,68 @@
+## -*- asm -*- ##############################################################
+# #
+# GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS #
+# #
+# C A C H E #
+# #
+# Assembly File #
+# #
+# Copyright (C) 2012-2019 AdaCore #
+# #
+# GNAT is free software; you can redistribute it and/or modify it under #
+# terms of the GNU General Public License as published by the Free Soft- #
+# ware Foundation; either version 3, or (at your option) any later ver- #
+# sion. GNAT is distributed in the hope that it will be useful, but WITH- #
+# OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY #
+# or FITNESS FOR A PARTICULAR PURPOSE. #
+# #
+# As a special exception under Section 7 of GPL version 3, you are granted #
+# additional permissions described in the GCC Runtime Library Exception, #
+# version 3.1, as published by the Free Software Foundation. #
+# #
+# You should have received a copy of the GNU General Public License and #
+# a copy of the GCC Runtime Library Exception along with this program; #
+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #
+# . #
+# #
+#############################################################################
+
+ .syntax unified
+ .cpu cortex-m4
+ .thumb
+
+ .text
+ .thumb_func
+ .globl _nrf5_start_common
+_nrf5_start_common:
+ .type _nrf5_start_common, #function
+
+ /************************
+ * Enable debug Monitor *
+ ************************/
+
+ /* Debug register definition */
+ .set DEMCR, 0xE000EDFC
+
+ /* Enable the debug monitor so that bkpt instructions are not treated
+ * as hard fault when no debugger is attached */
+ ldr r0, =DEMCR
+ ldr r1, [r0]
+ orr r1, r1, #0x10000 /* Set MON_EN in DEMCR */
+ str r1, [r0]
+
+ /**************/
+ /* Enable FPU */
+ /**************/
+
+ movw r0,#0xED88
+ movt r0,#0xE000
+ ldr r1,[r0]
+ orr r1,r1,#(0xF << 20)
+ str r1,[r0]
+
+ dsb
+ isb
+
+end:
+ bx lr
+ .size _nrf5_start_common, . - _nrf5_start_common
diff --git a/arm/nordic/nrf52/start-rom.S b/arm/nordic/nrf52/start-rom.S
new file mode 100644
index 00000000..ed21f7db
--- /dev/null
+++ b/arm/nordic/nrf52/start-rom.S
@@ -0,0 +1,80 @@
+## -*- asm -*- ##############################################################
+# #
+# GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS #
+# #
+# S T A R T #
+# #
+# Assembly File #
+# #
+# Copyright (C) 2012-2019 AdaCore #
+# #
+# GNAT is free software; you can redistribute it and/or modify it under #
+# terms of the GNU General Public License as published by the Free Soft- #
+# ware Foundation; either version 3, or (at your option) any later ver- #
+# sion. GNAT is distributed in the hope that it will be useful, but WITH- #
+# OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY #
+# or FITNESS FOR A PARTICULAR PURPOSE. #
+# #
+# As a special exception under Section 7 of GPL version 3, you are granted #
+# additional permissions described in the GCC Runtime Library Exception, #
+# version 3.1, as published by the Free Software Foundation. #
+# #
+# You should have received a copy of the GNU General Public License and #
+# a copy of the GCC Runtime Library Exception along with this program; #
+# see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #
+# . #
+# #
+#############################################################################
+
+ .syntax unified
+ .cpu cortex-m4
+ .thumb
+
+ /* This is the initial vector table and also the one that is used by
+ the zfp runtime. Ravenscar runtimes install its own table (using
+ VTOR register) defined in handler.S. */
+ .section .vectors,"a"
+__vectors0:
+ .word __stack_end /* stack top address */
+ .word _start_rom /* 1 Reset */
+ .word hang /* 2 NMI */
+ .word hang /* 3 HardFault */
+ .word hang /* 4 MemManage */
+
+ .text
+
+ .thumb_func
+ .globl _start_rom
+_start_rom:
+ /* Enable FPU and cache when appropriate */
+ bl _nrf5_start_common
+
+ /* Copy .data */
+ movw r0,#:lower16:__data_start
+ movt r0,#:upper16:__data_start
+ movw r1,#:lower16:__data_words
+ movw r2,#:lower16:__data_load
+ movt r2,#:upper16:__data_load
+ cbz r1,1f
+0: ldr r4,[r2],#4
+ str r4,[r0],#4
+ subs r1,r1,#1
+ bne 0b
+1:
+ /* Clear .bss */
+ movw r0,#:lower16:__bss_start
+ movt r0,#:upper16:__bss_start
+ movw r1,#:lower16:__bss_words
+ mov r2,#0
+ cbz r1,1f
+0: str r2,[r0],#4
+ subs r1,r1,#1
+ bne 0b
+
+1:
+ bl _ada_setup_board
+ bl main
+
+ bl _exit
+
+hang: b .
diff --git a/arm/nordic/nrf52/system-xi-nrf52-full.ads b/arm/nordic/nrf52/system-xi-nrf52-full.ads
new file mode 100644
index 00000000..d8b6e14a
--- /dev/null
+++ b/arm/nordic/nrf52/system-xi-nrf52-full.ads
@@ -0,0 +1,164 @@
+------------------------------------------------------------------------------
+-- --
+-- GNAT RUN-TIME COMPONENTS --
+-- --
+-- S Y S T E M --
+-- --
+-- S p e c --
+-- (ARM Cortex M4 Version) --
+-- --
+-- Copyright (C) 2015-2019, Free Software Foundation, Inc. --
+-- --
+-- This specification is derived from the Ada Reference Manual for use with --
+-- GNAT. The copyright notice above, and the license provisions that follow --
+-- apply solely to the contents of the part following the private keyword. --
+-- --
+-- GNAT is free software; you can redistribute it and/or modify it under --
+-- terms of the GNU General Public License as published by the Free Soft- --
+-- ware Foundation; either version 3, or (at your option) any later ver- --
+-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
+-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
+-- or FITNESS FOR A PARTICULAR PURPOSE. --
+-- --
+-- As a special exception under Section 7 of GPL version 3, you are granted --
+-- additional permissions described in the GCC Runtime Library Exception, --
+-- version 3.1, as published by the Free Software Foundation. --
+-- --
+-- You should have received a copy of the GNU General Public License and --
+-- a copy of the GCC Runtime Library Exception along with this program; --
+-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
+-- . --
+-- --
+-- GNAT was originally developed by the GNAT team at New York University. --
+-- Extensive contributions were provided by Ada Core Technologies Inc. --
+-- --
+------------------------------------------------------------------------------
+
+pragma Restrictions (No_Exception_Registration);
+-- Disable exception name registration. This capability is not used because
+-- it is only required by exception stream attributes which are not supported
+-- in this run time.
+
+pragma Profile (GNAT_Extended_Ravenscar);
+-- This is a Ravenscar run time
+
+pragma Restrictions (No_Task_At_Interrupt_Priority);
+-- On Cortex-M, it is not possible to have tasks at Interrupt_Priority, as
+-- the context switch is triggered by the Pend_SV interrupt, which is at
+-- lowest priority.
+
+package System is
+ pragma Pure;
+ -- Note that we take advantage of the implementation permission to make
+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada
+ -- 2005, this is Pure in any case (AI-362).
+
+ pragma No_Elaboration_Code_All;
+ -- Allow the use of that restriction in units that WITH this unit
+
+ type Name is (SYSTEM_NAME_GNAT);
+ System_Name : constant Name := SYSTEM_NAME_GNAT;
+
+ -- System-Dependent Named Numbers
+
+ Min_Int : constant := Long_Long_Integer'First;
+ Max_Int : constant := Long_Long_Integer'Last;
+
+ Max_Binary_Modulus : constant := 2 ** Long_Long_Integer'Size;
+ Max_Nonbinary_Modulus : constant := 2 ** Integer'Size - 1;
+
+ Max_Base_Digits : constant := Long_Long_Float'Digits;
+ Max_Digits : constant := Long_Long_Float'Digits;
+
+ Max_Mantissa : constant := 63;
+ Fine_Delta : constant := 2.0 ** (-Max_Mantissa);
+
+ Tick : constant := 0.000_001;
+
+ -- Storage-related Declarations
+
+ type Address is private;
+ pragma Preelaborable_Initialization (Address);
+ Null_Address : constant Address;
+
+ Storage_Unit : constant := 8;
+ Word_Size : constant := 32;
+ Memory_Size : constant := 2 ** 32;
+
+ -- Address comparison
+
+ function "<" (Left, Right : Address) return Boolean;
+ function "<=" (Left, Right : Address) return Boolean;
+ function ">" (Left, Right : Address) return Boolean;
+ function ">=" (Left, Right : Address) return Boolean;
+ function "=" (Left, Right : Address) return Boolean;
+
+ pragma Import (Intrinsic, "<");
+ pragma Import (Intrinsic, "<=");
+ pragma Import (Intrinsic, ">");
+ pragma Import (Intrinsic, ">=");
+ pragma Import (Intrinsic, "=");
+
+ -- Other System-Dependent Declarations
+
+ type Bit_Order is (High_Order_First, Low_Order_First);
+ Default_Bit_Order : constant Bit_Order :=
+ Bit_Order'Val (Standard'Default_Bit_Order);
+ pragma Warnings (Off, Default_Bit_Order); -- kill constant condition warning
+
+ -- Priority-related Declarations (RM D.1)
+
+ -- 249 .. 255 corresponds to priority level 7 .. 1
+
+ Max_Interrupt_Priority : constant Positive := 255;
+ Max_Priority : constant Positive := 248;
+
+ subtype Any_Priority is Integer range 0 .. 255;
+ subtype Priority is Any_Priority range 0 .. 248;
+ subtype Interrupt_Priority is Any_Priority range 249 .. 255;
+
+ Default_Priority : constant Priority := 120;
+
+private
+
+ type Address is mod Memory_Size;
+ Null_Address : constant Address := 0;
+
+ --------------------------------------
+ -- System Implementation Parameters --
+ --------------------------------------
+
+ -- These parameters provide information about the target that is used by
+ -- the compiler. They are in the private part of System, where they can be
+ -- accessed using the special circuitry in the Targparm unit whose source
+ -- should be consulted for more detailed descriptions of the individual
+ -- switch values.
+
+ Atomic_Sync_Default : constant Boolean := False;
+ Backend_Divide_Checks : constant Boolean := False;
+ Backend_Overflow_Checks : constant Boolean := True;
+ Command_Line_Args : constant Boolean := False;
+ Configurable_Run_Time : constant Boolean := True;
+ Denorm : constant Boolean := True;
+ Duration_32_Bits : constant Boolean := False;
+ Exit_Status_Supported : constant Boolean := False;
+ Fractional_Fixed_Ops : constant Boolean := False;
+ Frontend_Layout : constant Boolean := False;
+ Machine_Overflows : constant Boolean := False;
+ Machine_Rounds : constant Boolean := True;
+ Preallocated_Stacks : constant Boolean := True;
+ Signed_Zeros : constant Boolean := True;
+ Stack_Check_Default : constant Boolean := False;
+ Stack_Check_Probes : constant Boolean := False;
+ Stack_Check_Limits : constant Boolean := False;
+ Support_Aggregates : constant Boolean := True;
+ Support_Composite_Assign : constant Boolean := True;
+ Support_Composite_Compare : constant Boolean := True;
+ Support_Long_Shifts : constant Boolean := True;
+ Always_Compatible_Rep : constant Boolean := True;
+ Suppress_Standard_Library : constant Boolean := False;
+ Use_Ada_Main_Program_Name : constant Boolean := False;
+ Frontend_Exceptions : constant Boolean := False;
+ ZCX_By_Default : constant Boolean := True;
+
+end System;
diff --git a/arm/nordic/nrf52/system-xi-nrf52-sfp.ads b/arm/nordic/nrf52/system-xi-nrf52-sfp.ads
new file mode 100644
index 00000000..db532dcc
--- /dev/null
+++ b/arm/nordic/nrf52/system-xi-nrf52-sfp.ads
@@ -0,0 +1,174 @@
+------------------------------------------------------------------------------
+-- --
+-- GNAT RUN-TIME COMPONENTS --
+-- --
+-- S Y S T E M --
+-- --
+-- S p e c --
+-- (ARM Cortex M4 Version) --
+-- --
+-- Copyright (C) 1992-2019, Free Software Foundation, Inc. --
+-- --
+-- This specification is derived from the Ada Reference Manual for use with --
+-- GNAT. The copyright notice above, and the license provisions that follow --
+-- apply solely to the contents of the part following the private keyword. --
+-- --
+-- GNAT is free software; you can redistribute it and/or modify it under --
+-- terms of the GNU General Public License as published by the Free Soft- --
+-- ware Foundation; either version 3, or (at your option) any later ver- --
+-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
+-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
+-- or FITNESS FOR A PARTICULAR PURPOSE. --
+-- --
+-- As a special exception under Section 7 of GPL version 3, you are granted --
+-- additional permissions described in the GCC Runtime Library Exception, --
+-- version 3.1, as published by the Free Software Foundation. --
+-- --
+-- You should have received a copy of the GNU General Public License and --
+-- a copy of the GCC Runtime Library Exception along with this program; --
+-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
+-- . --
+-- --
+-- GNAT was originally developed by the GNAT team at New York University. --
+-- Extensive contributions were provided by Ada Core Technologies Inc. --
+-- --
+------------------------------------------------------------------------------
+
+pragma Restrictions (No_Exception_Propagation);
+-- Only local exception handling is supported in this profile
+
+pragma Restrictions (No_Exception_Registration);
+-- Disable exception name registration. This capability is not used because
+-- it is only required by exception stream attributes which are not supported
+-- in this run time.
+
+pragma Restrictions (No_Implicit_Dynamic_Code);
+-- Pointers to nested subprograms are not allowed in this run time, in order
+-- to prevent the compiler from building "trampolines".
+
+pragma Restrictions (No_Finalization);
+-- Controlled types are not supported in this run time
+
+pragma Profile (Ravenscar);
+-- This is a Ravenscar run time
+
+pragma Restrictions (No_Task_At_Interrupt_Priority);
+-- On Cortex-M, it is not possible to have tasks at Interrupt_Priority, as
+-- the context switch is triggered by the Pend_SV interrupt, which is at
+-- lowest priority.
+
+package System is
+ pragma Pure;
+ -- Note that we take advantage of the implementation permission to make
+ -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada
+ -- 2005, this is Pure in any case (AI-362).
+
+ pragma No_Elaboration_Code_All;
+ -- Allow the use of that restriction in units that WITH this unit
+
+ type Name is (SYSTEM_NAME_GNAT);
+ System_Name : constant Name := SYSTEM_NAME_GNAT;
+
+ -- System-Dependent Named Numbers
+
+ Min_Int : constant := Long_Long_Integer'First;
+ Max_Int : constant := Long_Long_Integer'Last;
+
+ Max_Binary_Modulus : constant := 2 ** Long_Long_Integer'Size;
+ Max_Nonbinary_Modulus : constant := 2 ** Integer'Size - 1;
+
+ Max_Base_Digits : constant := Long_Long_Float'Digits;
+ Max_Digits : constant := Long_Long_Float'Digits;
+
+ Max_Mantissa : constant := 63;
+ Fine_Delta : constant := 2.0 ** (-Max_Mantissa);
+
+ Tick : constant := 0.000_001;
+
+ -- Storage-related Declarations
+
+ type Address is private;
+ pragma Preelaborable_Initialization (Address);
+ Null_Address : constant Address;
+
+ Storage_Unit : constant := 8;
+ Word_Size : constant := 32;
+ Memory_Size : constant := 2 ** 32;
+
+ -- Address comparison
+
+ function "<" (Left, Right : Address) return Boolean;
+ function "<=" (Left, Right : Address) return Boolean;
+ function ">" (Left, Right : Address) return Boolean;
+ function ">=" (Left, Right : Address) return Boolean;
+ function "=" (Left, Right : Address) return Boolean;
+
+ pragma Import (Intrinsic, "<");
+ pragma Import (Intrinsic, "<=");
+ pragma Import (Intrinsic, ">");
+ pragma Import (Intrinsic, ">=");
+ pragma Import (Intrinsic, "=");
+
+ -- Other System-Dependent Declarations
+
+ type Bit_Order is (High_Order_First, Low_Order_First);
+ Default_Bit_Order : constant Bit_Order :=
+ Bit_Order'Val (Standard'Default_Bit_Order);
+ pragma Warnings (Off, Default_Bit_Order); -- kill constant condition warning
+
+ -- Priority-related Declarations (RM D.1)
+
+ -- 249 .. 255 corresponds to priority level 7 .. 1
+
+ Max_Interrupt_Priority : constant Positive := 255;
+ Max_Priority : constant Positive := 248;
+
+ subtype Any_Priority is Integer range 0 .. 255;
+ subtype Priority is Any_Priority range 0 .. 248;
+ subtype Interrupt_Priority is Any_Priority range 249 .. 255;
+
+ Default_Priority : constant Priority := 120;
+
+private
+
+ type Address is mod Memory_Size;
+ Null_Address : constant Address := 0;
+
+ --------------------------------------
+ -- System Implementation Parameters --
+ --------------------------------------
+
+ -- These parameters provide information about the target that is used by
+ -- the compiler. They are in the private part of System, where they can be
+ -- accessed using the special circuitry in the Targparm unit whose source
+ -- should be consulted for more detailed descriptions of the individual
+ -- switch values.
+
+ Atomic_Sync_Default : constant Boolean := False;
+ Backend_Divide_Checks : constant Boolean := False;
+ Backend_Overflow_Checks : constant Boolean := True;
+ Command_Line_Args : constant Boolean := False;
+ Configurable_Run_Time : constant Boolean := True;
+ Denorm : constant Boolean := True;
+ Duration_32_Bits : constant Boolean := False;
+ Exit_Status_Supported : constant Boolean := False;
+ Fractional_Fixed_Ops : constant Boolean := False;
+ Frontend_Layout : constant Boolean := False;
+ Machine_Overflows : constant Boolean := False;
+ Machine_Rounds : constant Boolean := True;
+ Preallocated_Stacks : constant Boolean := True;
+ Signed_Zeros : constant Boolean := True;
+ Stack_Check_Default : constant Boolean := False;
+ Stack_Check_Probes : constant Boolean := False;
+ Stack_Check_Limits : constant Boolean := False;
+ Support_Aggregates : constant Boolean := True;
+ Support_Composite_Assign : constant Boolean := True;
+ Support_Composite_Compare : constant Boolean := True;
+ Support_Long_Shifts : constant Boolean := True;
+ Always_Compatible_Rep : constant Boolean := True;
+ Suppress_Standard_Library : constant Boolean := True;
+ Use_Ada_Main_Program_Name : constant Boolean := False;
+ Frontend_Exceptions : constant Boolean := False;
+ ZCX_By_Default : constant Boolean := True;
+
+end System;
diff --git a/arm/nordic/svd.mk b/arm/nordic/svd.mk
index e3d65bf3..fabfe286 100644
--- a/arm/nordic/svd.mk
+++ b/arm/nordic/svd.mk
@@ -4,7 +4,9 @@ SVD2ADA_DIR=$(shell dirname $(shell which svd2ada))
all: svd
-svd:
+svd: svd-nrf51 svd-nrf52
+
+svd-nrf51:
rm -rf */svd */svdtmp
$(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/Nordic/nrf51.svd -p Interfaces.NRF51 -o nrf51/svdtmp --boolean
for d in */svdtmp; do \
@@ -19,3 +21,44 @@ svd:
cd ../..; \
done
rm -rf */svdtmp
+
+svd-nrf52:
+ rm -rf nrf52/nrf52832/svd nrf52/nrf52832/svdtmp
+ $(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/Nordic/nrf52.svd -p Interfaces.NRF52 -o nrf52/nrf52832/svdtmp
+ cd nrf52/nrf52832/svdtmp && \
+ echo $(CURDIR) && \
+ mkdir ../svd && \
+ mv i-nrf52.ads ../svd && \
+ mv i-nrf52-clock.ads ../svd && \
+ mv i-nrf52-ficr.ads ../svd && \
+ mv i-nrf52-gpio.ads ../svd && \
+ mv i-nrf52-nvmc.ads ../svd && \
+ mv i-nrf52-rtc.ads ../svd && \
+ mv i-nrf52-temp.ads ../svd && \
+ mv i-nrf52-uart.ads ../svd && \
+ mv i-nrf52-uicr.ads ../svd && \
+ mv a-intnam.ads ../svd && \
+ mv handler.S ../svd && \
+ cd ../../..
+ rm -rf nrf52/nrf52832/svdtmp
+
+svd-nrf52840:
+ rm -rf nrf52/nrf52840/svd nrf52/nrf52840/svdtmp
+ $(SVD2ADA_DIR)/svd2ada $(SVD2ADA_DIR)/CMSIS-SVD/Nordic/nrf52840.svd -p Interfaces.NRF52 -o nrf52/nrf52840/svdtmp
+ cd nrf52/nrf52840/svdtmp && \
+ echo $(CURDIR) && \
+ mkdir ../svd && \
+ mv i-nrf52.ads ../svd && \
+ mv i-nrf52-ccm.ads ../svd && \
+ mv i-nrf52-clock.ads ../svd && \
+ mv i-nrf52-ficr.ads ../svd && \
+ mv i-nrf52-gpio.ads ../svd && \
+ mv i-nrf52-nvmc.ads ../svd && \
+ mv i-nrf52-rtc.ads ../svd && \
+ mv i-nrf52-temp.ads ../svd && \
+ mv i-nrf52-uart.ads ../svd && \
+ mv i-nrf52-uicr.ads ../svd && \
+ mv a-intnam.ads ../svd && \
+ mv handler.S ../svd && \
+ cd ../../..
+ rm -rf nrf52/nrf52840/svdtmp
diff --git a/build_rts.py b/build_rts.py
index 240d918b..1efa7b80 100755
--- a/build_rts.py
+++ b/build_rts.py
@@ -18,6 +18,7 @@
# Cortex-M runtimes
from arm.cortexm import Stm32, Sam, SmartFusion2, LM3S, M1AGL, Microbit, \
+ NRF52840, NRF52832, \
CortexM0, CortexM0P, CortexM1, CortexM3, CortexM4, CortexM4F, \
CortexM7F, CortexM7DF
@@ -89,6 +90,10 @@ def build_configs(target):
t = M1AGL()
elif target == 'microbit':
t = Microbit()
+ elif target == 'nrf52840':
+ t = NRF52840()
+ elif target == 'nrf52832':
+ t = NRF52832()
elif target == 'cortex-m0':
t = CortexM0()
elif target == 'cortex-m0p':
diff --git a/src/s-bbbosu__nrf52.adb b/src/s-bbbosu__nrf52.adb
new file mode 100644
index 00000000..cdb7e556
--- /dev/null
+++ b/src/s-bbbosu__nrf52.adb
@@ -0,0 +1,460 @@
+------------------------------------------------------------------------------
+-- --
+-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS --
+-- --
+-- S Y S T E M . B B . B O A R D _ S U P P O R T --
+-- --
+-- B o d y --
+-- --
+-- Copyright (C) 1999-2002 Universidad Politecnica de Madrid --
+-- Copyright (C) 2003-2005 The European Space Agency --
+-- Copyright (C) 2003-2019, AdaCore --
+-- --
+-- GNAT is free software; you can redistribute it and/or modify it under --
+-- terms of the GNU General Public License as published by the Free Soft- --
+-- ware Foundation; either version 3, or (at your option) any later ver- --
+-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
+-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
+-- or FITNESS FOR A PARTICULAR PURPOSE. --
+-- --
+-- As a special exception under Section 7 of GPL version 3, you are granted --
+-- additional permissions described in the GCC Runtime Library Exception, --
+-- version 3.1, as published by the Free Software Foundation. --
+-- --
+-- You should have received a copy of the GNU General Public License and --
+-- a copy of the GCC Runtime Library Exception along with this program; --
+-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
+-- . --
+-- --
+-- GNAT was originally developed by the GNAT team at New York University. --
+-- Extensive contributions were provided by Ada Core Technologies Inc. --
+-- --
+-- The port of GNARL to bare board targets was initially developed by the --
+-- Real-Time Systems Group at the Technical University of Madrid. --
+-- --
+------------------------------------------------------------------------------
+
+with System.Machine_Code;
+
+with System.BB.CPU_Primitives;
+with System.BB.Board_Parameters;
+
+with Interfaces.NRF52; use Interfaces.NRF52;
+with Interfaces.NRF52.RTC; use Interfaces.NRF52.RTC;
+with Interfaces.NRF52.CLOCK; use Interfaces.NRF52.CLOCK;
+
+package body System.BB.Board_Support is
+ use CPU_Primitives, BB.Interrupts, Machine_Code, Time;
+
+ package BBOPA renames System.BB.Board_Parameters;
+
+ Interrupt_Request_Vector : constant Vector_Id := 16;
+ -- See vector definitions in ARMv7-M version of System.BB.CPU_Primitives.
+ -- Defined by ARMv7-M specifications.
+
+ Alarm_Time : Time.Timer_Interval;
+ pragma Volatile (Alarm_Time);
+ pragma Export (C, Alarm_Time, "__gnat_alarm_time");
+
+ Alarm_Interrupt_ID : constant Interrupt_ID := 11; -- RTC0 IRQ
+
+ -------------------
+ -- RTC0 Handling --
+ -------------------
+
+ -- RTC0 is used as the clock source, which we use to implement
+ -- "tick-less" alarm handling.
+ --
+ -- The RTC is a 24-bit timer running at 32.768 kHz, resulting in a period
+ -- of 512 seconds (2**24 / 32_768).
+ --
+ -- We use the COMPARE feature of the RTC to provide accurate alarms.
+ -- We achieve this by updating CC[0] each time Set_Alarm is called so
+ -- that the alarm is triggered exactly at the alarm time. This results in
+ -- an alarm accuracy of 30.518 µs.
+ --
+ -- Note that the underlying 24-bit RTC runs at a frequency of 32.768 kHz,
+ -- but Timer_Interval is scaled up that, at 65.536 kHz ticks (or higher,
+ -- depending on RTC_Tick_Scaling_Factor) to ensure that
+ -- Ada.Real_Time.Time_Unit meets the requirements in Ada RM D.8/30
+
+ ----------------------------------------------
+ -- New Vectored Interrupt Controller (NVIC) --
+ ----------------------------------------------
+
+ NVIC_Base : constant := 16#E000_E000#;
+ -- Nested Vectored Interrupt Controller (NVIC) base.
+
+ NVIC_ISER0 : constant Address := NVIC_Base + 16#100#;
+ -- Writing a bit mask to this register enables the corresponding interrupts
+
+ NVIC_STIR : Word with Volatile, Address => NVIC_Base + 16#F00#;
+ -- Software Trigger Interrupt Register
+
+ type PRI is mod 2**8;
+ -- Type for ARMv7-M interrupt priorities. Note that 0 is the highest
+ -- priority, which is reserved for the kernel and has no corresponding
+ -- Interrupt_Priority value, and 255 is the lowest. We assume the PRIGROUP
+ -- setting is such that the 3 most significant bits determine the priority
+ -- group used for preemption.
+
+ function To_PRI (P : Integer) return PRI is
+ (if P not in Interrupt_Priority then 0
+ else PRI (Interrupt_Priority'Last - P + 1) * 32);
+ -- Return the BASEPRI mask for the given Ada priority. Note that the zero
+ -- value here means no mask, so no interrupts are masked.
+
+ function To_Priority (P : PRI) return Interrupt_Priority is
+ (if P = 0 then Interrupt_Priority'Last
+ else (Interrupt_Priority'Last - Any_Priority'Base (P / 32) + 1));
+ -- Given an ARM interrupt priority (PRI value), determine the Ada priority
+ -- While the value 0 is reserved for the kernel and has no Ada priority
+ -- that represents it, Interrupt_Priority'Last is closest.
+
+ IP : array (0 .. Interrupt_ID'Last) of PRI
+ with Volatile, Address => 16#E000_E400#;
+
+ -- Local utility functions
+
+ procedure Enable_Interrupt_Request
+ (Interrupt : Interrupt_ID;
+ Prio : Interrupt_Priority);
+ -- Enable interrupt requests for the given interrupt
+
+ procedure Trigger_Interrupt (Interrupt : Interrupt_ID);
+ -- Trigger an interrupt in the NVIC.
+
+ procedure Interrupt_Handler;
+ -- Low-level interrupt handlers
+
+ ----------------------
+ -- Initialize_Board --
+ ----------------------
+
+ procedure Initialize_Board is
+ begin
+ -- Mask interrupts
+ Disable_Interrupts;
+
+ -- Timer --
+
+ -- The 32.768 kHz RTC0 peripheral is used as the clock source on this
+ -- board. This is used instead of the SysTick timer because the "wfi"
+ -- instruction (used for entering the CPU sleep mode to save power)
+ -- powers down the entire CPU, *including* the SysTick.
+ -- Since we still want to use "wfi" to save power whilst keeping task
+ -- delays alive, we instead use the RTC0 peripheral.
+
+ -- Start LFCLK
+ -- We assume that the LFCLK source (Xtal, Rc, or Synth) has already been
+ -- configured in setup_clocks.adb
+ CLOCK_Periph.TASKS_LFCLKSTART := (TASKS_LFCLKSTART => 1, others => <>);
+
+ -- Wait for LFCLK to start-up.
+ loop
+ exit when CLOCK_Periph.EVENTS_LFCLKSTARTED.EVENTS_LFCLKSTARTED /= 0;
+ end loop;
+
+ -- Clear event
+ CLOCK_Periph.EVENTS_LFCLKSTARTED := (EVENTS_LFCLKSTARTED => 0,
+ others => <>);
+
+ -- Ensure RTC is stopped.
+ RTC0_Periph.TASKS_STOP := (TASKS_STOP => 1, others => <>);
+
+ -- Set to 0 before setting TASKS_CLEAR to prevent triggering a COMPARE
+ -- event.
+ RTC0_Periph.CC (0).COMPARE := 0;
+
+ -- Clear RTC
+ RTC0_Periph.TASKS_CLEAR := (TASKS_CLEAR => 1, others => <>);
+
+ -- Run at 32.768 kHz
+ RTC0_Periph.PRESCALER.PRESCALER := 0;
+
+ -- Enable CC[0] interrupt only; TICK and OVRFLW aren't needed.
+ RTC0_Periph.INTENSET.TICK := Intenset_Tick_Field_Reset;
+ RTC0_Periph.INTENSET.OVRFLW := Intenset_Ovrflw_Field_Reset;
+ RTC0_Periph.INTENSET.COMPARE := (As_Array => False, -- Use COMPARE0
+ Val => 2#0001#);
+
+ Time.Set_Alarm (Max_Timer_Interval);
+ Time.Clear_Alarm_Interrupt;
+
+ -- We do not start the timer until the handler is ready to receive the
+ -- interrupt, i.e. in Install_Alarm_Handler.
+
+ -- Interrupts --
+
+ Install_Trap_Handler
+ (Interrupt_Handler'Address, Interrupt_Request_Vector);
+ end Initialize_Board;
+
+ package body Time is
+
+ ------------------------
+ -- Max_Timer_Interval --
+ ------------------------
+
+ function Max_Timer_Interval return Timer_Interval
+ is ((2**24 - 1) * BBOPA.RTC_Tick_Scaling_Factor);
+ -- nRF52840 RTC is a 24-bit timer @ 32.768 kHz.
+ -- Since Timer_Interval is in a scaled up unit (e.g. 65.536 kHz ticks)
+ -- we need to also scaled up the 24-bit resolution.
+
+ ----------------
+ -- Read_Clock --
+ ----------------
+
+ function Read_Clock return BB.Time.Time is
+ PRIMASK : Word;
+ Res : Timer_Interval;
+
+ begin
+ -- As several registers and variables need to be read or modified, do
+ -- it atomically.
+
+ Asm ("mrs %0, PRIMASK",
+ Outputs => Word'Asm_Output ("=&r", PRIMASK),
+ Volatile => True);
+ Asm ("msr PRIMASK, %0",
+ Inputs => Word'Asm_Input ("r", 1),
+ Volatile => True);
+
+ -- Double the value of the COUNTER register since the RTC runs at
+ -- 32.768 kHz, but our Timer_Interval values are in scaled up units
+ -- (e.g. 65.536 kHz if RTC_Tick_Scaling_Factor is 2)
+ Res := Timer_Interval (RTC0_Periph.COUNTER.COUNTER);
+ Res := Res * BBOPA.RTC_Tick_Scaling_Factor;
+
+ -- Restore interrupt mask
+
+ Asm ("msr PRIMASK, %0",
+ Inputs => Word'Asm_Input ("r", PRIMASK),
+ Volatile => True);
+
+ return BB.Time.Time (Res);
+ end Read_Clock;
+
+ ---------------------------
+ -- Clear_Alarm_Interrupt --
+ ---------------------------
+
+ procedure Clear_Alarm_Interrupt is
+ begin
+ -- Only clear the COMPARE event; don't clear OVRFLW here since we
+ -- read (and clear) that event in Read_Clock to return the correct
+ -- time when an overflow occurs.
+ RTC0_Periph.EVENTS_COMPARE (0) := (EVENTS_COMPARE => 0, others => <>);
+ end Clear_Alarm_Interrupt;
+
+ ---------------
+ -- Set_Alarm --
+ ---------------
+
+ procedure Set_Alarm (Ticks : Timer_Interval) is
+ RTC_Counter : UInt24;
+
+ -- Remember that 'Ticks' is in scaled up ticks, but the RTC
+ -- peripheral actually runs at 32.768 kHz.
+ RTC_Ticks : UInt24 :=
+ UInt24 (Ticks / BBOPA.RTC_Tick_Scaling_Factor);
+
+ CC0_Value : UInt24;
+ RTC_Ticks_Until_Alarm : UInt24;
+
+ begin
+
+ -- If the COMPARE time is within 2 RTC cycles then it might be
+ -- missed due to mirroring of the RTC registers between the
+ -- PCLK16M and LFCLK domains.
+ -- Setting the CC[0] to COUNTER+2 is guaranteed to trigger an
+ -- event. See Section 23.7 of the nRF52832 Objective Product Spec.
+ RTC_Ticks := UInt24'Max (RTC_Ticks, 2);
+
+ -- Set an interrupt to trigger after the requested number of ticks.
+ RTC_Counter := RTC0_Periph.COUNTER.COUNTER;
+ CC0_Value := RTC_Counter + RTC_Ticks;
+ RTC0_Periph.CC (0).COMPARE := CC0_Value;
+
+ -- Note that the RTC might have ticked between reading COUNTER and
+ -- setting CC[0], which may break the guarantee that CC[0] is always
+ -- written as at least COUNTER+2.
+ --
+ -- We check for this below, and re-write CC[0] so that it is
+ -- guaranteed to trigger an interrupt. We also check for the unlikely
+ -- scenario that the COUNTER has gone past CC[0], in which case we
+ -- trigger the interrupt immediately.
+ -- This might result in an extra unecessary interrupt just before
+ -- the alarm time, but ensures the alarm time is not missed.
+
+ RTC_Counter := RTC0_Periph.COUNTER.COUNTER;
+ RTC_Ticks_Until_Alarm := CC0_Value - RTC_Counter;
+
+ if RTC_Ticks_Until_Alarm < 2
+ or Ticks = 0
+ or RTC_Ticks_Until_Alarm > RTC_Ticks
+ then
+ CC0_Value := RTC_Counter + RTC_Ticks;
+ RTC0_Periph.CC (0).COMPARE := CC0_Value;
+
+ Trigger_Interrupt (Alarm_Interrupt_ID);
+ end if;
+ end Set_Alarm;
+
+ ---------------------------
+ -- Install_Alarm_Handler --
+ ---------------------------
+
+ procedure Install_Alarm_Handler
+ (Handler : BB.Interrupts.Interrupt_Handler) is
+ begin
+ BB.Interrupts.Attach_Handler
+ (Handler,
+ Alarm_Interrupt_ID,
+ Interrupt_Priority'Last);
+
+ -- Clear pending timer interrupt if any
+ Time.Clear_Alarm_Interrupt;
+
+ -- Now that the interrupt handler is attached, we can start the timer
+ RTC0_Periph.TASKS_START := (TASKS_START => 1, others => <>);
+ end Install_Alarm_Handler;
+ end Time;
+
+ package body Multiprocessors is separate;
+
+ -----------------------
+ -- Interrupt_Handler --
+ -----------------------
+
+ procedure Interrupt_Handler is
+ Id : Interrupt_ID;
+ Res : Word;
+ PRIMASK : Word;
+ begin
+ Asm ("mrs %0, PRIMASK",
+ Outputs => Word'Asm_Output ("=&r", PRIMASK),
+ Volatile => True);
+ Asm ("msr PRIMASK, %0",
+ Inputs => Word'Asm_Input ("r", 1),
+ Volatile => True);
+
+ -- The exception number is read from the IPSR
+
+ Asm ("mrs %0, ipsr",
+ Word'Asm_Output ("=r", Res),
+ Volatile => True);
+
+ Res := Res and 16#FF#;
+
+ -- Convert it to IRQ number by substracting 16 (number of cpu
+ -- exceptions).
+
+ Id := Interrupt_ID'Base (Res) - 16;
+
+ Interrupt_Wrapper (Id);
+
+ -- Restore interrupt mask
+
+ Asm ("msr PRIMASK, %0",
+ Inputs => Word'Asm_Input ("r", PRIMASK),
+ Volatile => True);
+ end Interrupt_Handler;
+
+ ------------------------------
+ -- Enable_Interrupt_Request --
+ ------------------------------
+
+ procedure Enable_Interrupt_Request
+ (Interrupt : Interrupt_ID;
+ Prio : Interrupt_Priority)
+ is
+ begin
+ if Interrupt = Alarm_Interrupt_ID then
+
+ -- Consistency check with Priority_Of_Interrupt
+
+ pragma Assert (Prio = Interrupt_Priority'Last);
+
+ Time.Clear_Alarm_Interrupt;
+ end if;
+
+ declare
+ pragma Assert (Interrupt >= 0);
+ IRQ : constant Natural := Interrupt;
+ Regofs : constant Natural := IRQ / 32;
+ Regbit : constant Word := 2** (IRQ mod 32);
+ NVIC_ISER : array (0 .. 15) of Word
+ with Volatile, Address => NVIC_ISER0;
+
+ -- Many NVIC registers use 16 words of 32 bits each to serve as a
+ -- bitmap for all interrupt channels. Regofs indicates register
+ -- offset (0 .. 15), and Regbit indicates the mask required for
+ -- addressing the bit.
+
+ begin
+ NVIC_ISER (Regofs) := Regbit;
+ end;
+ end Enable_Interrupt_Request;
+
+ -----------------------
+ -- Trigger_Interrupt --
+ -----------------------
+ procedure Trigger_Interrupt (Interrupt : Interrupt_ID) is
+ begin
+ NVIC_STIR := Word (Interrupt) and 16#0000_01FF#;
+ end Trigger_Interrupt;
+
+ package body Interrupts is
+ -------------------------------
+ -- Install_Interrupt_Handler --
+ -------------------------------
+
+ procedure Install_Interrupt_Handler
+ (Interrupt : Interrupt_ID;
+ Prio : Interrupt_Priority)
+ is
+ begin
+ if Interrupt /= Alarm_Interrupt_ID then
+ IP (Interrupt) := To_PRI (Prio);
+ end if;
+
+ Enable_Interrupt_Request (Interrupt, Prio);
+ end Install_Interrupt_Handler;
+
+ ---------------------------
+ -- Priority_Of_Interrupt --
+ ---------------------------
+
+ function Priority_Of_Interrupt
+ (Interrupt : Interrupt_ID) return Any_Priority
+ is
+ (if Interrupt = Alarm_Interrupt_ID then Interrupt_Priority'Last
+ else To_Priority (IP (Interrupt)));
+
+ ----------------
+ -- Power_Down --
+ ----------------
+
+ procedure Power_Down is
+ begin
+ Asm ("wfi", Volatile => True);
+ end Power_Down;
+
+ --------------------------
+ -- Set_Current_Priority --
+ --------------------------
+
+ procedure Set_Current_Priority (Priority : Integer) is
+ begin
+ -- Writing a 0 to BASEPRI disables interrupt masking, while values
+ -- 15 .. 1 correspond to interrupt priorities 255 .. 241 in that
+ -- order.
+
+ Asm ("msr BASEPRI, %0",
+ Inputs => PRI'Asm_Input ("r", To_PRI (Priority)),
+ Volatile => True);
+ end Set_Current_Priority;
+ end Interrupts;
+end System.BB.Board_Support;
diff --git a/src/s-bbpara__nrf52.ads b/src/s-bbpara__nrf52.ads
new file mode 100644
index 00000000..59e445eb
--- /dev/null
+++ b/src/s-bbpara__nrf52.ads
@@ -0,0 +1,125 @@
+------------------------------------------------------------------------------
+-- --
+-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS --
+-- --
+-- S Y S T E M . B B . P A R A M E T E R S --
+-- --
+-- S p e c --
+-- --
+-- Copyright (C) 1999-2002 Universidad Politecnica de Madrid --
+-- Copyright (C) 2003-2005 The European Space Agency --
+-- Copyright (C) 2003-2019, AdaCore --
+-- --
+-- GNAT is free software; you can redistribute it and/or modify it under --
+-- terms of the GNU General Public License as published by the Free Soft- --
+-- ware Foundation; either version 3, or (at your option) any later ver- --
+-- sion. GNAT is distributed in the hope that it will be useful, but WITH- --
+-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY --
+-- or FITNESS FOR A PARTICULAR PURPOSE. --
+-- --
+-- As a special exception under Section 7 of GPL version 3, you are granted --
+-- additional permissions described in the GCC Runtime Library Exception, --
+-- version 3.1, as published by the Free Software Foundation. --
+-- --
+-- You should have received a copy of the GNU General Public License and --
+-- a copy of the GCC Runtime Library Exception along with this program; --
+-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see --
+-- . --
+-- --
+-- GNAT was originally developed by the GNAT team at New York University. --
+-- Extensive contributions were provided by Ada Core Technologies Inc. --
+-- --
+-- The port of GNARL to bare board targets was initially developed by the --
+-- Real-Time Systems Group at the Technical University of Madrid. --
+-- --
+------------------------------------------------------------------------------
+
+-- This package defines basic parameters used by the low level tasking system
+
+-- This is the nRF52840 (ARMv7) version of this package
+
+with System.BB.Board_Parameters;
+with System.BB.MCU_Parameters;
+
+package System.BB.Parameters is
+ pragma No_Elaboration_Code_All;
+ pragma Preelaborate (System.BB.Parameters);
+
+ Clock_Frequency : constant := Board_Parameters.Main_Clock_Frequency;
+ Ticks_Per_Second : constant := Clock_Frequency;
+
+ ----------------
+ -- Interrupts --
+ ----------------
+
+ -- These definitions are in this package in order to isolate target
+ -- dependencies.
+
+ subtype Interrupt_Range is Integer
+ range -1 .. MCU_Parameters.Number_Of_Interrupts;
+ -- Number of interrupts for the interrupt controller
+
+ Trap_Vectors : constant := 17;
+ -- While on this target there is little difference between interrupts
+ -- and traps, we consider the following traps:
+ --
+ -- Name Nr
+ --
+ -- Reset_Vector 1
+ -- NMI_Vector 2
+ -- Hard_Fault_Vector 3
+ -- Mem_Manage_Vector 4
+ -- Bus_Fault_Vector 5
+ -- Usage_Fault_Vector 6
+ -- SVC_Vector 11
+ -- Debug_Mon_Vector 12
+ -- Pend_SV_Vector 14
+ -- Sys_Tick_Vector 15
+ -- Interrupt_Request_Vector 16
+ --
+ -- These trap vectors correspond to different low-level trap handlers in
+ -- the run time. Note that as all interrupt requests (IRQs) will use the
+ -- same interrupt wrapper, there is no benefit to consider using separate
+ -- vectors for each.
+
+ Context_Buffer_Capacity : constant := 10;
+ -- The context buffer contains registers r4 .. r11 and the SP_process
+ -- (PSP). The size is rounded up to an even number for alignment
+
+ ------------
+ -- Stacks --
+ ------------
+
+ Interrupt_Stack_Size : constant := 2 * 1024;
+ -- Size of each of the interrupt stacks in bytes. While there nominally is
+ -- an interrupt stack per interrupt priority, the entire space is used as a
+ -- single stack.
+
+ Interrupt_Sec_Stack_Size : constant := 128;
+ -- Size of the secondary stack for interrupt handlers
+
+ Has_FPU : constant Boolean := True;
+ -- Set to true if core has a FPU
+
+ Has_VTOR : constant Boolean := True;
+ -- Set to true if core has a Vector Table Offset Register (VTOR).
+ -- VTOR is implemented in Cortex-M0+, Cortex-M4 and above.
+
+ Has_OS_Extensions : constant Boolean := True;
+ -- Set to true if core has armv6-m OS extensions (PendSV, MSP, PSP,
+ -- etc...). The OS extensions are optional for the Cortex-M1.
+
+ Is_ARMv6m : constant Boolean := False;
+ -- Set to true if core is an armv6-m (Cortex-M0, Cortex-M0+, Cortex-M1)
+
+ ----------
+ -- CPUS --
+ ----------
+
+ Max_Number_Of_CPUs : constant := 1;
+ -- Maximum number of CPUs
+
+ Multiprocessor : constant Boolean := Max_Number_Of_CPUs /= 1;
+ -- Are we on a multiprocessor board?
+
+end System.BB.Parameters;