@@ -5755,10 +5755,6 @@ opclass memory(indirect, indIndexScaled, indIndexScaledI2L, indIndexI2L, indInde
57555755 indirectN, indIndexScaledN, indIndexScaledI2LN, indIndexI2LN, indIndexN, indOffIN, indOffLN, indirectX2P, indOffX2P);
57565756
57575757
5758- opclass memory_noindex(indirect,
5759- indOffI1, indOffL1,indOffI2, indOffL2, indOffI4, indOffL4, indOffI8, indOffL8,
5760- indirectN, indOffIN, indOffLN, indirectX2P, indOffX2P);
5761-
57625758// iRegIorL2I is used for src inputs in rules for 32 bit int (I)
57635759// operations. it allows the src to be either an iRegI or a (ConvL2I
57645760// iRegL). in the latter case the l2i normally planted for a ConvL2I
@@ -6695,16 +6691,21 @@ instruct loadNKlass(iRegNNoSp dst, memory4 mem)
66956691 ins_pipe(iload_reg_mem);
66966692%}
66976693
6698- instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory_noindex mem)
6694+ instruct loadNKlassCompactHeaders(iRegNNoSp dst, memory4 mem)
66996695%{
67006696 match(Set dst (LoadNKlass mem));
67016697 predicate(!needs_acquiring_load(n) && UseCompactObjectHeaders);
67026698
67036699 ins_cost(4 * INSN_COST);
6704- format %{ "load_narrow_klass_compact $dst, $mem\t# compressed class ptr" %}
6700+ format %{
6701+ "ldrw $dst, $mem\t# compressed class ptr, shifted\n\t"
6702+ "lsrw $dst, $dst, markWord::klass_shift_at_offset"
6703+ %}
67056704 ins_encode %{
6706- assert($mem$$index$$Register == noreg, "must not have indexed address");
6707- __ load_narrow_klass_compact_c2($dst$$Register, $mem$$base$$Register, $mem$$disp);
6705+ // inlined aarch64_enc_ldrw
6706+ loadStore(masm, &MacroAssembler::ldrw, $dst$$Register, $mem->opcode(),
6707+ as_Register($mem$$base), $mem$$index, $mem$$scale, $mem$$disp, 4);
6708+ __ lsrw($dst$$Register, $dst$$Register, markWord::klass_shift_at_offset);
67086709 %}
67096710 ins_pipe(iload_reg_mem);
67106711%}
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