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loongson-jvmloongson-jvm
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Update (2022.09.03) (openjdk#3)
23864: Fix caller saved fpu regset 27580: Delete MIPS instructions in LA files 26659: Fix push_fpu/pop_fpu typo and implement push_vp/pop_vp to save/restore vector register
1 parent 57e68ca commit e45ae0f

11 files changed

+148
-160
lines changed

‎src/hotspot/cpu/loongarch/assembler_loongarch.hpp‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1609,7 +1609,6 @@ class Assembler : public AbstractAssembler {
16091609
static int get_vec_imm(float x);
16101610
static int get_vec_imm(double x);
16111611

1612-
// LoongArch lui is sign extended, so if you wan't to use imm, you have to use the follow
16131612
static int split_low16(int x) {
16141613
return (x & 0xffff);
16151614
}

‎src/hotspot/cpu/loongarch/gc/g1/g1BarrierSetAssembler_loongarch.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -428,10 +428,10 @@ void G1BarrierSetAssembler::generate_c1_pre_barrier_runtime_stub(StubAssembler*
428428
__ b(done);
429429

430430
__ bind(runtime);
431-
__ pushad();
431+
__ push_call_clobbered_registers();
432432
__ load_parameter(0, pre_val);
433433
__ call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_field_pre_entry), pre_val, TREG);
434-
__ popad();
434+
__ pop_call_clobbered_registers();
435435
__ bind(done);
436436

437437
__ epilogue();
@@ -496,9 +496,9 @@ void G1BarrierSetAssembler::generate_c1_post_barrier_runtime_stub(StubAssembler*
496496
__ b(done);
497497

498498
__ bind(runtime);
499-
__ pushad();
499+
__ push_call_clobbered_registers();
500500
__ call_VM_leaf(CAST_FROM_FN_PTR(address, G1BarrierSetRuntime::write_ref_field_post_entry), card_addr, TREG);
501-
__ popad();
501+
__ pop_call_clobbered_registers();
502502
__ bind(done);
503503
__ epilogue();
504504
}

‎src/hotspot/cpu/loongarch/gc/shenandoah/shenandoahBarrierSetAssembler_loongarch.cpp‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -285,7 +285,7 @@ void ShenandoahBarrierSetAssembler::load_reference_barrier(MacroAssembler* masm,
285285
__ beqz(SCR2, not_cset);
286286
}
287287

288-
__ pushad_except_v0();
288+
__ push_call_clobbered_registers_except(RegSet::of(V0));
289289
if (is_strong) {
290290
if (is_narrow) {
291291
__ li(RA, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_strong_narrow));
@@ -304,7 +304,7 @@ void ShenandoahBarrierSetAssembler::load_reference_barrier(MacroAssembler* masm,
304304
__ li(RA, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_phantom));
305305
}
306306
__ jalr(RA);
307-
__ popad_except_v0();
307+
__ pop_call_clobbered_registers_except(RegSet::of(V0));
308308

309309
__ bind(not_cset);
310310

@@ -320,9 +320,9 @@ void ShenandoahBarrierSetAssembler::load_reference_barrier(MacroAssembler* masm,
320320

321321
void ShenandoahBarrierSetAssembler::iu_barrier(MacroAssembler* masm, Register dst, Register tmp) {
322322
if (ShenandoahIUBarrier) {
323-
__ pushad();
323+
__ push_call_clobbered_registers();
324324
satb_write_barrier_pre(masm, noreg, dst, TREG, tmp, true, false);
325-
__ popad();
325+
__ pop_call_clobbered_registers();
326326
}
327327
}
328328

@@ -374,15 +374,15 @@ void ShenandoahBarrierSetAssembler::load_at(MacroAssembler* masm, DecoratorSet d
374374
// 3: apply keep-alive barrier if needed
375375
if (ShenandoahBarrierSet::need_keep_alive_barrier(decorators, type)) {
376376
__ enter();
377-
__ pushad();
377+
__ push_call_clobbered_registers();
378378
satb_write_barrier_pre(masm /* masm */,
379379
noreg /* obj */,
380380
dst /* pre_val */,
381381
TREG /* thread */,
382382
tmp1 /* tmp */,
383383
true /* tosca_live */,
384384
true /* expand_call */);
385-
__ popad();
385+
__ pop_call_clobbered_registers();
386386
__ leave();
387387
}
388388
}
@@ -729,10 +729,10 @@ void ShenandoahBarrierSetAssembler::generate_c1_pre_barrier_runtime_stub(StubAss
729729
__ b(done);
730730

731731
__ bind(runtime);
732-
__ pushad();
732+
__ push_call_clobbered_registers();
733733
__ load_parameter(0, pre_val);
734734
__ call_VM_leaf(CAST_FROM_FN_PTR(address, ShenandoahRuntime::write_ref_field_pre_entry), pre_val, thread);
735-
__ popad();
735+
__ pop_call_clobbered_registers();
736736
__ bind(done);
737737

738738
__ epilogue();
@@ -743,7 +743,7 @@ void ShenandoahBarrierSetAssembler::generate_c1_load_reference_barrier_runtime_s
743743
__ bstrins_d(SP, R0, 3, 0);
744744
// arg0 : object to be resolved
745745

746-
__ pushad_except_v0();
746+
__ push_call_clobbered_registers_except(RegSet::of(V0));
747747
__ load_parameter(0, A0);
748748
__ load_parameter(1, A1);
749749

@@ -774,7 +774,7 @@ void ShenandoahBarrierSetAssembler::generate_c1_load_reference_barrier_runtime_s
774774
__ li(RA, CAST_FROM_FN_PTR(address, ShenandoahRuntime::load_reference_barrier_phantom));
775775
}
776776
__ jalr(RA);
777-
__ popad_except_v0();
777+
__ pop_call_clobbered_registers_except(RegSet::of(V0));
778778

779779
__ epilogue();
780780
}

‎src/hotspot/cpu/loongarch/gc/z/zBarrierSetAssembler_loongarch.cpp‎

Lines changed: 20 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -99,15 +99,15 @@ void ZBarrierSetAssembler::load_at(MacroAssembler* masm,
9999
if (dst != V0) {
100100
__ push(V0);
101101
}
102-
__ pushad_except_v0();
102+
__ push_call_clobbered_registers_except(RegSet::of(V0));
103103

104104
if (dst != A0) {
105105
__ move(A0, dst);
106106
}
107107
__ move(A1, scratch);
108108
__ MacroAssembler::call_VM_leaf_base(ZBarrierSetRuntime::load_barrier_on_oop_field_preloaded_addr(decorators), 2);
109109

110-
__ popad_except_v0();
110+
__ pop_call_clobbered_registers_except(RegSet::of(V0));
111111

112112
// Make sure dst has the return value.
113113
if (dst != V0) {
@@ -290,15 +290,15 @@ void ZBarrierSetAssembler::generate_c1_load_barrier_runtime_stub(StubAssembler*
290290
DecoratorSet decorators) const {
291291
__ prologue("zgc_load_barrier stub", false);
292292

293-
__ pushad_except_v0();
293+
__ push_call_clobbered_registers_except(RegSet::of(V0));
294294

295295
// Setup arguments
296296
__ load_parameter(0, A0);
297297
__ load_parameter(1, A1);
298298

299299
__ call_VM_leaf(ZBarrierSetRuntime::load_barrier_on_oop_field_preloaded_addr(decorators), 2);
300300

301-
__ popad_except_v0();
301+
__ pop_call_clobbered_registers_except(RegSet::of(V0));
302302

303303
__ epilogue();
304304
}
@@ -327,6 +327,8 @@ class ZSaveLiveRegisters {
327327
MacroAssembler* const _masm;
328328
RegSet _gp_regs;
329329
FloatRegSet _fp_regs;
330+
FloatRegSet _lsx_vp_regs;
331+
FloatRegSet _lasx_vp_regs;
330332

331333
public:
332334
void initialize(ZLoadBarrierStubC2* stub) {
@@ -339,32 +341,43 @@ class ZSaveLiveRegisters {
339341
if (vm_reg->is_Register()) {
340342
_gp_regs += RegSet::of(vm_reg->as_Register());
341343
} else if (vm_reg->is_FloatRegister()) {
342-
_fp_regs += FloatRegSet::of(vm_reg->as_FloatRegister());
344+
if (UseLASX && vm_reg->next(7))
345+
_lasx_vp_regs += FloatRegSet::of(vm_reg->as_FloatRegister());
346+
else if (UseLSX && vm_reg->next(3))
347+
_lsx_vp_regs += FloatRegSet::of(vm_reg->as_FloatRegister());
348+
else
349+
_fp_regs += FloatRegSet::of(vm_reg->as_FloatRegister());
343350
} else {
344351
fatal("Unknown register type");
345352
}
346353
}
347354
}
348355

349356
// Remove C-ABI SOE registers, scratch regs and _ref register that will be updated
350-
_gp_regs -= RegSet::range(r23, r30) + RegSet::of(r3, r16, r19, stub->ref());
357+
_gp_regs -= RegSet::range(S0, S7) + RegSet::of(SP, SCR1, SCR2, stub->ref());
351358
}
352359

353360
ZSaveLiveRegisters(MacroAssembler* masm, ZLoadBarrierStubC2* stub) :
354361
_masm(masm),
355362
_gp_regs(),
356-
_fp_regs() {
363+
_fp_regs(),
364+
_lsx_vp_regs(),
365+
_lasx_vp_regs() {
357366

358367
// Figure out what registers to save/restore
359368
initialize(stub);
360369

361370
// Save registers
362371
__ push(_gp_regs);
363372
__ push_fpu(_fp_regs);
373+
__ push_vp(_lsx_vp_regs /* UseLSX */);
374+
__ push_vp(_lasx_vp_regs /* UseLASX */);
364375
}
365376

366377
~ZSaveLiveRegisters() {
367378
// Restore registers
379+
__ pop_vp(_lasx_vp_regs /* UseLASX */);
380+
__ pop_vp(_lsx_vp_regs /* UseLSX */);
368381
__ pop_fpu(_fp_regs);
369382
__ pop(_gp_regs);
370383
}

‎src/hotspot/cpu/loongarch/loongarch_64.ad‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8895,7 +8895,7 @@ instruct addI_salI_Reg_Reg_immI_1_4(mRegI dst, mRegI src1, mRegI src2, immI_1_4
88958895
instruct addP_reg_reg(mRegP dst, mRegP src1, mRegLorI2L src2) %{
88968896
match(Set dst (AddP src1 src2));
88978897

8898-
format %{ "dadd $dst, $src1, $src2 #@addP_reg_reg" %}
8898+
format %{ "ADD $dst, $src1, $src2 #@addP_reg_reg" %}
88998899

89008900
ins_encode %{
89018901
Register dst = $dst$$Register;
@@ -8910,7 +8910,7 @@ instruct addP_reg_reg(mRegP dst, mRegP src1, mRegLorI2L src2) %{
89108910
instruct addP_reg_imm12(mRegP dst, mRegP src1, immL12 src2) %{
89118911
match(Set dst (AddP src1 src2));
89128912

8913-
format %{ "daddi $dst, $src1, $src2 #@addP_reg_imm12" %}
8913+
format %{ "ADD $dst, $src1, $src2 #@addP_reg_imm12" %}
89148914
ins_encode %{
89158915
Register src1 = $src1$$Register;
89168916
long src2 = $src2$$constant;
@@ -10920,7 +10920,7 @@ instruct CallLeafNoFPDirect(method meth) %{
1092010920
instruct prefetchAlloc(memory mem) %{
1092110921
match(PrefetchAllocation mem);
1092210922
ins_cost(125);
10923-
format %{ "pref $mem\t# Prefetch allocation @ prefetchAlloc" %}
10923+
format %{ "preld $mem\t# Prefetch allocation @ prefetchAlloc" %}
1092410924
ins_encode %{
1092510925
int base = $mem$$base;
1092610926
int index = $mem$$index;
@@ -11238,7 +11238,7 @@ instruct loadSSF(regF dst, stackSlotF src)
1123811238
match(Set dst src);
1123911239

1124011240
ins_cost(125);
11241-
format %{ "lwc1 $dst, $src\t# float stk @ loadSSF" %}
11241+
format %{ "fld_s $dst, $src\t# float stk @ loadSSF" %}
1124211242
ins_encode %{
1124311243
guarantee( Assembler::is_simm($src$$disp, 12), "disp too long (loadSSF) !");
1124411244
__ fld_s($dst$$FloatRegister, SP, $src$$disp);
@@ -11251,7 +11251,7 @@ instruct storeSSF(stackSlotF dst, regF src)
1125111251
match(Set dst src);
1125211252

1125311253
ins_cost(100);
11254-
format %{ "swc1 $dst, $src\t# float stk @ storeSSF" %}
11254+
format %{ "fst_s $dst, $src\t# float stk @ storeSSF" %}
1125511255
ins_encode %{
1125611256
guarantee( Assembler::is_simm($dst$$disp, 12), "disp too long (storeSSF) !");
1125711257
__ fst_s($src$$FloatRegister, SP, $dst$$disp);
@@ -11265,7 +11265,7 @@ instruct loadSSD(regD dst, stackSlotD src)
1126511265
match(Set dst src);
1126611266

1126711267
ins_cost(125);
11268-
format %{ "ldc1 $dst, $src\t# double stk @ loadSSD" %}
11268+
format %{ "fld_d $dst, $src\t# double stk @ loadSSD" %}
1126911269
ins_encode %{
1127011270
guarantee( Assembler::is_simm($src$$disp, 12), "disp too long (loadSSD) !");
1127111271
__ fld_d($dst$$FloatRegister, SP, $src$$disp);

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