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loongson-jvmloongson-jvm
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Update (2023.09.20, 2nd)
32268: [shenandoah] Use indirect memory operand for cmpxchg 32266: [C2] Effect TEMP_DEF res for get_and_set/add 32163: The size of is_wide_vector should be greater than 8 bytes
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4 files changed

+38
-58
lines changed

4 files changed

+38
-58
lines changed

‎src/hotspot/cpu/loongarch/gc/shenandoah/shenandoah_loongarch_64.ad‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -44,7 +44,7 @@ encode %{
4444
%}
4545
%}
4646

47-
instruct compareAndSwapP_shenandoah(mRegI res, memory_exclusive mem, mRegP oldval, mRegP newval) %{
47+
instruct compareAndSwapP_shenandoah(mRegI res, indirect mem, mRegP oldval, mRegP newval) %{
4848
match(Set res (ShenandoahCompareAndSwapP mem (Binary oldval newval)));
4949

5050
format %{
@@ -56,7 +56,7 @@ instruct compareAndSwapP_shenandoah(mRegI res, memory_exclusive mem, mRegP oldva
5656
ins_pipe(pipe_slow);
5757
%}
5858

59-
instruct compareAndSwapN_shenandoah(mRegI res, memory_exclusive mem, mRegN oldval, mRegN newval) %{
59+
instruct compareAndSwapN_shenandoah(mRegI res, indirect mem, mRegN oldval, mRegN newval) %{
6060
match(Set res (ShenandoahCompareAndSwapN mem (Binary oldval newval)));
6161

6262
format %{
@@ -72,7 +72,7 @@ instruct compareAndSwapN_shenandoah(mRegI res, memory_exclusive mem, mRegN oldva
7272
ins_pipe(pipe_slow);
7373
%}
7474

75-
instruct compareAndSwapPAcq_shenandoah(mRegI res, memory_exclusive mem, mRegP oldval, mRegP newval) %{
75+
instruct compareAndSwapPAcq_shenandoah(mRegI res, indirect mem, mRegP oldval, mRegP newval) %{
7676
match(Set res (ShenandoahCompareAndSwapP mem (Binary oldval newval)));
7777

7878
format %{
@@ -84,7 +84,7 @@ instruct compareAndSwapPAcq_shenandoah(mRegI res, memory_exclusive mem, mRegP ol
8484
ins_pipe(pipe_slow);
8585
%}
8686

87-
instruct compareAndSwapNAcq_shenandoah(mRegI res, memory_exclusive mem, mRegN oldval, mRegN newval) %{
87+
instruct compareAndSwapNAcq_shenandoah(mRegI res, indirect mem, mRegN oldval, mRegN newval) %{
8888
match(Set res (ShenandoahCompareAndSwapN mem (Binary oldval newval)));
8989

9090
format %{
@@ -100,7 +100,7 @@ instruct compareAndSwapNAcq_shenandoah(mRegI res, memory_exclusive mem, mRegN ol
100100
ins_pipe(pipe_slow);
101101
%}
102102

103-
instruct compareAndExchangeN_shenandoah(mRegN res, memory_exclusive mem, mRegN oldval, mRegN newval) %{
103+
instruct compareAndExchangeN_shenandoah(mRegN res, indirect mem, mRegN oldval, mRegN newval) %{
104104
match(Set res (ShenandoahCompareAndExchangeN mem (Binary oldval newval)));
105105

106106
format %{
@@ -116,7 +116,7 @@ instruct compareAndExchangeN_shenandoah(mRegN res, memory_exclusive mem, mRegN o
116116
ins_pipe(pipe_slow);
117117
%}
118118

119-
instruct compareAndExchangeP_shenandoah(mRegP res, memory_exclusive mem, mRegP oldval, mRegP newval) %{
119+
instruct compareAndExchangeP_shenandoah(mRegP res, indirect mem, mRegP oldval, mRegP newval) %{
120120
match(Set res (ShenandoahCompareAndExchangeP mem (Binary oldval newval)));
121121

122122
format %{
@@ -132,7 +132,7 @@ instruct compareAndExchangeP_shenandoah(mRegP res, memory_exclusive mem, mRegP o
132132
ins_pipe(pipe_slow);
133133
%}
134134

135-
instruct compareAndExchangeNAcq_shenandoah(mRegN res, memory_exclusive mem, mRegN oldval, mRegN newval) %{
135+
instruct compareAndExchangeNAcq_shenandoah(mRegN res, indirect mem, mRegN oldval, mRegN newval) %{
136136
match(Set res (ShenandoahCompareAndExchangeN mem (Binary oldval newval)));
137137

138138
format %{
@@ -148,7 +148,7 @@ instruct compareAndExchangeNAcq_shenandoah(mRegN res, memory_exclusive mem, mReg
148148
ins_pipe(pipe_slow);
149149
%}
150150

151-
instruct compareAndExchangePAcq_shenandoah(mRegP res, memory_exclusive mem, mRegP oldval, mRegP newval) %{
151+
instruct compareAndExchangePAcq_shenandoah(mRegP res, indirect mem, mRegP oldval, mRegP newval) %{
152152
match(Set res (ShenandoahCompareAndExchangeP mem (Binary oldval newval)));
153153

154154
format %{
@@ -164,7 +164,7 @@ instruct compareAndExchangePAcq_shenandoah(mRegP res, memory_exclusive mem, mReg
164164
ins_pipe(pipe_slow);
165165
%}
166166

167-
instruct weakCompareAndSwapN_shenandoah(mRegI res, memory_exclusive mem, mRegN oldval, mRegN newval) %{
167+
instruct weakCompareAndSwapN_shenandoah(mRegI res, indirect mem, mRegN oldval, mRegN newval) %{
168168
match(Set res (ShenandoahWeakCompareAndSwapN mem (Binary oldval newval)));
169169

170170
format %{
@@ -180,7 +180,7 @@ instruct weakCompareAndSwapN_shenandoah(mRegI res, memory_exclusive mem, mRegN o
180180
ins_pipe(pipe_slow);
181181
%}
182182

183-
instruct weakCompareAndSwapP_shenandoah(mRegI res, memory_exclusive mem, mRegP oldval, mRegP newval) %{
183+
instruct weakCompareAndSwapP_shenandoah(mRegI res, indirect mem, mRegP oldval, mRegP newval) %{
184184
match(Set res (ShenandoahWeakCompareAndSwapP mem (Binary oldval newval)));
185185

186186
format %{
@@ -197,7 +197,7 @@ instruct weakCompareAndSwapP_shenandoah(mRegI res, memory_exclusive mem, mRegP o
197197
ins_pipe(pipe_slow);
198198
%}
199199

200-
instruct weakCompareAndSwapNAcq_shenandoah(mRegI res, memory_exclusive mem, mRegN oldval, mRegN newval) %{
200+
instruct weakCompareAndSwapNAcq_shenandoah(mRegI res, indirect mem, mRegN oldval, mRegN newval) %{
201201
match(Set res (ShenandoahWeakCompareAndSwapN mem (Binary oldval newval)));
202202

203203
format %{
@@ -214,7 +214,7 @@ instruct weakCompareAndSwapNAcq_shenandoah(mRegI res, memory_exclusive mem, mReg
214214
ins_pipe(pipe_slow);
215215
%}
216216

217-
instruct weakCompareAndSwapPAcq_shenandoah(mRegI res, memory_exclusive mem, mRegP oldval, mRegP newval) %{
217+
instruct weakCompareAndSwapPAcq_shenandoah(mRegI res, indirect mem, mRegP oldval, mRegP newval) %{
218218
match(Set res (ShenandoahWeakCompareAndSwapP mem (Binary oldval newval)));
219219

220220
format %{

‎src/hotspot/cpu/loongarch/gc/x/x_loongarch_64.ad‎

Lines changed: 1 addition & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -248,12 +248,7 @@ instruct xGetAndSetP(mRegP mem, mRegP newv, mRegP prev, mRegP tmp) %{
248248
Register newv = $newv$$Register;
249249
Register addr = $mem$$Register;
250250
__ block_comment("xGetAndSetP");
251-
if (prev == newv || prev == addr) {
252-
__ amswap_db_d(AT, newv, addr);
253-
__ move(prev, AT);
254-
} else {
255-
__ amswap_db_d(prev, newv, addr);
256-
}
251+
__ amswap_db_d(prev, newv, addr);
257252
x_load_barrier(_masm, this, Address(noreg, 0), prev, $tmp$$Register, barrier_data());
258253
%}
259254

‎src/hotspot/cpu/loongarch/loongarch_64.ad‎

Lines changed: 23 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -11955,44 +11955,38 @@ instruct compareAndSwapN(mRegI res, indirect mem_ptr, mRegN oldval, mRegN newval
1195511955

1195611956
instruct get_and_setI(indirect mem, mRegI newv, mRegI prev) %{
1195711957
match(Set prev (GetAndSetI mem newv));
11958+
effect(TEMP_DEF prev);
1195811959
ins_cost(2 * MEMORY_REF_COST);
11959-
format %{ "amswap_db_w $prev, $newv, [$mem]" %}
11960+
format %{ "amswap_db_w $prev, $newv, [$mem] @get_and_setI" %}
1196011961
ins_encode %{
1196111962
Register prev = $prev$$Register;
1196211963
Register newv = $newv$$Register;
1196311964
Register addr = as_Register($mem$$base);
11964-
if (prev == newv || prev == addr) {
11965-
__ amswap_db_w(AT, newv, addr);
11966-
__ move(prev, AT);
11967-
} else {
11968-
__ amswap_db_w(prev, newv, addr);
11969-
}
11965+
11966+
__ amswap_db_w(prev, newv, addr);
1197011967
%}
1197111968
ins_pipe( pipe_serial );
1197211969
%}
1197311970

1197411971
instruct get_and_setL(indirect mem, mRegL newv, mRegL prev) %{
1197511972
match(Set prev (GetAndSetL mem newv));
11973+
effect(TEMP_DEF prev);
1197611974
ins_cost(2 * MEMORY_REF_COST);
11977-
format %{ "amswap_db_d $prev, $newv, [$mem]" %}
11975+
format %{ "amswap_db_d $prev, $newv, [$mem] @get_and_setL" %}
1197811976
ins_encode %{
1197911977
Register prev = $prev$$Register;
1198011978
Register newv = $newv$$Register;
1198111979
Register addr = as_Register($mem$$base);
11982-
if (prev == newv || prev == addr) {
11983-
__ amswap_db_d(AT, newv, addr);
11984-
__ move(prev, AT);
11985-
} else {
11986-
__ amswap_db_d(prev, newv, addr);
11987-
}
11980+
11981+
__ amswap_db_d(prev, newv, addr);
1198811982
%}
1198911983
ins_pipe( pipe_serial );
1199011984
%}
1199111985

1199211986
instruct get_and_setN(indirect mem, mRegN newv, mRegN prev) %{
1199311987
match(Set prev (GetAndSetN mem newv));
1199411988
ins_cost(2 * MEMORY_REF_COST);
11995-
format %{ "amswap_db_w $prev, $newv, [$mem]" %}
11989+
format %{ "amswap_db_w $prev, $newv, [$mem] @get_and_setN" %}
1199611990
ins_encode %{
1199711991
Register prev = $prev$$Register;
1199811992
Register newv = $newv$$Register;
@@ -12005,36 +11999,30 @@ instruct get_and_setN(indirect mem, mRegN newv, mRegN prev) %{
1200511999

1200612000
instruct get_and_setP(indirect mem, mRegP newv, mRegP prev) %{
1200712001
match(Set prev (GetAndSetP mem newv));
12002+
effect(TEMP_DEF prev);
1200812003
ins_cost(2 * MEMORY_REF_COST);
12009-
format %{ "amswap_db_d $prev, $newv, [$mem]" %}
12004+
format %{ "amswap_db_d $prev, $newv, [$mem] @get_and_setP" %}
1201012005
ins_encode %{
1201112006
Register prev = $prev$$Register;
1201212007
Register newv = $newv$$Register;
1201312008
Register addr = as_Register($mem$$base);
12014-
if (prev == newv || prev == addr) {
12015-
__ amswap_db_d(AT, newv, addr);
12016-
__ move(prev, AT);
12017-
} else {
12018-
__ amswap_db_d(prev, newv, addr);
12019-
}
12009+
12010+
__ amswap_db_d(prev, newv, addr);
1202012011
%}
1202112012
ins_pipe( pipe_serial );
1202212013
%}
1202312014

1202412015
instruct get_and_addL(indirect mem, mRegL newval, mRegL incr) %{
1202512016
match(Set newval (GetAndAddL mem incr));
12017+
effect(TEMP_DEF newval);
1202612018
ins_cost(2 * MEMORY_REF_COST + 1);
12027-
format %{ "amadd_db_d $newval, [$mem], $incr" %}
12019+
format %{ "amadd_db_d $newval, [$mem], $incr @get_and_addL" %}
1202812020
ins_encode %{
1202912021
Register newv = $newval$$Register;
1203012022
Register incr = $incr$$Register;
1203112023
Register addr = as_Register($mem$$base);
12032-
if (newv == incr || newv == addr) {
12033-
__ amadd_db_d(AT, incr, addr);
12034-
__ move(newv, AT);
12035-
} else {
12036-
__ amadd_db_d(newv, incr, addr);
12037-
}
12024+
12025+
__ amadd_db_d(newv, incr, addr);
1203812026
%}
1203912027
ins_pipe( pipe_serial );
1204012028
%}
@@ -12043,7 +12031,7 @@ instruct get_and_addL_no_res(indirect mem, Universe dummy, mRegL incr) %{
1204312031
predicate(n->as_LoadStore()->result_not_used());
1204412032
match(Set dummy (GetAndAddL mem incr));
1204512033
ins_cost(2 * MEMORY_REF_COST);
12046-
format %{ "amadd_db_d [$mem], $incr" %}
12034+
format %{ "amadd_db_d [$mem], $incr @get_and_addL_no_res" %}
1204712035
ins_encode %{
1204812036
__ amadd_db_d(R0, $incr$$Register, as_Register($mem$$base));
1204912037
%}
@@ -12052,18 +12040,15 @@ instruct get_and_addL_no_res(indirect mem, Universe dummy, mRegL incr) %{
1205212040

1205312041
instruct get_and_addI(indirect mem, mRegI newval, mRegIorL2I incr) %{
1205412042
match(Set newval (GetAndAddI mem incr));
12043+
effect(TEMP_DEF newval);
1205512044
ins_cost(2 * MEMORY_REF_COST + 1);
12056-
format %{ "amadd_db_w $newval, [$mem], $incr" %}
12045+
format %{ "amadd_db_w $newval, [$mem], $incr @get_and_addI" %}
1205712046
ins_encode %{
1205812047
Register newv = $newval$$Register;
1205912048
Register incr = $incr$$Register;
1206012049
Register addr = as_Register($mem$$base);
12061-
if (newv == incr || newv == addr) {
12062-
__ amadd_db_w(AT, incr, addr);
12063-
__ move(newv, AT);
12064-
} else {
12065-
__ amadd_db_w(newv, incr, addr);
12066-
}
12050+
12051+
__ amadd_db_w(newv, incr, addr);
1206712052
%}
1206812053
ins_pipe( pipe_serial );
1206912054
%}
@@ -12072,7 +12057,7 @@ instruct get_and_addI_no_res(indirect mem, Universe dummy, mRegIorL2I incr) %{
1207212057
predicate(n->as_LoadStore()->result_not_used());
1207312058
match(Set dummy (GetAndAddI mem incr));
1207412059
ins_cost(2 * MEMORY_REF_COST);
12075-
format %{ "amadd_db_w [$mem], $incr" %}
12060+
format %{ "amadd_db_w [$mem], $incr @get_and_addI_no_res" %}
1207612061
ins_encode %{
1207712062
__ amadd_db_w(R0, $incr$$Register, as_Register($mem$$base));
1207812063
%}

‎src/hotspot/cpu/loongarch/sharedRuntime_loongarch_64.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -311,9 +311,9 @@ void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
311311
}
312312

313313
// Is vector's size (in bytes) bigger than a size saved by default?
314-
// 16 bytes XMM registers are saved by default using fxsave/fxrstor instructions.
314+
// 8 bytes registers are saved by default using fld/fst instructions.
315315
bool SharedRuntime::is_wide_vector(int size) {
316-
return size > 16;
316+
return size > 8;
317317
}
318318

319319
// ---------------------------------------------------------------------------

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