Update (2022.09.30)

28135: Add linux-loongarch64 to CheckedFeatures.notImplemented
28039: Fix typo for generate_method_entry_barrier and BarrierSetAssembler::nmethod_entry_barrier
28128: using Address reference as argument
28133: 8293657: sun/management/jmxremote/bootstrap/RmiBootstrapTest.java#id1 failed with "SSLHandshakeException: Remote host terminated the handshake"
27811: [LA][C2] xml.validation fatal error SIGSEGV with +UseFPUForSpilling
28051: LA port of 8293660: Fix frame::sender_for_compiled_frame frame size assert
27891: Deprecated assembler removal
27957: Mark stub code without alignment padding
27965: Remove unused CORE macro definition
28048: Enable hsdis for loongarch64

Author: loongson-jvm

src/hotspot/cpu/loongarch/assembler_loongarch.cpp

@@ -105,7 +105,7 @@ int AbstractAssembler::code_fill_byte() {
 }
 
 // Now the Assembler instruction (identical for 32/64 bits)
-void Assembler::ld_b(Register rd, Address src) {
+void Assembler::ld_b(Register rd, const Address &src) {
   Register dst   = rd;
   Register base  = src.base();
   Register index = src.index();
@@ -150,7 +150,7 @@ void Assembler::ld_b(Register rd, Address src) {
   }
 }
 
-void Assembler::ld_bu(Register rd, Address src) {
+void Assembler::ld_bu(Register rd, const Address &src) {
   Register dst   = rd;
   Register base  = src.base();
   Register index = src.index();
@@ -195,7 +195,7 @@ void Assembler::ld_bu(Register rd, Address src) {
   }
 }
 
-void Assembler::ld_d(Register rd, Address src){
+void Assembler::ld_d(Register rd, const Address &src) {
   Register dst   = rd;
   Register base  = src.base();
   Register index = src.index();
@@ -249,7 +249,7 @@ void Assembler::ld_d(Register rd, Address src){
   }
 }
 
-void Assembler::ld_h(Register rd, Address src){
+void Assembler::ld_h(Register rd, const Address &src) {
   Register dst   = rd;
   Register base  = src.base();
   Register index = src.index();
@@ -294,7 +294,7 @@ void Assembler::ld_h(Register rd, Address src){
   }
 }
 
-void Assembler::ld_hu(Register rd, Address src){
+void Assembler::ld_hu(Register rd, const Address &src) {
   Register dst   = rd;
   Register base  = src.base();
   Register index = src.index();
@@ -339,17 +339,17 @@ void Assembler::ld_hu(Register rd, Address src){
   }
 }
 
-void Assembler::ll_w(Register rd, Address src){
+void Assembler::ll_w(Register rd, const Address &src) {
   assert(src.index() == NOREG, "index is unimplemented");
   ll_w(rd, src.base(), src.disp());
 }
 
-void Assembler::ll_d(Register rd, Address src){
+void Assembler::ll_d(Register rd, const Address &src) {
   assert(src.index() == NOREG, "index is unimplemented");
   ll_d(rd, src.base(), src.disp());
 }
 
-void Assembler::ld_w(Register rd, Address src){
+void Assembler::ld_w(Register rd, const Address &src) {
   Register dst   = rd;
   Register base  = src.base();
   Register index = src.index();
@@ -403,7 +403,7 @@ void Assembler::ld_w(Register rd, Address src){
   }
 }
 
-void Assembler::ld_wu(Register rd, Address src){
+void Assembler::ld_wu(Register rd, const Address &src) {
   Register dst   = rd;
   Register base  = src.base();
   Register index = src.index();
@@ -448,7 +448,7 @@ void Assembler::ld_wu(Register rd, Address src){
   }
 }
 
-void Assembler::st_b(Register rd, Address dst) {
+void Assembler::st_b(Register rd, const Address &dst) {
   Register src   = rd;
   Register base  = dst.base();
   Register index = dst.index();
@@ -495,17 +495,17 @@ void Assembler::st_b(Register rd, Address dst) {
   }
 }
 
-void Assembler::sc_w(Register rd, Address dst) {
+void Assembler::sc_w(Register rd, const Address &dst) {
   assert(dst.index() == NOREG, "index is unimplemented");
   sc_w(rd, dst.base(), dst.disp());
 }
 
-void Assembler::sc_d(Register rd, Address dst) {
+void Assembler::sc_d(Register rd, const Address &dst) {
   assert(dst.index() == NOREG, "index is unimplemented");
   sc_d(rd, dst.base(), dst.disp());
 }
 
-void Assembler::st_d(Register rd, Address dst) {
+void Assembler::st_d(Register rd, const Address &dst) {
   Register src   = rd;
   Register base  = dst.base();
   Register index = dst.index();
@@ -561,7 +561,7 @@ void Assembler::st_d(Register rd, Address dst) {
   }
 }
 
-void Assembler::st_h(Register rd, Address dst) {
+void Assembler::st_h(Register rd, const Address &dst) {
   Register src   = rd;
   Register base  = dst.base();
   Register index = dst.index();
@@ -608,7 +608,7 @@ void Assembler::st_h(Register rd, Address dst) {
   }
 }
 
-void Assembler::st_w(Register rd, Address dst) {
+void Assembler::st_w(Register rd, const Address &dst) {
   Register src   = rd;
   Register base  = dst.base();
   Register index = dst.index();
@@ -664,7 +664,7 @@ void Assembler::st_w(Register rd, Address dst) {
   }
 }
 
-void Assembler::fld_s(FloatRegister fd, Address src) {
+void Assembler::fld_s(FloatRegister fd, const Address &src) {
   Register base  = src.base();
   Register index = src.index();
 
@@ -708,7 +708,7 @@ void Assembler::fld_s(FloatRegister fd, Address src) {
   }
 }
 
-void Assembler::fld_d(FloatRegister fd, Address src) {
+void Assembler::fld_d(FloatRegister fd, const Address &src) {
   Register base  = src.base();
   Register index = src.index();
 
@@ -752,7 +752,7 @@ void Assembler::fld_d(FloatRegister fd, Address src) {
   }
 }
 
-void Assembler::fst_s(FloatRegister fd, Address dst) {
+void Assembler::fst_s(FloatRegister fd, const Address &dst) {
   Register base  = dst.base();
   Register index = dst.index();
 
@@ -796,7 +796,7 @@ void Assembler::fst_s(FloatRegister fd, Address dst) {
   }
 }
 
-void Assembler::fst_d(FloatRegister fd, Address dst) {
+void Assembler::fst_d(FloatRegister fd, const Address &dst) {
   Register base  = dst.base();
   Register index = dst.index();
 

src/hotspot/cpu/loongarch/assembler_loongarch.hpp

@@ -2074,25 +2074,25 @@ class Assembler : public AbstractAssembler  {
   void fstx_s (FloatRegister fd, Register rj, Register rk) { emit_int32(insn_RRR(fstx_s_op,    (int)rk->encoding(), (int)rj->encoding(), (int)fd->encoding())); }
   void fstx_d (FloatRegister fd, Register rj, Register rk) { emit_int32(insn_RRR(fstx_d_op,    (int)rk->encoding(), (int)rj->encoding(), (int)fd->encoding())); }
 
-  void ld_b  (Register rd, Address src);
-  void ld_bu (Register rd, Address src);
-  void ld_d  (Register rd, Address src);
-  void ld_h  (Register rd, Address src);
-  void ld_hu (Register rd, Address src);
-  void ll_w  (Register rd, Address src);
-  void ll_d  (Register rd, Address src);
-  void ld_wu (Register rd, Address src);
-  void ld_w  (Register rd, Address src);
-  void st_b  (Register rd, Address dst);
-  void st_d  (Register rd, Address dst);
-  void st_w  (Register rd, Address dst);
-  void sc_w  (Register rd, Address dst);
-  void sc_d  (Register rd, Address dst);
-  void st_h  (Register rd, Address dst);
-  void fld_s (FloatRegister fd, Address src);
-  void fld_d (FloatRegister fd, Address src);
-  void fst_s (FloatRegister fd, Address dst);
-  void fst_d (FloatRegister fd, Address dst);
+  void ld_b  (Register rd, const Address &src);
+  void ld_bu (Register rd, const Address &src);
+  void ld_d  (Register rd, const Address &src);
+  void ld_h  (Register rd, const Address &src);
+  void ld_hu (Register rd, const Address &src);
+  void ll_w  (Register rd, const Address &src);
+  void ll_d  (Register rd, const Address &src);
+  void ld_wu (Register rd, const Address &src);
+  void ld_w  (Register rd, const Address &src);
+  void st_b  (Register rd, const Address &dst);
+  void st_d  (Register rd, const Address &dst);
+  void st_w  (Register rd, const Address &dst);
+  void sc_w  (Register rd, const Address &dst);
+  void sc_d  (Register rd, const Address &dst);
+  void st_h  (Register rd, const Address &dst);
+  void fld_s (FloatRegister fd, const Address &src);
+  void fld_d (FloatRegister fd, const Address &src);
+  void fst_s (FloatRegister fd, const Address &dst);
+  void fst_d (FloatRegister fd, const Address &dst);
 
   void amswap_w   (Register rd, Register rk, Register rj) { assert_different_registers(rd, rj); assert_different_registers(rd, rk); emit_int32(insn_RRR(amswap_w_op,    (int)rk->encoding(), (int)rj->encoding(), (int)rd->encoding())); }
   void amswap_d   (Register rd, Register rk, Register rj) { assert_different_registers(rd, rj); assert_different_registers(rd, rk); emit_int32(insn_RRR(amswap_d_op,    (int)rk->encoding(), (int)rj->encoding(), (int)rd->encoding())); }

src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp

@@ -588,7 +588,7 @@ void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type,
   LIR_Const* c = src->as_constant_ptr();
   LIR_Address* to_addr = dest->as_address_ptr();
 
-  void (Assembler::* insn)(Register Rt, Address adr);
+  void (Assembler::* insn)(Register Rt, const Address &adr);
 
   switch (type) {
   case T_ADDRESS:

src/hotspot/cpu/loongarch/c2_MacroAssembler_loongarch.cpp

@@ -265,7 +265,7 @@ void C2_MacroAssembler::bc1f_long(Label& L) {
   bind(not_taken);
 }
 
-typedef void (MacroAssembler::* load_chr_insn)(Register rd, Address adr);
+typedef void (MacroAssembler::* load_chr_insn)(Register rd, const Address &adr);
 
 void C2_MacroAssembler::string_indexof(Register haystack, Register needle,
                                        Register haystack_len, Register needle_len,

src/hotspot/cpu/loongarch/frame_loongarch.inline.hpp

@@ -368,7 +368,7 @@ frame frame::sender_for_compiled_frame(RegisterMap* map) const {
   // in C2 code but it will have been pushed onto the stack. so we
   // have to find it relative to the unextended sp
 
-  assert(_cb->frame_size() >= 0, "must have non-zero frame size");
+  assert(_cb->frame_size() > 0, "must have non-zero frame size");
   intptr_t* l_sender_sp = unextended_sp() + _cb->frame_size();
   intptr_t* unextended_sp = l_sender_sp;
 

src/hotspot/cpu/loongarch/gc/shared/barrierSetAssembler_loongarch.cpp

@@ -281,7 +281,7 @@ void BarrierSetAssembler::nmethod_entry_barrier(MacroAssembler* masm, Label* slo
         __ srli_d(RA, SCR1, 32);
         __ orr(SCR2, SCR2, RA);
         // Read the global epoch value.
-        __ ld_wu(SCR2, SCR2);
+        __ ld_wu(SCR2, SCR2, 0);
         // Combine the guard value (low order) with the epoch value (high order).
         __ slli_d(SCR2, SCR2, 32);
         __ orr(SCR1, SCR1, SCR2);
@@ -305,7 +305,8 @@ void BarrierSetAssembler::nmethod_entry_barrier(MacroAssembler* masm, Label* slo
     __ emit_int32(0);   // nmethod guard value. Skipped over in common case.
     __ bind(skip_barrier);
   } else {
-    __ bne(SCR1, SCR2, *slow_path);
+    __ xorr(SCR1, SCR1, SCR2);
+    __ bnez(SCR1, *slow_path);
     __ bind(*continuation);
   }
 }

src/hotspot/cpu/loongarch/gc/shared/barrierSetNMethod_loongarch.cpp

@@ -40,7 +40,7 @@
 static int slow_path_size(nmethod* nm) {
   // The slow path code is out of line with C2.
   // Leave a b to the stub in the fast path.
-  return nm->is_compiled_by_c2() ? 1 : 6;
+  return nm->is_compiled_by_c2() ? 2 : 6;
 }
 
 static int entry_barrier_offset(nmethod* nm) {

src/hotspot/cpu/loongarch/macroAssembler_loongarch.cpp

@@ -79,50 +79,6 @@
 
 // Implementation of MacroAssembler
 
-intptr_t MacroAssembler::i[32] = {0};
-float MacroAssembler::f[32] = {0.0};
-
-void MacroAssembler::print(outputStream *s) {
-  unsigned int k;
-  for(k=0; k<sizeof(i)/sizeof(i[0]); k++) {
-    s->print_cr("i%d = 0x%.16lx", k, i[k]);
-  }
-  s->cr();
-
-  for(k=0; k<sizeof(f)/sizeof(f[0]); k++) {
-    s->print_cr("f%d = %f", k, f[k]);
-  }
-  s->cr();
-}
-
-int MacroAssembler::i_offset(unsigned int k) { return (intptr_t)&((MacroAssembler*)0)->i[k]; }
-int MacroAssembler::f_offset(unsigned int k) { return (intptr_t)&((MacroAssembler*)0)->f[k]; }
-
-void MacroAssembler::save_registers(MacroAssembler *masm) {
-#define __ masm->
-  for(int k=0; k<32; k++) {
-    __ st_w (as_Register(k), A0, i_offset(k));
-  }
-
-  for(int k=0; k<32; k++) {
-    __ fst_s (as_FloatRegister(k), A0, f_offset(k));
-  }
-#undef __
-}
-
-void MacroAssembler::restore_registers(MacroAssembler *masm) {
-#define __ masm->
-  for(int k=0; k<32; k++) {
-    __ ld_w (as_Register(k), A0, i_offset(k));
-  }
-
-  for(int k=0; k<32; k++) {
-    __ fld_s (as_FloatRegister(k), A0, f_offset(k));
-  }
-#undef __
-}
-
-
 void MacroAssembler::pd_patch_instruction(address branch, address target, const char* file, int line) {
   jint& stub_inst = *(jint*)branch;
   jint *pc = (jint *)branch;
@@ -960,11 +916,10 @@ void MacroAssembler::super_call_VM_leaf(address entry_point,
   MacroAssembler::call_VM_leaf_base(entry_point, 3);
 }
 
-void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
-}
+// these are no-ops overridden by InterpreterMacroAssembler
+void MacroAssembler::check_and_handle_earlyret(Register java_thread) {}
 
-void MacroAssembler::check_and_handle_popframe(Register java_thread) {
-}
+void MacroAssembler::check_and_handle_popframe(Register java_thread) {}
 
 void MacroAssembler::null_check(Register reg, int offset) {
   if (needs_explicit_null_check(offset)) {
@@ -1470,14 +1425,6 @@ void MacroAssembler::verify_tlab(Register t1, Register t2) {
 #endif
 }
 
-RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
-                                                      Register tmp,
-                                                      int offset) {
-  //TODO: LA
-  guarantee(0, "LA not implemented yet");
-  return RegisterOrConstant(tmp);
-}
-
 void MacroAssembler::bswap_h(Register dst, Register src) {
   revb_2h(dst, src);
   ext_w_h(dst, dst);  // sign extension of the lower 16 bits
@@ -1611,27 +1558,10 @@ void MacroAssembler::cmpxchg32(Address addr, Register oldval, Register newval, R
     b(*fail);
 }
 
-// be sure the three register is different
-void MacroAssembler::rem_s(FloatRegister fd, FloatRegister fs, FloatRegister ft, FloatRegister tmp) {
-  //TODO: LA
-  guarantee(0, "LA not implemented yet");
-}
-
-// be sure the three register is different
-void MacroAssembler::rem_d(FloatRegister fd, FloatRegister fs, FloatRegister ft, FloatRegister tmp) {
-  //TODO: LA
-  guarantee(0, "LA not implemented yet");
-}
-
 void MacroAssembler::align(int modulus) {
   while (offset() % modulus != 0) nop();
 }
 
-
-void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
-  //Unimplemented();
-}
-
 static RegSet caller_saved_regset = RegSet::range(A0, A7) + RegSet::range(T0, T8) + RegSet::of(FP, RA) - RegSet::of(SCR1, SCR2);
 static FloatRegSet caller_saved_fpu_regset = FloatRegSet::range(F0, F23);
 
@@ -2663,14 +2593,15 @@ int MacroAssembler::patched_branch(int dest_pos, int inst, int inst_pos) {
   case bge_op:
   case bltu_op:
   case bgeu_op:
-    assert(is_simm16(v), "must be simm16");
 #ifndef PRODUCT
     if(!is_simm16(v))
     {
       tty->print_cr("must be simm16");
       tty->print_cr("Inst: %x", inst);
+      tty->print_cr("Op:   %x", high(inst, 6));
     }
 #endif
+    assert(is_simm16(v), "must be simm16");
 
     inst &= 0xfc0003ff;
     inst |= ((v & 0xffff) << 10);