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loongson-jvmloongson-jvm
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Update (2023.09.19)
30718: Implement PopulateIndex 30721: Implement SignumF/D and SignumVF/D
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‎src/hotspot/cpu/loongarch/loongarch_64.ad‎

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@@ -9971,6 +9971,34 @@ instruct copySignD_reg(regD dst, regD src1, regD src2, immD_0 zero) %{
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ins_pipe( fpu_arith );
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%}
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instruct signumF_reg(regF dst, regF src, regF zero, regF one, regF tmp) %{
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match(Set dst (SignumF src (Binary zero one)));
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effect(TEMP_DEF dst, TEMP tmp);
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format %{ "signumF $dst, $src, $zero, $one\t# TEMP($tmp) @signumF_reg" %}
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ins_encode %{
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__ fcmp_clt_s(FCC0, $zero$$FloatRegister, $src$$FloatRegister);
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__ fsel($dst$$FloatRegister, $src$$FloatRegister, $one$$FloatRegister, FCC0);
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__ fcmp_clt_s(FCC0, $src$$FloatRegister, $zero$$FloatRegister);
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__ fneg_s($tmp$$FloatRegister, $one$$FloatRegister);
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__ fsel($dst$$FloatRegister, $dst$$FloatRegister, $tmp$$FloatRegister, FCC0);
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%}
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ins_pipe( pipe_slow );
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%}
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instruct signumD_reg(regD dst, regD src, regD zero, regD one, regD tmp) %{
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match(Set dst (SignumD src (Binary zero one)));
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effect(TEMP_DEF dst, TEMP tmp);
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format %{ "signumF $dst, $src, $zero, $one\t# TEMP($tmp) @signumD_reg" %}
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ins_encode %{
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__ fcmp_clt_d(FCC0, $zero$$FloatRegister, $src$$FloatRegister);
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__ fsel($dst$$FloatRegister, $src$$FloatRegister, $one$$FloatRegister, FCC0);
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__ fcmp_clt_d(FCC0, $src$$FloatRegister, $zero$$FloatRegister);
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__ fneg_d($tmp$$FloatRegister, $one$$FloatRegister);
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__ fsel($dst$$FloatRegister, $dst$$FloatRegister, $tmp$$FloatRegister, FCC0);
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%}
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ins_pipe( pipe_slow );
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%}
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997410002
//----------------------------------Logical Instructions----------------------
997510003
//__________________________________Integer Logical Instructions-------------
997610004

@@ -15534,6 +15562,49 @@ instruct loadconV(vReg dst, immI_0 src) %{
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ins_pipe( pipe_slow );
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%}
1553615564

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// ------------------------------ Populate Index to a Vector ------------------
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instruct populateIndexV(vReg dst, mRegI src1, immI_1 src2) %{
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match(Set dst (PopulateIndex src1 src2));
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format %{ "(x)vpopulate_index $dst, $src1, $src2\t# @populateIndexV" %}
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ins_encode %{
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assert($src2$$constant == 1, "required");
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BasicType bt = Matcher::vector_element_basic_type(this);
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int offset = exact_log2(type2aelembytes(bt)) << 5;
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__ li(AT, (long)(StubRoutines::la::vector_iota_indices() + offset));
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if (Matcher::vector_length_in_bytes(this) > 16) {
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__ xvld(fscratch, AT, (int)0);
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switch (bt) {
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case T_BYTE : __ xvreplgr2vr_b($dst$$FloatRegister, $src1$$Register);
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__ xvadd_b($dst$$FloatRegister, $dst$$FloatRegister, fscratch); break;
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case T_SHORT : __ xvreplgr2vr_h($dst$$FloatRegister, $src1$$Register);
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__ xvadd_h($dst$$FloatRegister, $dst$$FloatRegister, fscratch); break;
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case T_INT : __ xvreplgr2vr_w($dst$$FloatRegister, $src1$$Register);
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__ xvadd_w($dst$$FloatRegister, $dst$$FloatRegister, fscratch); break;
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case T_LONG : __ xvreplgr2vr_d($dst$$FloatRegister, $src1$$Register);
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__ xvadd_d($dst$$FloatRegister, $dst$$FloatRegister, fscratch); break;
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default:
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ShouldNotReachHere();
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}
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} else {
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__ vld(fscratch, AT, (int)0);
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switch (bt) {
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case T_BYTE : __ vreplgr2vr_b($dst$$FloatRegister, $src1$$Register);
15593+
__ vadd_b($dst$$FloatRegister, $dst$$FloatRegister, fscratch); break;
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case T_SHORT : __ vreplgr2vr_h($dst$$FloatRegister, $src1$$Register);
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__ vadd_h($dst$$FloatRegister, $dst$$FloatRegister, fscratch); break;
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case T_INT : __ vreplgr2vr_w($dst$$FloatRegister, $src1$$Register);
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__ vadd_w($dst$$FloatRegister, $dst$$FloatRegister, fscratch); break;
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case T_LONG : __ vreplgr2vr_d($dst$$FloatRegister, $src1$$Register);
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__ vadd_d($dst$$FloatRegister, $dst$$FloatRegister, fscratch); break;
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default:
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ShouldNotReachHere();
15602+
}
15603+
}
15604+
%}
15605+
ins_pipe( pipe_slow );
15606+
%}
15607+
1553715608
// ---------------------------- LOAD_SHUFFLE ----------------------------------
1553815609

1553915610
instruct loadShuffleVB(vReg dst) %{
@@ -15659,6 +15730,51 @@ instruct clzV(vReg dst, vReg src) %{
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ins_pipe( pipe_slow );
1566015731
%}
1566115732

15733+
// ------------------------------ Vector signum --------------------------------
15734+
15735+
instruct signumV(vReg dst, vReg src, vReg zero, vReg one, vReg tmp) %{
15736+
match(Set dst (SignumVF src (Binary zero one)));
15737+
match(Set dst (SignumVD src (Binary zero one)));
15738+
effect(TEMP_DEF dst, TEMP tmp);
15739+
format %{ "(x)vsignum $dst, $src, $zero, $one\t# TEMP($tmp) @signumV" %}
15740+
ins_encode %{
15741+
if (Matcher::vector_length_in_bytes(this) > 16) {
15742+
switch (Matcher::vector_element_basic_type(this, $src)) {
15743+
case T_FLOAT: __ xvfcmp_clt_s($dst$$FloatRegister, $zero$$FloatRegister, $src$$FloatRegister);
15744+
__ xvfcmp_clt_s($tmp$$FloatRegister, $src$$FloatRegister, $zero$$FloatRegister);
15745+
__ xvor_v($dst$$FloatRegister, $dst$$FloatRegister, $tmp$$FloatRegister);
15746+
__ xvsrli_w($dst$$FloatRegister, $dst$$FloatRegister, 1);
15747+
break;
15748+
case T_DOUBLE: __ xvfcmp_clt_d($dst$$FloatRegister, $zero$$FloatRegister, $src$$FloatRegister);
15749+
__ xvfcmp_clt_d($tmp$$FloatRegister, $src$$FloatRegister, $zero$$FloatRegister);
15750+
__ xvor_v($dst$$FloatRegister, $dst$$FloatRegister, $tmp$$FloatRegister);
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__ xvsrli_d($dst$$FloatRegister, $dst$$FloatRegister, 1);
15752+
break;
15753+
default:
15754+
ShouldNotReachHere();
15755+
}
15756+
__ xvbitsel_v($dst$$FloatRegister, $src$$FloatRegister, $one$$FloatRegister, $dst$$FloatRegister);
15757+
} else {
15758+
switch (Matcher::vector_element_basic_type(this, $src)) {
15759+
case T_FLOAT: __ vfcmp_clt_s($dst$$FloatRegister, $zero$$FloatRegister, $src$$FloatRegister);
15760+
__ vfcmp_clt_s($tmp$$FloatRegister, $src$$FloatRegister, $zero$$FloatRegister);
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__ vor_v($dst$$FloatRegister, $dst$$FloatRegister, $tmp$$FloatRegister);
15762+
__ vsrli_w($dst$$FloatRegister, $dst$$FloatRegister, 1);
15763+
break;
15764+
case T_DOUBLE: __ vfcmp_clt_d($dst$$FloatRegister, $zero$$FloatRegister, $src$$FloatRegister);
15765+
__ vfcmp_clt_d($tmp$$FloatRegister, $src$$FloatRegister, $zero$$FloatRegister);
15766+
__ vor_v($dst$$FloatRegister, $dst$$FloatRegister, $tmp$$FloatRegister);
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__ vsrli_d($dst$$FloatRegister, $dst$$FloatRegister, 1);
15768+
break;
15769+
default:
15770+
ShouldNotReachHere();
15771+
}
15772+
__ vbitsel_v($dst$$FloatRegister, $src$$FloatRegister, $one$$FloatRegister, $dst$$FloatRegister);
15773+
}
15774+
%}
15775+
ins_pipe(pipe_slow);
15776+
%}
15777+
1566215778

1566315779
//----------PEEPHOLE RULES-----------------------------------------------------
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// These must follow all instruction definitions as they use the names

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