|
22 | 22 | * |
23 | 23 | */ |
24 | 24 |
|
| 25 | +/* |
| 26 | + * This file has been modified by Loongson Technology in 2023, These |
| 27 | + * modifications are Copyright (c) 2023, Loongson Technology, and are made |
| 28 | + * available on the same license terms set forth above. |
| 29 | + */ |
| 30 | + |
25 | 31 | #include "precompiled.hpp" |
26 | 32 | #include "gc/shared/tlab_globals.hpp" |
27 | 33 | #include "gc/shared/c2/barrierSetC2.hpp" |
@@ -263,6 +269,8 @@ class C2AccessFence: public StackObj { |
263 | 269 |
|
264 | 270 | bool is_volatile = (decorators & MO_SEQ_CST) != 0; |
265 | 271 | bool is_acquire = (decorators & MO_ACQUIRE) != 0; |
| 272 | + bool is_relaxed = (decorators & MO_RELAXED) != 0; |
| 273 | + bool is_unsafe = (decorators & C2_UNSAFE_ACCESS) != 0; |
266 | 274 |
|
267 | 275 | // If reference is volatile, prevent following volatiles ops from |
268 | 276 | // floating up before the volatile access. |
@@ -296,6 +304,13 @@ class C2AccessFence: public StackObj { |
296 | 304 | assert(_leading_membar == nullptr || support_IRIW_for_not_multiple_copy_atomic_cpu, "no leading membar expected"); |
297 | 305 | Node* mb = kit->insert_mem_bar(Op_MemBarAcquire, n); |
298 | 306 | mb->as_MemBar()->set_trailing_load(); |
| 307 | + } else if (is_relaxed && is_unsafe) { |
| 308 | +#ifdef LOONGARCH64 |
| 309 | + assert(kit != nullptr, "unsupported at optimization time"); |
| 310 | + Node* n = _access.raw_access(); |
| 311 | + Node* mb = kit->insert_mem_bar(Op_SameAddrLoadFence, n); |
| 312 | + mb->as_MemBar()->set_trailing_load(); |
| 313 | +#endif |
299 | 314 | } |
300 | 315 | } |
301 | 316 | } |
|
0 commit comments