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loongson-jvmloongson-jvm
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Update (2023.12.08)
29494: Fix assert(_succ != current) failed: invariant 32796: Rethinking the ties-to-positive round mode 32874: Amend 30985: Insert acqure membar for load-exclusive with acquire to fix typo 32611: Remove unnecessary initialize constant pool for native wrapper 24942: 8316563: test tools/jpackage/linux/LinuxResourceTest.java fails on CentOS Linux release 8.5.2111 and Fedora 27 32758: Multiple uses of register t7
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-33
lines changed

11 files changed

+334
-33
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‎src/hotspot/cpu/loongarch/assembler_loongarch.hpp‎

Lines changed: 62 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -954,6 +954,10 @@ class Assembler : public AbstractAssembler {
954954
vshuf_h_op = 0b01110001011110101,
955955
vshuf_w_op = 0b01110001011110110,
956956
vshuf_d_op = 0b01110001011110111,
957+
vslti_b_op = 0b01110010100001100,
958+
vslti_h_op = 0b01110010100001101,
959+
vslti_w_op = 0b01110010100001110,
960+
vslti_d_op = 0b01110010100001111,
957961
vslti_bu_op = 0b01110010100010000,
958962
vslti_hu_op = 0b01110010100010001,
959963
vslti_wu_op = 0b01110010100010010,
@@ -1130,6 +1134,10 @@ class Assembler : public AbstractAssembler {
11301134
xvshuf_w_op = 0b01110101011110110,
11311135
xvshuf_d_op = 0b01110101011110111,
11321136
xvperm_w_op = 0b01110101011111010,
1137+
xvslti_b_op = 0b01110110100001100,
1138+
xvslti_h_op = 0b01110110100001101,
1139+
xvslti_w_op = 0b01110110100001110,
1140+
xvslti_d_op = 0b01110110100001111,
11331141
xvslti_bu_op = 0b01110110100010000,
11341142
xvslti_hu_op = 0b01110110100010001,
11351143
xvslti_wu_op = 0b01110110100010010,
@@ -1221,6 +1229,14 @@ class Assembler : public AbstractAssembler {
12211229
unknow_ops14 = 0b11111111111111
12221230
};
12231231

1232+
// 13-bit opcode, highest 13 bits: bits[31...19]
1233+
enum ops13 {
1234+
vldrepl_d_op = 0b0011000000010,
1235+
xvldrepl_d_op = 0b0011001000010,
1236+
1237+
unknow_ops13 = 0b1111111111111
1238+
};
1239+
12241240
// 12-bit opcode, highest 12 bits: bits[31...20]
12251241
enum ops12 {
12261242
fmadd_s_op = 0b000010000001,
@@ -1258,10 +1274,20 @@ class Assembler : public AbstractAssembler {
12581274
xvbitsel_v_op = 0b000011010010,
12591275
vshuf_b_op = 0b000011010101,
12601276
xvshuf_b_op = 0b000011010110,
1277+
vldrepl_w_op = 0b001100000010,
1278+
xvldrepl_w_op = 0b001100100010,
12611279

12621280
unknow_ops12 = 0b111111111111
12631281
};
12641282

1283+
// 11-bit opcode, highest 11 bits: bits[31...21]
1284+
enum ops11 {
1285+
vldrepl_h_op = 0b00110000010,
1286+
xvldrepl_h_op = 0b00110010010,
1287+
1288+
unknow_ops11 = 0b11111111111
1289+
};
1290+
12651291
// 10-bit opcode, highest 10 bits: bits[31...22]
12661292
enum ops10 {
12671293
bstr_w_op = 0b0000000001,
@@ -1297,6 +1323,8 @@ class Assembler : public AbstractAssembler {
12971323
xvst_op = 0b0010110011,
12981324
ldl_w_op = 0b0010111000,
12991325
ldr_w_op = 0b0010111001,
1326+
vldrepl_b_op = 0b0011000010,
1327+
xvldrepl_b_op = 0b0011001010,
13001328

13011329
unknow_ops10 = 0b1111111111
13021330
};
@@ -1475,10 +1503,25 @@ class Assembler : public AbstractAssembler {
14751503
// | opcode | I8 | rj | rd |
14761504
static inline int insn_I8RR (int op, int imm8, int rj, int rd) { /*assert(is_simm(imm8, 8), "not a signed 8-bit int");*/ return (op<<18) | (low(imm8, 8)<<10) | (rj<<5) | rd; }
14771505

1506+
// 2RI9-type
1507+
// 31 19 18 10 9 5 4 0
1508+
// | opcode | I9 | rj | vd |
1509+
static inline int insn_I9RR(int op, int imm9, int rj, int vd) { return (op<<19) | (low(imm9, 9)<<10) | (rj<<5) | vd; }
1510+
1511+
// 2RI10-type
1512+
// 31 20 19 10 9 5 4 0
1513+
// | opcode | I10 | rj | vd |
1514+
static inline int insn_I10RR(int op, int imm10, int rj, int vd) { return (op<<20) | (low(imm10, 10)<<10) | (rj<<5) | vd; }
1515+
1516+
// 2RI11-type
1517+
// 31 21 20 10 9 5 4 0
1518+
// | opcode | I11 | rj | vd |
1519+
static inline int insn_I11RR(int op, int imm11, int rj, int vd) { return (op<<21) | (low(imm11, 11)<<10) | (rj<<5) | vd; }
1520+
14781521
// 2RI12-type
14791522
// 31 22 21 10 9 5 4 0
14801523
// | opcode | I12 | rj | rd |
1481-
static inline int insn_I12RR(int op, int imm12, int rj, int rd) { /* assert(is_simm(imm12, 12), "not a signed 12-bit int");*/ return (op<<22) | (low(imm12, 12)<<10) | (rj<<5) | rd; }
1524+
static inline int insn_I12RR(int op, int imm12, int rj, int rd) { return (op<<22) | (low(imm12, 12)<<10) | (rj<<5) | rd; }
14821525

14831526
// 2RI14-type
14841527
// 31 24 23 10 9 5 4 0
@@ -2866,6 +2909,15 @@ class Assembler : public AbstractAssembler {
28662909
void xvslt_wu(FloatRegister xd, FloatRegister xj, FloatRegister xk) { ASSERT_LASX emit_int32(insn_RRR(xvslt_wu_op, (int)xk->encoding(), (int)xj->encoding(), (int)xd->encoding())); }
28672910
void xvslt_du(FloatRegister xd, FloatRegister xj, FloatRegister xk) { ASSERT_LASX emit_int32(insn_RRR(xvslt_du_op, (int)xk->encoding(), (int)xj->encoding(), (int)xd->encoding())); }
28682911

2912+
void vslti_b(FloatRegister vd, FloatRegister vj, int si5) { ASSERT_LSX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR( vslti_b_op, si5, (int)vj->encoding(), (int)vd->encoding())); }
2913+
void vslti_h(FloatRegister vd, FloatRegister vj, int si5) { ASSERT_LSX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR( vslti_h_op, si5, (int)vj->encoding(), (int)vd->encoding())); }
2914+
void vslti_w(FloatRegister vd, FloatRegister vj, int si5) { ASSERT_LSX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR( vslti_w_op, si5, (int)vj->encoding(), (int)vd->encoding())); }
2915+
void vslti_d(FloatRegister vd, FloatRegister vj, int si5) { ASSERT_LSX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR( vslti_d_op, si5, (int)vj->encoding(), (int)vd->encoding())); }
2916+
void xvslti_b(FloatRegister xd, FloatRegister xj, int si5) { ASSERT_LASX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR(xvslti_b_op, si5, (int)xj->encoding(), (int)xd->encoding())); }
2917+
void xvslti_h(FloatRegister xd, FloatRegister xj, int si5) { ASSERT_LASX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR(xvslti_h_op, si5, (int)xj->encoding(), (int)xd->encoding())); }
2918+
void xvslti_w(FloatRegister xd, FloatRegister xj, int si5) { ASSERT_LASX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR(xvslti_w_op, si5, (int)xj->encoding(), (int)xd->encoding())); }
2919+
void xvslti_d(FloatRegister xd, FloatRegister xj, int si5) { ASSERT_LASX assert(is_simm(si5, 5), "not a signed 5-bit int"); emit_int32(insn_I5RR(xvslti_d_op, si5, (int)xj->encoding(), (int)xd->encoding())); }
2920+
28692921
void vslti_bu(FloatRegister vd, FloatRegister vj, int ui5) { ASSERT_LSX emit_int32(insn_I5RR( vslti_bu_op, ui5, (int)vj->encoding(), (int)vd->encoding())); }
28702922
void vslti_hu(FloatRegister vd, FloatRegister vj, int ui5) { ASSERT_LSX emit_int32(insn_I5RR( vslti_hu_op, ui5, (int)vj->encoding(), (int)vd->encoding())); }
28712923
void vslti_wu(FloatRegister vd, FloatRegister vj, int ui5) { ASSERT_LSX emit_int32(insn_I5RR( vslti_wu_op, ui5, (int)vj->encoding(), (int)vd->encoding())); }
@@ -3104,6 +3156,15 @@ class Assembler : public AbstractAssembler {
31043156
void vstx(FloatRegister vd, Register rj, Register rk) { ASSERT_LSX emit_int32(insn_RRR( vstx_op, (int)rk->encoding(), (int)rj->encoding(), (int)vd->encoding())); }
31053157
void xvstx(FloatRegister xd, Register rj, Register rk) { ASSERT_LASX emit_int32(insn_RRR(xvstx_op, (int)rk->encoding(), (int)rj->encoding(), (int)xd->encoding())); }
31063158

3159+
void vldrepl_d(FloatRegister vd, Register rj, int si9) { ASSERT_LSX assert(is_simm(si9, 9), "not a signed 9-bit int"); emit_int32(insn_I9RR( vldrepl_d_op, si9, (int)rj->encoding(), (int)vd->encoding()));}
3160+
void vldrepl_w(FloatRegister vd, Register rj, int si10) { ASSERT_LSX assert(is_simm(si10, 10), "not a signed 10-bit int"); emit_int32(insn_I10RR( vldrepl_w_op, si10, (int)rj->encoding(), (int)vd->encoding()));}
3161+
void vldrepl_h(FloatRegister vd, Register rj, int si11) { ASSERT_LSX assert(is_simm(si11, 11), "not a signed 11-bit int"); emit_int32(insn_I11RR( vldrepl_h_op, si11, (int)rj->encoding(), (int)vd->encoding()));}
3162+
void vldrepl_b(FloatRegister vd, Register rj, int si12) { ASSERT_LSX assert(is_simm(si12, 12), "not a signed 12-bit int"); emit_int32(insn_I12RR( vldrepl_b_op, si12, (int)rj->encoding(), (int)vd->encoding()));}
3163+
void xvldrepl_d(FloatRegister xd, Register rj, int si9) { ASSERT_LASX assert(is_simm(si9, 9), "not a signed 9-bit int"); emit_int32(insn_I9RR(xvldrepl_d_op, si9, (int)rj->encoding(), (int)xd->encoding()));}
3164+
void xvldrepl_w(FloatRegister xd, Register rj, int si10) { ASSERT_LASX assert(is_simm(si10, 10), "not a signed 10-bit int"); emit_int32(insn_I10RR(xvldrepl_w_op, si10, (int)rj->encoding(), (int)xd->encoding()));}
3165+
void xvldrepl_h(FloatRegister xd, Register rj, int si11) { ASSERT_LASX assert(is_simm(si11, 11), "not a signed 11-bit int"); emit_int32(insn_I11RR(xvldrepl_h_op, si11, (int)rj->encoding(), (int)xd->encoding()));}
3166+
void xvldrepl_b(FloatRegister xd, Register rj, int si12) { ASSERT_LASX assert(is_simm(si12, 12), "not a signed 12-bit int"); emit_int32(insn_I12RR(xvldrepl_b_op, si12, (int)rj->encoding(), (int)xd->encoding()));}
3167+
31073168
#undef ASSERT_LSX
31083169
#undef ASSERT_LASX
31093170

‎src/hotspot/cpu/loongarch/c1_LIRAssembler_loongarch_64.cpp‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1324,7 +1324,9 @@ void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success,
13241324
__ load_klass(recv, obj);
13251325
type_profile_helper(mdo, md, data, recv, &update_done);
13261326
Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1327-
__ increment(counter_addr, DataLayout::counter_increment);
1327+
__ ld_d(SCR2, counter_addr);
1328+
__ addi_d(SCR2, SCR2, DataLayout::counter_increment);
1329+
__ st_d(SCR2, counter_addr);
13281330
__ bind(update_done);
13291331
} else {
13301332
__ beqz(obj, *obj_is_null);
@@ -1436,7 +1438,9 @@ void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
14361438
__ load_klass(recv, value);
14371439
type_profile_helper(mdo, md, data, recv, &update_done);
14381440
Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1439-
__ increment(counter_addr, DataLayout::counter_increment);
1441+
__ ld_d(SCR2, counter_addr);
1442+
__ addi_d(SCR2, SCR2, DataLayout::counter_increment);
1443+
__ st_d(SCR2, counter_addr);
14401444
__ bind(update_done);
14411445
} else {
14421446
__ beqz(value, done);

‎src/hotspot/cpu/loongarch/gc/x/x_loongarch_64.ad‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -56,12 +56,12 @@ static void x_compare_and_swap(MacroAssembler& _masm, const MachNode* node,
5656
// Weak CAS operations are thus only emitted if the barrier is elided.
5757
Address addr(mem);
5858
if (node->barrier_data() == XLoadBarrierElided) {
59-
__ cmpxchg(addr, oldval, newval, tmp, false /* retold */, acquire /* barrier */,
59+
__ cmpxchg(addr, oldval, newval, tmp, false /* retold */, acquire /* acquire */,
6060
weak /* weak */, false /* exchange */);
6161
__ move(res, tmp);
6262
} else {
6363
__ move(tmp, oldval);
64-
__ cmpxchg(addr, tmp, newval, AT, true /* retold */, acquire /* barrier */,
64+
__ cmpxchg(addr, tmp, newval, AT, true /* retold */, acquire /* acquire */,
6565
false /* weak */, false /* exchange */);
6666
__ move(res, AT);
6767

@@ -70,7 +70,7 @@ static void x_compare_and_swap(MacroAssembler& _masm, const MachNode* node,
7070
__ andr(AT, AT, tmp);
7171
__ beqz(AT, good);
7272
x_load_barrier_slow_path(_masm, node, addr, tmp, res /* used as tmp */);
73-
__ cmpxchg(addr, oldval, newval, tmp, false /* retold */, acquire /* barrier */, weak /* weak */, false /* exchange */);
73+
__ cmpxchg(addr, oldval, newval, tmp, false /* retold */, acquire /* acquire */, weak /* weak */, false /* exchange */);
7474
__ move(res, tmp);
7575
__ bind(good);
7676
}

‎src/hotspot/cpu/loongarch/loongarch_64.ad‎

Lines changed: 80 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -10870,6 +10870,28 @@ instruct convHF2F_reg_reg(regF dst, mRegI src, regF tmp) %{
1087010870
ins_pipe(pipe_slow);
1087110871
%}
1087210872

10873+
instruct round_float_reg(mRegI dst, regF src, mRegL tmp)
10874+
%{
10875+
match(Set dst (RoundF src));
10876+
effect(TEMP_DEF dst, TEMP tmp);
10877+
format %{ "round_float $dst, $src\t# @round_float_reg" %}
10878+
ins_encode %{
10879+
__ java_round_float($dst$$Register, $src$$FloatRegister, $tmp$$Register);
10880+
%}
10881+
ins_pipe( pipe_slow );
10882+
%}
10883+
10884+
instruct round_double_reg(mRegL dst, regD src, mRegL tmp)
10885+
%{
10886+
match(Set dst (RoundD src));
10887+
effect(TEMP_DEF dst, TEMP tmp);
10888+
format %{ "round_double $dst, $src\t# @round_double_reg" %}
10889+
ins_encode %{
10890+
__ java_round_double($dst$$Register, $src$$FloatRegister, $tmp$$Register);
10891+
%}
10892+
ins_pipe( pipe_slow );
10893+
%}
10894+
1087310895
instruct roundD(regD dst, regD src, immI rmode) %{
1087410896
predicate(UseLSX);
1087510897
match(Set dst (RoundDoubleMode src rmode));
@@ -12514,26 +12536,6 @@ instruct safePoint_poll_tls(mRegP poll) %{
1251412536
ins_pipe( pipe_serial );
1251512537
%}
1251612538

12517-
//----------Arithmetic Conversion Instructions---------------------------------
12518-
12519-
instruct roundFloat_nop(regF dst)
12520-
%{
12521-
match(Set dst (RoundFloat dst));
12522-
12523-
ins_cost(0);
12524-
ins_encode();
12525-
ins_pipe( empty );
12526-
%}
12527-
12528-
instruct roundDouble_nop(regD dst)
12529-
%{
12530-
match(Set dst (RoundDouble dst));
12531-
12532-
ins_cost(0);
12533-
ins_encode();
12534-
ins_pipe( empty );
12535-
%}
12536-
1253712539
//----------BSWAP Instructions-------------------------------------------------
1253812540
instruct bytes_reverse_int(mRegI dst, mRegIorL2I src) %{
1253912541
match(Set dst (ReverseBytesI src));
@@ -14223,6 +14225,64 @@ instruct reduceVD(regD dst, regD src, vReg vsrc, vReg tmp) %{
1422314225
ins_pipe( pipe_slow );
1422414226
%}
1422514227

14228+
// ------------------------------ Vector Round ---------------------------------
14229+
14230+
instruct round_float_lsx(vReg dst, vReg src, vReg vtemp1, vReg vtemp2) %{
14231+
predicate(Matcher::vector_length_in_bytes(n) <= 16);
14232+
match(Set dst (RoundVF src));
14233+
effect(TEMP_DEF dst, TEMP vtemp1, TEMP vtemp2);
14234+
format %{ "round_float_lsx $dst, $src\t# @round_float_lsx" %}
14235+
ins_encode %{
14236+
__ java_round_float_lsx($dst$$FloatRegister,
14237+
$src$$FloatRegister,
14238+
$vtemp1$$FloatRegister,
14239+
$vtemp2$$FloatRegister);
14240+
%}
14241+
ins_pipe( pipe_slow );
14242+
%}
14243+
14244+
instruct round_float_lasx(vReg dst, vReg src, vReg vtemp1, vReg vtemp2) %{
14245+
predicate(Matcher::vector_length_in_bytes(n) > 16);
14246+
match(Set dst (RoundVF src));
14247+
effect(TEMP_DEF dst, TEMP vtemp1, TEMP vtemp2);
14248+
format %{ "round_float_lasx $dst, $src\t# @round_float_lasx" %}
14249+
ins_encode %{
14250+
__ java_round_float_lasx($dst$$FloatRegister,
14251+
$src$$FloatRegister,
14252+
$vtemp1$$FloatRegister,
14253+
$vtemp2$$FloatRegister);
14254+
%}
14255+
ins_pipe( pipe_slow );
14256+
%}
14257+
14258+
instruct round_double_lsx(vReg dst, vReg src, vReg vtemp1, vReg vtemp2) %{
14259+
predicate(Matcher::vector_length_in_bytes(n) <= 16);
14260+
match(Set dst (RoundVD src));
14261+
effect(TEMP_DEF dst, TEMP vtemp1, TEMP vtemp2);
14262+
format %{ "round_double_lsx $dst, $src\t# @round_double_lsx" %}
14263+
ins_encode %{
14264+
__ java_round_double_lsx($dst$$FloatRegister,
14265+
$src$$FloatRegister,
14266+
$vtemp1$$FloatRegister,
14267+
$vtemp2$$FloatRegister);
14268+
%}
14269+
ins_pipe( pipe_slow );
14270+
%}
14271+
14272+
instruct round_double_lasx(vReg dst, vReg src, vReg vtemp1, vReg vtemp2) %{
14273+
predicate(Matcher::vector_length_in_bytes(n) > 16);
14274+
match(Set dst (RoundVD src));
14275+
effect(TEMP_DEF dst, TEMP vtemp1, TEMP vtemp2);
14276+
format %{ "round_double_lasx $dst, $src\t# @round_double_lasx" %}
14277+
ins_encode %{
14278+
__ java_round_double_lasx($dst$$FloatRegister,
14279+
$src$$FloatRegister,
14280+
$vtemp1$$FloatRegister,
14281+
$vtemp2$$FloatRegister);
14282+
%}
14283+
ins_pipe( pipe_slow );
14284+
%}
14285+
1422614286
// ------------------------------ RoundDoubleModeV ----------------------------
1422714287

1422814288
instruct roundVD(vReg dst, vReg src, immI rmode) %{

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